JPH08185386A - Integrated circuit for acoustic processing - Google Patents

Abstract

PURPOSE: To connect external memories respectively corresponding to plural function blocks by the small number of pins by allowing an acoustic processing circuit and a microcomputer circuit to share an external bus through a memory access control circuit. CONSTITUTION: A microcomputer 106 reads out a control program built in a ROM 103 through a data bus 111, an address bus 112 and a memory controller 105, scans a switch 102 and a keyboard 102 in accordance with the control program and controls a sound source block 107 through a control line group 113. The block 107 reads out PCM waveform data by stepping width corresponding to a sound level to be generated from the ROM 103 through the data bus 111, the address bus 112 and the memory controller 105, works the read data and outputs the worked data as musical waveform data. The data are discharged from a speaker 110 as sound.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sound processing integrated circuit for processing a sound signal, such as a tone generation integrated circuit used in an electronic musical instrument.

[0002]

2. Description of the Related Art Conventionally, in a sound processing system such as a sound generation system for an electronic musical instrument, a general-purpose micro-computer is used for detecting the operation state of a keyboard or a switch, controlling the sound generation, or setting the sound processing such as various effect processing. This is performed by a computer (microcomputer), and acoustic processing such as actual generation of a musical tone waveform or effect processing is performed by a dedicated sound source LSI or DSP (signal processing processor). Also, for example, the sound source L
As a waveform generation method by SI, a waveform read from an external PCM waveform ROM is generally subjected to arithmetic processing such as a filter to form a musical tone waveform. Also, DSP
For effect processing by, R for external delay
It is common to read and write waveform data to and from AM to obtain an effect-processed tone waveform.

FIG. 9 shows a block diagram of the prior art. In FIG. 9, a data bus 911 and an address bus 912
The microcomputer 903 connected to the computer has a built-in program ROM, but a data ROM and a work RAM have a data bus 911 and an address bus 912.
Are connected as a ROM 904 and a RAM 905. The microcomputer 903 is connected to the data bus 911 so that a musical sound determined by the setting state of the switch 902 connected to the microcomputer 903 is generated in response to the key depression of the keyboard 901 connected to the microcomputer 903. Sound source LSI (DSP) 90
Control 7 The sound source LSI (DSP) 907 is a PCM
The waveform data is read from the PCM ROM 906 with a step width corresponding to the pitch to be generated, and is processed to generate musical tone waveform data. Furthermore, a sound source LSI (DSP) 9
Reference numeral 07 indicates the generated tone waveform data, which is used for RA for delay.
A desired effect process is performed by reading and writing to M. The tone waveform data subjected to the effect processing is passed through the D / A converter 908 and the amplifier 909,
From the speaker 910, a sound is emitted.

[0004]

Here, the recent LSI
With the progress of technology, it has become possible to integrate a microcomputer and a plurality of functional blocks such as a sound source block on a one-chip LSI.

However, even in that case, a large-capacity memory cannot be built in the LSI, and therefore, as an external component,
ROM / RAM for microcomputer, RO for sound source
M, a RAM for delay and the like are required. Therefore, if the microcomputer and the sound source block are integrated into one chip as they are, the number of pins of the LSI becomes very large, and as a result, the unit cost of the LSI and the mounting cost increase. Have

An object of the present invention is to provide an LSI system having an optimum configuration in which an external memory corresponding to each of a plurality of functional blocks can be connected with a small number of pins.

[0007]

An integrated circuit for acoustic processing according to the present invention has the following circuits incorporated therein. First, a sound processing circuit for processing sound data is incorporated. This acoustic processing circuit is, for example, a circuit that generates acoustic waveform data by reading waveform data from a storage device (ROM 103) that is connected to an external bus and that stores data accessed by a microcomputer circuit described later in a mixed manner (sound source block). 107). Alternatively, the sound processing circuit is a storage device (RAM) that is connected to an external bus and stores data accessed by a microcomputer circuit in a mixed manner.
104) is a circuit (DSP 502) that performs acoustic processing on the acoustic waveform data by reading and writing the waveform data.

Next, a microcomputer circuit (microcomputer 106) for controlling the sound processing circuit is built in. A memory access control circuit (memory controller) for controlling memory access from the microcomputer circuit to the storage device connected to the external bus and memory access from the acoustic processing circuit to the storage device connected to the external bus and the same or different from the storage device. 105, 5
01). The memory access control circuit sets a state in which the microcomputer circuit can access the storage device connected to the external bus when the storage circuit connected to the external bus is not accessed by the sound processing circuit. When accessing the storage device connected to the external bus, the microcomputer circuit can be stopped only during a predetermined memory cycle (for example, one memory cycle), and the sound processing circuit can access the storage device connected to the external bus. Set to state.

[0009]

The sound processing circuit and the microcomputer circuit in the integrated circuit can share the external bus via the memory access control circuit. Therefore, the sound processing circuit and the microcomputer circuit can share the same storage device connected to the external bus, and the system can be configured with the minimum component configuration.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. <First Embodiment> FIG. 1 is an overall block diagram of a first embodiment of the present invention. In this embodiment, the present invention is applied to an electronic musical instrument.

The part surrounded by the broken line is a part which is made into one LSI chip. The microcomputer 106 is an R
The control program built in the OM 103 is read out via the data bus 111, the address bus 112, and the memory controller 105, and the switch 102 and the keyboard 101 are scanned according to the control program, and the tone generator block 107 is connected to the control line group 113. Control through. The sound source block 107 transfers the PCM waveform data to the data bus 11
1, address bus 112, and memory controller 10
The step width corresponding to the pitch to be generated is read from the ROM 103 via 5, and the step width is processed and output as musical tone waveform data. The tone waveform data is emitted as a tone from the speaker 110 via the D / A converter 108 and the amplifier 109.

The memory controller 105 normally outputs the data MDB and the address MAD output from the microcomputer 106 to the data bus 111 and the address bus 112, so that the ROM 103 or RA.
Access M104. As a result, the microcomputer 106, via the memory controller 105,
Read data MDB from OM103 or RA
Data MDB can be read or written to M104.

On the other hand, the sound source block 107 includes the ROM 10
When reading the waveform data from 3, the request signal REQ is output to the memory controller 105. In response to this, the memory controller 105 causes the sound source block 1
The ROM 103 is accessed by outputting the waveform address WAD output from 07 to the address bus 112. As a result, the sound source block 107 can read the waveform data WDT from the ROM 103 via the memory controller 105. At this time, the memory controller 105 outputs a wait signal WAIT to the microcomputer 106. Microcomputer 106
Becomes a stopped state (NOP state) while the wait signal WAIT is output.

FIG. 2 shows the microcomputer 10 of FIG.
It is a block diagram of FIG. The microcomputer 106 includes a CPU unit surrounded by a broken line in the center, a RAM 203, a timer 206, a port 209, and a bus controller 201.

The CPU section has a register (OPR) 204 for holding an operation code, a state counter (STCNT) 208 which is the basis of CPU operation, an instruction decoder (INSDEC) 205, and an AND gate 2.
07, and an operation block 202 for executing an arithmetic logic operation
Consists of

The AND gate 207 uses the clock CK0 as the clock CKST when the wait signal WAIT input from the memory controller 105 of FIG.
Blocking the input to 8 puts the CPU operation into a wait state.

FIG. 4 shows an operation timing chart of the first embodiment. In the basic clock group of FIG. 4 (a), the clock XTAL is a crystal oscillation clock. Clock C
K0 and CK0D are clocks obtained by dividing the clock XTAL. The clocks T1 and T2 are clocks obtained by dividing the clock CK0, and the clock T1D is a clock that is set in synchronization with the falling edge of the clock CK0D and that is output from a flip-flop (not shown).

FIG. 4 (b) shows the timing when the request signal REQ is not output from the sound source block 107 of FIG. 1 (at the low level). In this case, the clock CKST is constantly input to the state counter 208 of FIG. 2 via the AND gate 207.
Then, in the example of FIG. 4B, “STA” of FIG.
2 after the N-state instruction, as shown as "TE"
State instruction is being executed. In this embodiment,
Since the opcode of the instruction to be executed next in the final state of each instruction is fetched, the memory cycle M
CYCL is as shown in FIG. 4 (b). Therefore, the content of the register (OPR) 204 for holding the operation code is the clock C shown in FIG.
In synchronization with the KOP, it changes as shown in FIG. 4 (b).

FIG. 4C shows the timing when the sound source block 107 of FIG. 2 outputs the request signal REQ (at the high level). Also, FIG.
FIG. 3 is a configuration diagram of the memory controller 105 in FIG. 1.

The request signal REQ and the waveform address WAD output from the tone generator block 107 are as shown in FIG.
As shown in (c), it changes in synchronization with the clock T1. The address selector (ADS) 301 in FIG. 3 is switched by the request signal REQ, and as shown in FIG. 4 (c), the waveform address WAD is output to the address bus 112 in FIG. 1 only while the request signal REQ is at the high level. It

The request signal REQ is delayed by a flip-flop (FF) 303 set by a clock obtained by inverting the clock CK0D shown in FIG. 4A by the inverter 302 of FIG. As a result, the flip-flop 303 outputs the wait signal WAIT shown in FIG. 4C to the microcomputer 106 shown in FIG.

The waveform data register (WVR) 305 is
As shown in FIG. 4C, the wait signal WAIT, the clock T1D, and the clock CK0 are output from the AND gate 304.
The waveform data WDT is fetched from the ROM 103 of FIG. 1 via the data bus 111 in synchronization with the clock CKWV obtained as the output of the logical product of

On the other hand, in the microcomputer 106 having the configuration of FIG. 2 which receives the high level wait signal WAIT from the flip-flop 303 of FIG. 3, the AND gate 207 blocks the output of the clock CKST. Therefore, during this period, "STATE" in Fig. 4 (c)
CPU operation is N
It becomes the OP state. The microcomputer 106
Is a clock CK input to the state counter 208
Since it operates based on ST, CPU for only 2 states
The operation will be frozen. Therefore, “W” in FIG.
As shown as "AVE", the access to the ROM 103 in FIG. 1 is the access to the waveform data WDT only during the period when the request signal REQ is at the high level, and the access to the normal opcode or the like by the microcomputer 106 during the other periods. As a result, the waveform data WDT can be read into the sound source block 107 with a minimum weight for the microcomputer 106.

In the tone generator block 107, the request signal REQ and the waveform address WA output by the tone generator block 107.
If the condition that D is synchronized with the clock T1 as shown in FIGS. 4A and 4C is satisfied, the conventional sound source block can be used as it is as the sound source block 107 in FIG. <Second Embodiment> FIG. 5 is an overall block diagram of a second embodiment of the present invention. The configuration of FIG. 5 is different from the configuration of the first embodiment of FIG. 1 in that the configuration of FIG. 1 is realized as an electronic musical instrument, while the configuration of FIG. 5 is an A / D converter 503.
This is realized as an effector that adds a delay effect to an input audio signal input via the. Then, the sound source block 107 is replaced with a DSP (Signal Processor) 502, and the memory controller 5 in FIG.
The configuration of 01 is slightly different from the configuration of the memory controller 105 in FIG. In FIG. 5, the parts with the same numbers as in FIG. 1 have the same functions as in FIG.

In FIG. 5, the part surrounded by the broken line is LS.
This is a part that is made into one chip in I. The microcomputer 106 reads out the control program stored in the ROM 103 via the data bus 111, the address bus 112, and the memory controller 105, scans the switch 102 in accordance with the control program, and the DSP 50
2 is controlled via the control line group 504. DSP502
Reads the delayed waveform data from the delay area of the RAM 104 via the data bus 111, the address bus 112, and the memory controller 105, writes new waveform data to the delay area of the RAM 104, and reads the waveform data. The waveform data is mixed with the waveform data input from the A / D converter 503. The mixed waveform data is emitted from the speaker 110 via the D / A converter 108 and the amplifier 109 as effect-processed sound.

The memory controller 105 normally outputs the data MDB and the address MAD output from the microcomputer 106 to the data bus 111 and the address bus 112, so that the ROM 103 or RA.
Access M104. As a result, the microcomputer 106, via the memory controller 105,
Read data MDB from OM103 or RA
Data MDB can be read or written to M104.

On the other hand, the DSP 502 outputs a request signal REQ and a read / write signal R / W instructing read or write to the memory controller 105 when the waveform data is read or written in the RAM 104. In response to this, the memory controller 105
By outputting the waveform address WAD output from the DSP 502 to the address bus 112, the RAM 10
4 is accessed. As a result, the DSP 502 can read or write the waveform data in the delay area of the RAM 104 via the memory controller 105. At this time, the memory controller 105 outputs a wait signal WAIT to the microcomputer 106. The microcomputer 106 outputs the weight signal W
While AIT is being output, it is in a stopped state (NOP state).

The structure of the microcomputer 106 of FIG. 1 is similar to that of FIG. 2 relating to the first embodiment. 7 and 8 show operation timing charts of the second embodiment. In FIGS. 7 and 8, signals having the same symbols as those in FIG. 4 relating to the first embodiment have the same functions as in FIG.

First, the basic clock group of FIG. 7 (a) or FIG. 8 (a) is the same as the basic clock group of FIG. 4 (a). Next, FIG. 7B shows the case where the request signal REQ is not output from the DSP 502 of FIG. 5 (in the case of low level).
The timing is the same as in the case of FIG. 4 (b).

In FIG. 7 (c), the request signal REQ is output from the DSP 502 of FIG. 2 (at high level),
If the read / write signal R / W is at high level (D
This is the timing when the SP 502 performs read access to the RAM 104). 6 is a block diagram of the memory controller 501 of FIG. In FIG. 6, the parts with the same numbers as in FIG. 3 have the same functions as in FIG.

The request signal REQ, the read / write signal R / W, and the waveform address WAD output from the DSP 502 change in synchronization with the clock T1 as shown in FIGS. 7 (a) and 7 (c).

The request selector REQ switches the address selector (ADS) 301 shown in FIG.
As shown in (c), the waveform address WAD is output to the address bus 112 of FIG. 5 only while the request signal REQ is at the high level.

The request signal REQ is delayed by a flip-flop (FF) 303 set by a clock obtained by inverting the clock CK0D shown in FIG. 7A by the inverter 302 of FIG. As a result, the flip-flop 303 outputs the wait signal WAIT shown in FIG. 7C to the microcomputer 106 shown in FIG.

The waveform data register (WVR) 305 is
As shown in FIG. 7C, the wait signal WAIT, the clock T1D, and the clock CK0 are output from the AND gate 602.
And R of FIG. 5 in synchronization with the clock CKWV obtained as the output of the logical product of the inverted signal of the read / write signal R / W.
The waveform data WDTI is fetched from the AM 104 via the data bus 111.

On the other hand, the operation in which the microcomputer 106 having the configuration of FIG. 2 which receives the high-level wait signal WAIT from the flip-flop 303 of FIG. 6 enters the NOP state is as shown in FIG. 7 (c). This is exactly the same as the case of FIG. 4 (c) relating to the first embodiment. As a result,
The waveform data WDTI is transferred from the RAM 104 to the DSP 50 with a minimum weight for the microcomputer 106.
Can be read in 2.

In FIG. 8B, the request signal REQ is output from the DSP 502 of FIG. 2 (at the high level),
When the read / write signal R / W is at low level (D
This is the timing in the case where the SP 502 performs write access to the RAM 104).

The basic operation is the same as in the case of read access shown in FIG. 7C, but in the case of write access,
An AND gate 60 based on the low level read / write signal R / W and the low level clock T1 (FIG. 8 (a)).
1 through the gate 603 which is turned on in synchronization with the high level signal output from the DSP 1, and the data bus 111.
Waveform data WDTO from 02 to RAM 104 in FIG.
It is output at the timing shown as "WRITE DATA" in (b). This waveform data WDTO is shown in FIG.
It is written in the delay area of the RAM 104 at the rising timing of the signal shown as "WRB" in (b). The operation in which the microcomputer 106 having the configuration of FIG. 2 which receives the high-level wait signal WAIT from the flip-flop 303 of FIG.
As shown in FIG. 8 (b), this is exactly the same as FIG. 8 (c) or the case of FIG. 4 (c) relating to the first embodiment. As a result,
The waveform data WDTO is transferred from the DSP 502 to the RAM 10 with minimum weight for the microcomputer 106.
4 can be written.

As in the case of the sound source block 107 in the first embodiment, the DSP 5 in the second embodiment is
02, the request signal RE that it outputs
Q, read / write signal R / W, and waveform address WA
If the condition that D is synchronized with the clock T1 is satisfied, the DSP block of FIG.
It can be used as 2.

[0039]

According to the present invention, the sound processing circuit and the microcomputer circuit in the integrated circuit can share the external bus via the memory access control circuit. Therefore, it becomes possible to hold the data required for each with a small number of pins in an external large-capacity memory.

As a result, it is possible to realize an inexpensive acoustic processing system having a small number of LSI pins and a small number of parts.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a first embodiment.

FIG. 2 is a configuration diagram of a microcomputer 106.

FIG. 3 is a configuration diagram of a memory controller 105.

FIG. 4 is an operation timing chart of the first embodiment.

FIG. 5 is an overall block diagram of a second embodiment.

FIG. 6 is a configuration diagram of a memory controller 501.

FIG. 7 is an operation timing chart (No. 1) of the second embodiment.

FIG. 8 is an operation timing chart (No. 2) of the second embodiment.

FIG. 9 is a block diagram of a conventional technique.

[Explanation of symbols]

101 keyboard 102 switch 103 ROM 104 RAM 105, 501 memory controller 106 microcomputer 107 sound source block 108 D / A converter 109 amplifier 110 speaker 201 bus controller 202 operation block 203 RAM 204 register (OPR) 205 instruction decoder (INSDE)
C) 206 timers 207, 601, 602 AND gate 208 state counter (STCNT) 209 port 301 address selector (ADS) 302 inverter 303 flip-flop (FF) 304 AND gate 305 waveform data register (WVR) 502 DSP 503 A / D conversion 603 Gate MAD address MDB data WAIT wait signal WAD waveform address WDT waveform data REQ request signal R / W read / write signal

Claims (4)

[Claims] 1. A sound processing circuit for processing sound data, a microcomputer circuit for controlling the sound processing circuit, memory access to a storage device connected from the microcomputer circuit to an external bus, and the sound processing. An acoustic processing integrated circuit, comprising: a memory access control circuit, which is connected to the external bus from a circuit and controls memory access to the same or different storage device as the storage device. 2. The memory access control circuit can access the storage device connected to the external bus by the microcomputer circuit when the sound processing circuit is not accessing the storage device connected to the external bus. State, and when the sound processing circuit accesses the storage device connected to the external bus, the microcomputer circuit is stopped for a predetermined memory cycle and the sound processing circuit is connected to the external bus. The acoustic processing integrated circuit according to claim 1, wherein a connected storage device is set to be accessible. 3. The acoustic processing circuit generates acoustic waveform data by reading waveform data from a storage device which is connected to the external bus and which stores data accessed by the microcomputer circuit in a mixed manner. The acoustic processing integrated circuit according to claim 1. 4. The acoustic processing circuit reads and writes waveform data to and from a storage device that is connected to the external bus and stores data accessed by the microcomputer circuit in a mixed manner. The acoustic processing integrated circuit according to claim 1, wherein the acoustic processing is performed on the acoustic processing integrated circuit.