JPH08181554A - Digital radio communication equipment provided with automatic gain control circuit - Google Patents

Abstract

PURPOSE: To make a circuit configuration small and to reduce the cost by decreasing the resolution required for A/D conversion while sufficiently securing the resolution of a reception signal used for demodulation. CONSTITUTION: An arithmetic circuit 24 is provided between a demodulation circuit 11 conducting demodulation processing and an A/D converter 20 sampling a 2nd reception intermediate frequency signal whose gain is controlled variably by an AGC circuit. The arithmetic circuit 24 multiplies a gain equivalent to a reciprocal of an overall gain G generated from the AGC circuit to control variably a level of the 2nd reception intermediate frequency signal with an output signal of the A/D converter 20 and an A/D conversion output signal multiplied by 1/G obtained from the A/D converter 20 is fed to the demodulation circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital radio communication apparatus used in a mobile radio communication system such as a mobile / automobile telephone system or a cordless telephone system adopting a digital communication system, and particularly to the amplitude of a received modulated wave signal. The present invention relates to a wireless communication device including an automatic gain control circuit that keeps a level constant.

[0002]

2. Description of the Related Art In recent years, as one of mobile radio communication systems, a system adopting a digital communication system which is excellent in confidentiality and enables effective use of radio frequencies has been developed. In this type of system, a digital modulation method such as QPSK or π / 4 shift DQPSK is used as a modulation method. Since these digital modulation systems are systems in which information is transmitted by adding phase and amplitude, if the received modulated wave signal is saturated in the wireless reception circuit system, accurate demodulation cannot be performed. Therefore, in a wireless communication device used in this type of system, an automatic gain control circuit (AGC: Automatic Gain Controller) is generally used in a wireless receiving circuit.
ol circuit) is provided to prevent saturation of the received modulated wave signal.

FIG. 6 shows an example of the configuration of a conventional radio receiving circuit having an AGC circuit. In the figure,
The radio modulated wave signal RFS received by the antenna 1 is first mixed by the first mixer 2 with the first local oscillation signal LO1 generated from the first local oscillator 3 and converted into the first reception intermediate frequency signal IFS1. The amplitude level is variably controlled by the variable gain amplifier 4 as the first intermediate frequency amplifier. Then, the first reception intermediate frequency signal IFS1 ', whose amplitude level is variably controlled, is subsequently supplied to the second mixer 5
The second local oscillation signal L generated from the second local oscillator 6 at
The second reception intermediate frequency signal IFS2 mixed with O2
Then, the amplitude level is variably controlled by the variable gain amplifier 7 as the second intermediate frequency amplifier. The second reception intermediate frequency signal IFS output from the variable gain amplifier 7.
2'is further mixed by the third mixer 8 with the third local oscillation signal LO3 generated from the third local oscillator 9, and converted into a reception baseband signal BS. The received baseband signal BS is analog / digital (A /
D) In the converter 10, the signal is sampled at a predetermined sampling frequency and quantized with a predetermined resolution, whereby the digital reception baseband signal DBS is obtained.
Is used for demodulation signal processing by the demodulation circuit 11.

The digital reception baseband signal DBS output from the A / D converter 10 is also input to a power value calculation circuit (PWR) 12, where the power value is detected. Then, the detected power value is calculated by the averaging circuit (AVE) 1
After being averaged in 3, the determination circuit 14 compares the average value with the reference value, and the comparison result is input to the gain value calculation circuit 15.
The gain value calculation circuit 15 calculates a variable gain value for bringing the detected power value closer to the reference value according to the comparison result. The decoder 16 determines gain values G1 and G2 to be assigned to each of the first and second variable gain amplifiers 4 and 7 based on the calculated variable gain value. Then, the gain control signals GS1, which represent these gain values G1, G2,
The GS2 is supplied to the first and second variable gain amplifiers 4 and 7, respectively, whereby the gain is set in the first and second variable gain amplifiers 4 and 7.

Therefore, even if the amplitude level of the received radio modulated wave signal changes due to the influence of multipath, for example, the change of the amplitude level is suppressed by the gain control by the first and second variable gain amplifiers 4 and 7. Is
As a result, the A / D converter 10 controls the reception baseband signal B whose amplitude level is always controlled to be within a certain range.
S is input.

Generally, in a radio communication device used in a digital mobile communication system, the input dynamic range of a radio modulated wave signal is -120 dBm to -20 dBm.
Up to about 100 dB is required. Further, due to fading, level fluctuations of about -30 dB to +10 dB always occur at a pitch of about several tens Hz. The AGC circuit described above is indispensable for A / D converting the wireless modulated wave signal in the A / D converter 10 while maintaining the resolution.

By the way, the following points must be taken into consideration when configuring the AGC circuit. That is, when the delay equalizer is used to equalize the multipath distortion, the amplitude information of the received modulated wave signal is also necessary for demodulation, and therefore the influence of the response of the AGC circuit on the amplitude information should be minimized. I have to. Usually, the response time of this AGC circuit is set to be 100 times or more the length of one symbol of received data.

However, if the response time of the AGC circuit is set long as described above, it becomes impossible to sufficiently follow the level fluctuation due to fading. Therefore, the resolution of the A / D converter 10 must be additionally ensured in consideration of the level variation due to this fading. For example, if the level fluctuation due to fading is set to -20 dB to +10 dB, the resolution required for the A / D converter 10 is 13 bits or more.

The resolution of the numerically controlled variable gain amplifiers used as the first and second variable gain amplifiers 4 and 7 is set high enough to minimize the non-linear effect on the delay equalizer. It is necessary to set it, and it is usually set to 0.5 dB or less per step.

[0010]

As described above, in the conventional device, the A / D converter 10 is required to have high resolution. However, A with high resolution and higher sampling frequency
The / D converter is large and expensive, and it is difficult at present to integrate it with a digital signal processing circuit such as a DSP into one chip. For example, if the second received intermediate frequency signal IFS2 'is A
When attempting to perform D / D conversion, the second received intermediate frequency signal I
The frequency of FS2 'is usually 455 kHz, and in order to sample a signal of this frequency with an A / D converter, a sampling frequency of at least 1 MHz or higher is required in consideration of the bandwidth of the received modulated wave signal. However, it is difficult to form an A / D converter having a resolution of 13 bits or more and operating at a sampling frequency of 1 MHz into one chip together with the DSP as described above, and if it is manufactured as a separate chip, the circuit is formed. Becomes expensive. For this reason, at present, as shown in FIG. 6, a third mixer 8 is provided in front of the A / D converter 10, and the second reception intermediate frequency signal IFS2 'is down-converted by the mixer 8 to the baseband signal BS. After that, it had to be supplied to the A / D converter 10. However, such a structure naturally requires the third mixer 8 and the third local oscillator 9, and thus the circuit becomes complicated and large.

Also for the numerical control type variable gain amplifier, 200 steps are required to secure a dynamic range of 100 dB per step of 0.5 dB, which is also difficult and expensive to manufacture.

The present invention has been made in view of the above circumstances, and an object thereof is to sufficiently secure the resolution of a received signal used for demodulation and to lower the resolution required for A / D conversion. Therefore, it is possible to provide a digital radio communication device equipped with an automatic gain control circuit whose circuit configuration is downsized and whose cost is reduced.

Another object of the present invention is to make the gain step width of the variable gain type level varying means for varying the amplitude level of the received modulated wave signal large so that the circuit configuration of the variable gain type level varying means. Another object of the present invention is to provide a digital wireless communication device equipped with an automatic gain control circuit which is designed to be simple and compact.

[0014]

In order to achieve each of the above objects, the present invention provides a digital radio communication apparatus equipped with an automatic gain control circuit for variably controlling the amplitude level of a modulated wave signal received by a radio receiving circuit. A variable gain type level varying means for varying and outputting the amplitude level of the received modulated wave signal is provided in the intermediate frequency stage of the radio receiving circuit, and the received modulated wave whose amplitude level is varied by the level varying means. Analog to convert signals to digital signals
Gain control for detecting the power value of the digital converting means and the output signal of the analog / digital converting means, and variably controlling the gain of the level varying means based on the result of comparison between the detected power value and a preset reference value. And an arithmetic means at the output stage of the analog / digital conversion means. Then, in this arithmetic means, the amplitude level of the output signal of the analog / digital converting means is variably controlled by a gain corresponding to the reciprocal of the gain of the level varying means variably controlled by the gain controlling means. The signal thus obtained is subjected to signal processing for demodulation.

Further, according to the present invention, the arithmetic circuit comprises a barrel shifter which outputs a signal variably controlled with a gain corresponding to the reciprocal of the gain of the level varying means by bit-shifting the output signal of the analog / digital converting means. It is also characterized by doing.

[0016]

As a result, according to the present invention, the received modulated wave signal output from the analog / digital converting means is demodulated after its amplitude level is variably controlled with a gain corresponding to the reciprocal of the gain set in the level varying means. It will be used for signal processing. That is, the demodulation circuit is supplied with the received modulated wave signal equivalent to the case where the resolution of the A / D conversion is increased without performing the gain control by the AGC circuit. Therefore, it is possible to set the resolution of the A / D conversion means to a low level, which allows the A / D conversion means to be integrated into one chip together with a digital signal processing circuit for performing demodulation signal processing and the like. It is possible to reduce the size and cost of the structure.

Further, the A / D conversion means enables high speed sampling as much as the resolution can be lowered. Therefore, in the A / D conversion means, the received intermediate frequency signal can be sampled as the intermediate frequency signal without being down-converted to the base band signal, whereby the frequency conversion circuit to the base band signal becomes unnecessary and the circuit becomes unnecessary. The configuration can be simplified and downsized.

Further, since the amplitude level of the received modulated wave signal is variably controlled by a gain corresponding to the reciprocal of the gain set in the first level varying means, it is subjected to demodulation signal processing, so that the gain variable in the AGC circuit is variable. Even if the step width is large, the change in the received modulated wave signal used for demodulation signal processing can be regarded as almost continuous. Therefore, when the delay equalizer is used, the non-linear effect on the delay equalizer is affected only by the accuracy of the step width of the gain change, which causes the gain in the level varying means of the AGC circuit. The number of variable steps can be reduced and the level variable means can be easily manufactured.
Further, by configuring the arithmetic means by the barrel shifter, the arithmetic means can be realized very easily.

[0019]

1 is a block diagram showing the structure of a radio receiving circuit section of a digital radio communication apparatus having an AGC circuit according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 6 are designated by the same reference numerals and detailed description thereof will be omitted.

The second received intermediate frequency signal IFS 'output from the second variable gain amplifier 7 is input to the A / D converter 20. The A / D converter 20 samples the second reception intermediate frequency signal IFS 'at a sampling frequency that is predetermined according to the frequency of the second reception intermediate frequency signal IFS'. The digital reception signal DIFS output from the A / D converter 20 is the power value calculation circuit (PWR) 2
Input to 1. The power value calculation circuit 21 calculates the power value of the digital received signal DIFS, and the calculated power value is input to the gain value calculation circuit 22. The gain value calculation circuit 22 compares the calculated power value with a reference value and calculates a total gain value G for bringing the calculated power value closer to the reference value based on the comparison result. The decoder 23 determines gain values G1 and G2 to be distributed to the first and second variable gain amplifiers 4 and 7 based on the total gain value G, and these gain values G1 and G1.
Gain control signals GS1 and GS2 representing G2 are supplied to the variable gain amplifiers 4 and 7, respectively.

Further, in the wireless communication device of this embodiment, the arithmetic circuit 24 is provided between the A / D converter 20 and the demodulation circuit 11.
Is inserted. This arithmetic circuit 24 is used for the A / D converter 2
The digital reception signal DIFS output from 0 is multiplied by the reciprocal (1 / G) of the total gain value G obtained by the gain value calculation circuit 22, and the amplitude-controlled digital reception signal DIFS 'is obtained. It is supplied to the demodulation circuit 11 for demodulation processing.

FIG. 2 is a circuit block diagram specifically showing the configuration of the main part of the radio receiving circuit section described above. This radio receiving circuit section is for the case where the QPSK method is used as the modulation method.

The quadrature demodulator 3 is provided downstream of the A / D converter 20.
0 is set. The quadrature demodulator 30 includes two multipliers 31 and 32, a local oscillator 33, and a π / 2 phase shifter 34.
Composed of and. The local oscillator 33 is composed of a ROM that stores sine wave data, and includes a digital signal processing circuit 11
The sine wave data is read according to the address information supplied from 0, and this sine wave data is output as a local oscillation signal. This local oscillation signal is branched into two, one of which is supplied to the multiplier 31 as it is, and the other of which is subjected to π / 2 phase shift by the π / 2 phase shifter 34 and supplied to the multiplier 32. The multipliers 31 and 32 respectively receive the digital reception signal DIF of the second intermediate frequency output from the A / D converter 20.
S is mixed with the local oscillation signal, and is thereby converted into an in-phase (I) component and a quadrature (Q) component baseband signal.

The power value calculation circuit 21 includes two multipliers 21.
1, 212 and an adder 213. Then, these multipliers 211 and 212 and adder 213
Thus, the square value of the power value of the received baseband signal output from the quadrature demodulator 30 is calculated.

The gain value calculation circuit 22 includes a comparator 221 and
It is composed of an up / down counter 222. The comparator 221 has two thresholds TH1 and TH2 for determining the power value calculated by the power value calculation circuit 21. FIG. 3 is for explaining these threshold values TH1 and TH2. That is, if the resolution of the A / D converter 20 is, for example, 8 bits, the output signal of the A / D converter 20 takes any value within the range of -128 to +127 when expressed in 2's complement. In order to keep the power value of the received baseband signal within the range of 32 ² to 64 ² , the total gain value G is decreased by one step (= 6 dB) when the power value is increased to 64 ² = 4096 or more. On the other hand, when the power value decreases to 32 ² = 1024 or less, it is sufficient to increase it by one step. Therefore, each of the thresholds TH1 and TH2 of the comparator 221 has a received power value of 4
The count-down pulse is output when it increases to 096 or more, and the count-up pulse is output when the received power value decreases to 1024 or less.

The up / down counter 222 is composed of, for example, a 5-bit counter, and increments the count value by -1, + 1 in accordance with the output of the countdown pulse and the countup pulse from the comparator 221. Then, this count value is output to the decoder 23 and barrel shifters 241, 242 as information indicating the total gain value G.

The decoder 23 comprises, for example, a ROM forming a memory table, and the up / down counter 2
When the count value of 22 is supplied as an address, the gain value G1 to be given to the first and second variable gain amplifiers 4 and 7 stored in advance in association with this address.
Read the decoded value representing G2. FIG. 4 shows the count value of the up / down counter 222 and the gain control value GS to be given to the first and second variable gain amplifiers 4 and 7.
1, GS2 and the corresponding relationship with the decoded value are shown together with the total gain value G and the gain values G1 and G2 of the first variable gain amplifier 4.

When the count value of the up / down counter 222 is input to the barrel shifters 241, 242,
The value of the received baseband signal output from the quadrature demodulator 30 is shifted in the direction of decreasing the count value, whereby the amplitude value of the received baseband signal is the reciprocal of the total gain value G (1 / G). ) Perform the multiplication operation.

The demodulation circuit 11 is composed of a digital signal processing circuit 110 and includes the barrel shifters 241 and 24.
The receiving baseband signal output from the receiver 2 is received, and digital signal processing for demodulating the receiving baseband signal is executed.

Next, the operation of the circuit configured as described above will be described. Radio modulated signal R received by antenna 1
FS is the first mixer 2 for receiving the first reception intermediate frequency signal IFS1.
The first variable gain amplifier 4 is down-converted to
Is level-controlled by the second mixer 5, and is down-converted to the second reception intermediate frequency signal IFS2 by the second mixer 5, and then level-controlled by the second variable gain amplifier 7. And
This level-controlled second reception intermediate frequency signal IFS2 '
Are sampled in the A / D converter 20.

When the sampled second reception intermediate frequency signal DIFS is output from the A / D converter 20, the second reception intermediate frequency signal DIFS is orthogonally demodulated into a baseband signal by the quadrature demodulator 30 and then power is supplied. The value is input to the value calculation circuit 21, and the power value calculation circuit 21 calculates the power value of the received baseband signal. Then, in the gain value calculation circuit 22, the power calculation value is set to the threshold values TH1 and TH.
2, the total gain value G for keeping the received power value within the predetermined range is obtained based on the comparison result, and the first and second gain control signals GS1 and GS1 corresponding to the total gain value G are obtained.
The GS2 is output from the decoder 23 and supplied to the first and second variable gain amplifiers 4 and 7.

Therefore, even if the received power value of the radio modulated wave signal RFS changes due to fading, for example,
This change in the received power value is suppressed within the predetermined range in the first and second variable gain amplifiers 4 and 7.
Therefore, the A / D converter 20 can be supplied with the second reception intermediate frequency signal IFS2 'having an amplitude level that does not exceed the dynamic range and can secure the necessary resolution.

It is to be noted that the AGC circuit composed of the power value calculation circuit 21, the gain value calculation circuit 22, the decoder 23 and the first and second variable gain amplifiers 4 and 7 performs one AG.
If the received power value of the received intermediate frequency signal does not fall within the predetermined range in the C control, the AGC control operation by the AGC circuit is repeatedly executed until the received power value falls within the predetermined range.

Thus, the second reception intermediate frequency signal IFS2 'variably controlled to have an appropriate input level is A /
After being sampled by the D converter 20, it is input to the arithmetic circuit 24, where it is multiplied by the reciprocal (1 / G) of the total gain G given to the variable gain amplifiers 4 and 7 by the AGC control. For example, if the input level of the A / D converter 20 is proper when the total gain G given to the first and second variable gain amplifiers 4 and 7 is 0 dB, the reception level of the radio modulated wave signal RFS is 24 dB. If it drops,
To compensate for this, the total gain G of the first and second variable gain amplifiers 4, 7 is set to 24 dB (G = 16). At this time, the output signal of the A / D converter 20 is changed to 1/16 in the arithmetic circuit 24. Therefore, the decrease in the reception level of the radio modulated wave signal RFS is reflected in the reception baseband signal input to the demodulation circuit 11. However, the resolution of the sampling value in the A / D converter 20 is secured as much as when the total gain value G = 0 dB. That is, the received baseband signal directly reflecting the amplitude variation of the radio modulated wave signal RFS is input to the demodulation circuit 11 without lowering the resolution.

Therefore, even when the amplitude information of the received modulated wave signal is also required for demodulation as in the case of using the delay equalizer, the sample value which is hardly influenced by the response of the AGC circuit to the amplitude information should be used for demodulation. Is possible.

In the circuit of FIG. 6 shown as a conventional example,
Received level fluctuation due to fading is -30 dB ~
It was necessary to provide the A / D converter 10 with the resolution required to cover +10 dB. For example, the A / D converter 10
The range is 6 dB each time the resolution increases by 1 bit.
Assuming that 6 dB resolution is required for a normal signal, -30 dB is 5 bits and +10 dB is 2 bits.
Since it requires bits, a total resolution of 13 bits was required.

On the other hand, in the circuit of this embodiment, the arithmetic circuit 24 is provided at the output stage of the A / D converter 20 so that the amplitude level of the output signal of the A / D converter 20 is multiplied by 1 / G. Therefore, the received signal level fluctuation due to fading is -30
A / D with the resolution required to cover dB to +10 dB
It is not necessary to have the converter 20. Therefore A / D
It suffices that the converter 20 has a total resolution of 7 to 8 bits, which is obtained by adding a 1-bit or 2-bit margin necessary for determining the magnitude of the amplitude to the 6-bit resolution normally required.

Therefore, such low resolution A / D
The converter 20 makes it possible to use a high sampling frequency, which results in the second received intermediate frequency signal I
FS2 'can be sampled as it is. Therefore, the third mixer 8 and the third local oscillator 9 for down-converting the second reception intermediate frequency signal IFS2 'to a baseband signal are unnecessary, and the circuit configuration can be simplified and miniaturized accordingly. In addition, the A / D converter 2
Since 0 can have a low resolution, the A / D converter 20 can be configured with a digital signal processing circuit and a single chip, which also makes it possible to reduce the circuit size and cost.

Further, in this embodiment, the 1 / G times arithmetic circuit 24
By providing the above, even if the gain variable step width in the AGC circuit is large, it is possible to consider that the level change of the reception baseband signal used for demodulation signal processing is almost continuous. That is, the gain step widths of the variable gain amplifiers 4 and 7 can be set to be large, so that the variable gain amplifiers 4 and 7 can be easily manufactured.

Further, in the present embodiment, the arithmetic circuit 24 for multiplying the output signal of the A / D converter 20 by the reciprocal multiple of the total gain value G is composed of barrel shifters 241 and 242. When the gain step width of the variable gain amplifiers 4 and 7 is 6 dB, the reciprocal of the total gain value G is 1/2 ⁿ (n
It is realized by the bit shift of the register, focusing on the fact that = 0, 1, 2, ... With this configuration, the configuration of the arithmetic circuit 24 for multiplying the A / D converted output by the reciprocal of the total gain value G can be made extremely simple.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the second reception intermediate frequency signal IFS2 'is supplied to the A / D converter 20 as it is for sampling, but the second reception intermediate frequency signal IFS2' is supplied to the third mixer as shown in FIG. It may be configured such that a frequency conversion circuit composed of 8 and the third local oscillator 9 down-converts into a baseband signal and then supplies the baseband signal to the A / D converter 40. With this configuration, it is possible to use the A / D converter 40 that has a low resolution and operates at a low sampling frequency, which makes it possible to configure the A / D converter more easily and at a lower cost. Become.

In the above embodiment, the A / D conversion output is multiplied by 1 / G in the arithmetic circuit 24 and then supplied to the demodulation circuit 11. However, the demodulation circuit 11 is composed of a digital signal processing circuit (DSP). If you have this DSP
May be configured to be performed in.

Further, the 1 / G times arithmetic circuit 24 determines the output signal level of the A / D converter and the total gain value G and the A / D value.
A memory such as a ROM in which table data representing the correspondence with the converted output level multiplied by 1 / G is stored in advance is used, and the output signal level of the A / D converter and the total gain value G are used as addresses in this memory. Enter and corresponding 1 / G
You may comprise so that the doubled A / D conversion output signal level may be read.

In addition, applications and configurations of wireless communication devices, AG
The configuration of the C circuit, the configuration for variably controlling the amplitude level of the output signal of the A / B conversion means by the gain corresponding to the reciprocal of the gain of the level varying means variably controlled by the gain controlling means, and the like of the present invention. Various modifications can be made without departing from the scope of the invention.

[0045]

As described above in detail, in the digital radio communication apparatus of the present invention, variable gain type level varying means for varying and outputting the amplitude level of the received modulated wave signal is provided in the intermediate frequency stage of the radio receiving circuit. An analog / digital converting means for converting the received modulated wave signal whose amplitude level is changed by the level changing means into a digital signal, and the power value of the output signal of the analog / digital converting means are detected to detect the power. Gain control means for variably controlling the gain of the level varying means based on the result of comparison between the value and a preset reference value is provided, and further arithmetic means is provided at the output stage of the analog / digital converting means. Then, in this arithmetic means, the amplitude level of the output signal of the analog / digital converting means is variably controlled by a gain corresponding to the reciprocal of the gain of the level varying means variably controlled by the gain controlling means. The signal thus obtained is subjected to signal processing for demodulation.

Therefore, according to the present invention, the resolution required for the A / D conversion can be lowered while sufficiently securing the resolution of the received signal used for demodulation, whereby the A / D conversion can be performed.
It is possible to provide a digital wireless communication device equipped with an automatic gain control circuit capable of simplifying the circuit configurations of the D converter and the variable gain level varying means and reducing the cost.

Further, according to the present invention, the gain step width of the variable gain type level varying means for varying the amplitude level of the received modulated wave signal can be increased, whereby the circuit configuration of the variable gain type level varying means. It is possible to provide a digital wireless communication device equipped with an automatic gain control circuit that can achieve a simple size reduction and a cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a wireless reception circuit unit of a digital wireless communication apparatus including an automatic gain control circuit according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram specifically showing a configuration of a main part of a wireless reception circuit unit shown in FIG.

FIG. 3 is a diagram for explaining thresholds TH1 and TH2 used in a comparator of a gain value calculation circuit.

FIG. 4 is a diagram showing an example of table data stored in a decoder.

FIG. 5 is a block diagram showing a configuration of a wireless reception circuit unit of a digital wireless communication apparatus including an automatic gain control circuit according to another embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a configuration of a wireless reception circuit unit of a digital wireless communication device including a conventional automatic gain control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Antenna 2 ... 1st mixer 3 ... 1st local oscillator 4 ... 1st variable gain amplifier 5 ... 2nd mixer 6 ... 2nd local oscillator 7 ... 2nd variable gain amplifier 8 ... 3rd mixer 9 ... 3rd Local oscillator 10, 20 ... A / D converter 11 ... Demodulation circuit 12, 21 ... Power value calculation circuit (PWR) 13 ... Average circuit (AVE) 14 ... Judgment circuit 15, 22 ... Gain value calculation circuit 16, 23 ... Decoder 24 ... 1 / G times arithmetic circuit 30 ... Quadrature demodulator 31, 32 ... Multiplier 33 ... Local oscillator 34 ... .pi. / 2 phase shifter 110 ... Digital signal processing circuit 211, 212 ... Multiplier 213 ... Adder 221 ... Comparison Container 222 ... Up-down counter 241,242 ... Barrel shifter

Claims (2)

[Claims] 1. A digital wireless communication device comprising an automatic gain control circuit for variably controlling the amplitude level of a modulated wave signal received by a wireless receiving circuit, wherein the digital modulating device is inserted in an intermediate frequency stage of the wireless receiving circuit to perform reception modulation. Variable gain type level varying means for varying and outputting the amplitude level of the wave signal, and analog / digital converting means for sampling and outputting the received modulated wave signal whose amplitude level is varied by the level varying means. And a gain control means for variably controlling the gain of the level varying means based on a result of comparison between the detected power value of the analog / digital converting means and the detected power value and a preset reference value. Is provided on the output side of the analog / digital conversion means, and the amplitude level of the output signal of the analog / digital conversion means is set to the gain An automatic gain control circuit, comprising: an arithmetic means for variably controlling with a gain corresponding to the reciprocal of the gain of the level varying means variably controlled by the controlling means and providing the signal processing for demodulation. Equipped digital wireless communication device. 2. The arithmetic circuit is composed of a barrel shifter that outputs a signal variably controlled with a gain corresponding to the reciprocal of the gain of the level varying means by bit-shifting the output signal of the analog / digital converting means. A digital wireless communication apparatus comprising the automatic gain control circuit according to claim 1.