JPH1075273A - Reception signal amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly restore a transmission signal from a transmitting device in a device for amplifying a reception signal to a desired level through the use of logarithm amplifiers and reverse logarithm converters. SOLUTION: In a receiving part for receiving modulation wave by a π/4-DQPSK system, the reception signal is amplified by a low noise amplifier LNA and the I component and the Q component of the reception signal are respectively demodulated by an orthogonal demodulator 20. Then, an output from the orthogonal demodulator 20 is amplified by logarithm amplifiers 30i and 30q, a D.C. component is removed by using capacitors Ci and Cq and, after that, reverse logarithm conversion is executed by the reverse logarithm converters 501 and 50q. Since the signal after logarithm amplification is made to correspond to the absolute value of the reception signal and a polarity (phase) is lost, the output from the orthogonal demodulator 20 is amplified respectively by amplitude limiting amplifiers 40i and 40q so that a polarity judging signal expressing the polarity of the output is generated and the polarities of the outputs from the reverse logarithm converters 50i and 50q are established. Therefore, data is correctly restored from the output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received signal amplifying apparatus for amplifying a received signal using a logarithmic amplifier, and more particularly to a received signal amplifying apparatus suitable for amplifying a phase-modulated received signal.

[0002]

2. Description of the Related Art Conventionally, Japanese Patent Application Laid-Open No.
As disclosed in Japanese Patent Application Laid-Open No. 04-2004, as a receiving device for performing envelope detection of an amplitude-modulated received signal, a logarithmic amplifier (a so-called log amplifier) that logarithmically amplifies the received signal, and a DC component from the signal after logarithmic amplification DC component removing means for removing,
There has been known an amplifier configured to amplify a received signal using an amplifying device including an antilogarithmic converter for performing an antilogarithmic conversion of a signal from which a DC component has been removed by the DC component removing means.

[0003] This device uses an automatic gain control circuit (a so-called "A") to amplify a received signal to a desired level (in other words, to increase the dynamic range of the receiving device).
The use of an amplifying device provided with a GC circuit) causes a problem in that the received signal may be distorted due to the operation speed (delay) of the AGC circuit, and the received signal may not be accurately demodulated. By amplifying the received signal using a logarithmic amplifier, cutting the DC component included in the amplified signal, and performing inverse logarithmic conversion on the signal,
The received signal can be amplified to a desired level without distortion.

[0004]

However, when the input signal Sin is amplified using the logarithmic amplifier as described above, the output signal Sout from the logarithmic amplifier is expressed by the following equation (1): Sout = K · log | Sin | … (1) where K is represented by a constant and corresponds to the absolute value of the input signal Sin.
From the output signal Sout, the polarity of the input signal Sin cannot be identified. Therefore, the signal transmitted by the transmitting device cannot be accurately restored only by simply performing the inverse logarithmic conversion on the signal after logarithmic amplification as in the related art, and the conventional amplifying device using the logarithmic amplifier is phase-modulated. This cannot be used to amplify the received signal.

That is, in a conventional amplifying device using a logarithmic amplifier, the amplitude of a signal transmitted by a transmitting device can be restored, so that an amplitude-modulated received signal is enveloped as in the receiving device disclosed in the above publication. It can be used as long as it is a receiving device that performs detection, but since the polarity of the received signal is lost by passing through the logarithmic amplifier, the phase of the received signal cannot be identified from the amplified signal, and the reception that demodulates and receives the phase modulated signal It cannot be used for equipment.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a receiving signal amplifying apparatus that amplifies a received signal to a desired level by using a logarithmic amplifier and an antilogarithmic converter accurately converts a transmitted signal transmitted by the transmitting apparatus. The purpose is to be able to restore.

[0007]

According to a first aspect of the present invention, there is provided a reception signal amplifying apparatus comprising:
The logarithmic amplifier amplifies the received signal, and the DC component removing means
The DC component is removed from the amplified signal. Then, the signal after removing the DC component is input to an antilog converter,
It is antilog transformed.

Therefore, even if the level of the received signal input to the receiving apparatus fluctuates due to the characteristics of the signal transmission system from the transmitting apparatus to the receiving apparatus such as attenuation of radio waves, the fluctuation component does not affect the received signal. , The received signal can be amplified to a desired level. In other words, the level of the received signal at the receiving device fluctuates due to the characteristics of the signal transmission system, and the received signal
-When Sin, output signal Sout from logarithmic amplifier
Is given by Sout = K.log | X.Sin | = K.log | Sin | + K.log | X | (2) From the output signal Sout, a DC component (K. log | X |) is removed, so that the antilogarithmic converter provides the signal S transmitted from the transmitting device.
The signal (K · log | Sin |) obtained by logarithmically converting in is input, and the received signal Sin amplified to a desired level can be restored by antilogarithmic conversion by the antilogarithmic converter.

As described above, when the received signal is logarithmically amplified, the polarity of the received signal is removed from the signal after logarithmic amplification. It cannot be restored to the polarity of Sin. Therefore, in the present invention, a polarity determining means for determining whether the received signal is positive or negative with respect to the zero cross point is provided, and the polarity of the output from the antilogarithmic converter is determined according to the determination result. I am trying to do it.

As a result, according to the present invention, despite the fact that the received signal is amplified to the desired level using the logarithmic amplifier, the polarity (phase) is not lost from the amplified received signal. Even if the signal is a phase-modulated signal, the data before modulation can be accurately restored from the amplified received signal.

Here, the polarity judging means may be as follows.
As described above, an amplitude limiting amplifier (a so-called limiter amplifier) can be used. If the polarity of the received signal is determined using the amplitude limiting amplifier, the polarity of the received signal can be easily and accurately determined. That is, the amplitude limiting amplifier is generally used in a receiving device or the like that performs data communication using the FM modulation wave, and can be configured relatively easily, and furthermore, the output level from the amplitude limiting amplifier is equal to that of the input signal. High / Low depending on polarity
Therefore, the polarity of the received signal can be accurately identified.

The polarity determining means may be any as long as it can determine whether the received signal is positive or negative with respect to the zero-cross point. For example, the polarity determining means detects the level of the zero-cross point of the received signal. The detection circuit compares the level of the detected zero-cross point with the level of the received signal, and outputs a signal indicating positive polarity when the received signal is higher than the zero-cross point, and the received signal is lower than the zero-cross point. In such a case, it may be constituted by a comparison circuit that outputs a signal indicating negative polarity.

Next, as an antilogarithmic converter, for example, an A / D converter for converting a signal passed through the DC component removing means into digital data,
Storage means in which antilogarithmically converted data obtained by adding a polarity to an antilogarithmically converted value for each data obtained by adding the determination result by the polarity determination means to the digital data from the / D converter is stored in advance; What is necessary is just to comprise so that the output data from the A / D converter and the antilogarithm conversion data corresponding to the determination result by the polarity determination means may be output. With this configuration, the antilogarithmic conversion and the operation for imparting a polarity to the conversion result are not required, and the antilogarithmic converter can be easily configured.

Further, according to the reception signal amplifying device of the present invention (claims 1 to 3), the polarity (phase) of the reception signal is not lost even though the logarithmic amplifier is used.
Since the received signal can be amplified to a desired level as it is, even if the received signal is amplitude-modulated, or if the received signal is phase-modulated (including frequency-modulated), amplification can be performed. Although the signal before modulation can be accurately demodulated from the subsequent signal, the effect can be further enhanced if the signal is used in a receiving device that receives a phase-modulated signal as a received signal. Can be.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 2 is a block diagram illustrating a circuit configuration of a communication device according to an embodiment to which the present invention is applied.

The communication apparatus of the present embodiment is configured to perform π / 4 shift 4-phase differential PSK (hereinafter referred to as π / 4-DQP), which is a kind of phase modulation, with a base station (not shown) connected to a telephone network.
For example, a PDC (Personal Digital Cellular) telephone terminal that performs bidirectional data communication by transmitting and receiving radio waves modulated by the SK method. It has an audio output unit 14 and a display function for displaying the operation state of the device and the like,
An operation unit 16 for inputting telephone numbers and various instructions is provided.

Further, the communication apparatus of the present embodiment includes a transmitting antenna 4 and a receiving antenna 2 for transmitting and receiving a π / 4-DQPSK signal to and from a base station, and transmitting data to be transmitted (transmission data) to a transmission signal. (Π / 4-DQPSK signal) which is converted into a (π / 4-DQPSK signal) and output to the transmitting antenna 4, and a phase component (I component) orthogonal to each other from the received signal (π / 4-DQPSK signal) input from the receiving antenna 2 , Q component), a synthesizer 6 that generates a local oscillation signal of a predetermined frequency, which is a communication carrier, and outputs the signal to the transmission unit 8 and the reception unit 10, respectively, and an operation unit 16 and a voice input unit. The transmission data is generated according to the input data from the base station 18 and output to the transmission unit 8, or the transmission data from the base station is restored from the demodulated signal demodulated by the reception unit 10, and the voice included in the restored data is restored. The control unit 12 that performs various kinds of signal processing for outputting to the audio output unit 14 converts the over data to the audio signal is provided.

The control section 12 is composed of a digital signal processing circuit mainly composed of a microcomputer, and executes various signal processing for data communication in accordance with a control program stored in advance. Further, the transmission unit 8 converts transmission data input from the control unit 12 into π / 4-D
A modulator for performing QPSK modulation, a frequency converter for mixing a modulated signal output from the modulator with a local oscillation signal from the synthesizer 6 and frequency-converting the mixed signal into a transmission signal in a predetermined frequency band;
The transmission signal from the frequency conversion unit is amplified and the transmission antenna 4
, And an amplifier that outputs the data.

Next, the receiving unit 10 which is a main part of the present invention is described.
As shown in FIG. 1, a low-noise amplifier (a so-called low-noise amplifier) LNA that amplifies a reception signal received by the reception antenna 2 by, for example, about 50 dB, and a reception signal amplified by the low-noise amplifier LNA A quadrature demodulator 20 for demodulating into I and Q component signals using a local signal from the synthesizer 6, and a demodulated signal (received signal) of the I component and Q component output from the quadrature demodulator 20 as a logarithm. Logarithmic amplifiers (so-called log amplifiers) 30i and 30q to amplify, capacitors Ci and Cq as DC component removing means for removing DC components from the signals after logarithmic amplification output from the respective logarithmic amplifiers 30i and 30q, and quadrature. Amplitude limited amplifiers (so-called limiter amplifiers) 40i, 4 as polarity determining means for amplifying the demodulated signal (received signal) from the demodulator 20 respectively.
0q and logarithmic amplifier 30 via capacitors Ci and Cq.
i, 30q, respectively, and antilogarithmic converters 50i, 50q that perform antilogarithmic conversion of these signals in accordance with the outputs from the amplitude limiting amplifiers 40i, 40q, respectively.

Here, the quadrature demodulator 20 converts the received signal into an I component having the same phase as the local oscillation signal and a Q signal orthogonal to the local oscillation signal without converting the frequency of the received signal into an intermediate frequency (IF). And a component splitter (PS: power splitter) 2 for distributing the received signal input via the low-noise amplifier LNA to two systems.
2 and a mixer (MI) that mixes one of the received signals output from the duplexer 22 and the local signal from the synthesizer 6.
X) An analog low-pass filter (low-pass filter: LP) that passes a data signal component (I component) superimposed on the received signal from the output signal from the mixer 24i
F) 26i, a phase shifter 28 for shifting the phase of the local oscillation signal from the synthesizer 6 by π / 2 (that is, 90 °),
A mixer (MI) that mixes the local oscillation signal passing through the phase shifter 28 and the other reception signal output from the duplexer 22
X) An analog low-pass filter (low-pass filter: LP) that passes a data signal component (Q component) superimposed on the received signal from the output signal from the mixer 24q and the output signal from the mixer 24q
F) 26q.

Then, the quadrature demodulator 20 inputs the I and Q components of the received signal, which have passed through the low-pass filters 26i and 26q, to logarithmic amplifiers 30i and 30q and amplitude limiting amplifiers 40i and 40q, respectively. The amplitude limiting amplifiers 40i and 40q output a high-level or low-level binary signal (polarity determination signal) that limits the received signal at its zero-cross point.

Next, as shown in FIG. 3, the antilogarithmic converters 50i and 50q are each provided with a logarithmic amplifier 30 (30i or 30q) input via a capacitor C (Ci or Cq).
52 having a predetermined gain N for amplifying an output signal from
And an A / D converter 5 for converting a signal (analog signal) passed through the amplifier 52 into, for example, 8-bit digital data.
4 and 9-bit data obtained by adding the polarity determination signal output from the amplitude limiting amplifier 40 (40i or 40q) to the 8-bit data A / D-converted by the A / D converter 54 as the most significant bit data. For each specified address, antilogarithm conversion data (for example, 8 bits) corresponding to the 9-bit data
And a ROM 56 storing bit data). The A / D converter 54 and the amplitude limiting amplifier 40
The output from (40i or 40q) is input to the ROM 56, and the antilogarithm conversion data stored at the address represented by the input data is output from the ROM 56 as reception data representing the I component or the Q component of the reception signal.

That is, the signal input to the antilogarithmic converter 50 (50i or 50q) via the capacitor C (Ci or Cq) is obtained by removing the polarity of the received signal by logarithmic amplification. Even if the logarithm conversion is performed as it is, the polarity of the received signal cannot be specified, and the transmission data from the base station cannot be restored.

Therefore, in this embodiment, the input signal is set to A /
8-bit digital data (value:
0 to 255), and the polarity determination signal is set to Low level at each of the addresses (0 to 511) of the ROM 56 specified by the 9-bit data to which the polarity determination signal is added as the most significant bit data of the 8-bit data. When the polarity of the received signal is negative, each address (0 to 255) corresponding to the 8-bit data after A / D conversion corresponds to inverted data (255 to 0) obtained by inverting the 8-bit data. When the polarity determination signal is High level and the polarity of the received signal is positive, each address (256 to 511) corresponding to the 8-bit data after A / D conversion is stored. The antilogarithm conversion data corresponding to the address value is stored, and the antilogarithm conversion data is stored as shown in Table 1 below, and the capacitor C (C Or Cq) is of as sweeping inverse logarithmic transformation data corresponds to the signal after logarithmic amplification that has passed and the polarity of the received signal.

[0025]

[Table 1]

The antilogarithm conversion data (0 to 511) shown in Table 1 are actually set as follows. That is, if the input signal input to the antilogarithmic converter 50 (50i or 50q) via the capacitor C (Ci or Cq) is “y = log x”, the input signal to the A / D converter 54 is “ y ′ = N × log x ”, and the A / D converter 5
Assuming that the maximum input voltage of No. 4 is 5 V, the A / D conversion value is "yAD = N * log x / (5/255)".
Then, since the antilogarithmic conversion is to obtain “x = 10 ^y ”, each address of the ROM 56 has this A
From the / D conversion value yAD, the following equation (3) x = 10 ^{{yAD · (5/255)} / N} × c (3) c: An ^{antilogarithm} conversion value is obtained using a coefficient that determines a data range, The antilogarithm conversion data in which the value after the decimal point is rounded is stored in advance together with polarity data indicating the polarity of the received signal. In the above equation,
“5/255” represents the resolution of the A / D converter 54, and is about 20 mV in the present embodiment.

Then, as described above, the logarithmic amplifiers 30i,
30q, capacitors Ci and Cq, amplitude limiting amplifier 40
By the operation of i, 40q and the antilogarithmic converters 50i, 50q, the digital data corresponding to the I component and the Q component of the demodulated signal (received signal) subjected to logarithmic amplification → DC component removal → polarity determination → antilogarithmic conversion becomes Each is input to the control unit 12, and the control unit 12 transmits the transmission data (2
Bit data) is restored.

As described above, in the present embodiment, π /
In a receiving unit 10 that receives a signal modulated by the 4-DQPSK method, an I component and a Q component are respectively extracted (demodulated) from a received signal by a quadrature demodulator 20, and the demodulated signal is logarithmically amplified. The DC component is cut from the amplified signal, and the signal is subjected to antilogarithmic conversion, thereby amplifying each demodulated signal (received signal) to a desired level without using an AGC circuit with low response, and The dynamic range of 10 is expanded.

Also, since the signal after logarithmic amplification does not include the polarity of the received signal, even if the signal is subjected to antilogarithmic conversion as it is, the phase of the received signal can be calculated from the amplified demodulated signal (I component and Q component). Cannot be detected, and the transmission data transmitted from the base station cannot be restored. In the present embodiment, the demodulated signals of the I component and the Q component output from the quadrature demodulator 20 are Each of the amplitude limiting amplifiers 40
i, 40q, the amplitude limiting amplifier 40
i, 40q, to output a polarity determination signal indicating the polarity of each demodulated signal. When the antilogarithmic converters 50i, 50q perform antilogarithmic conversion on the demodulated signal after logarithmic amplification, the polarity determination signal is used. Thus, the polarity of the demodulated signal after antilogarithmic conversion is determined.

For this reason, according to the present embodiment, the control unit 12
In, the transmission data from the base station can be accurately restored from the demodulated signals of the I and Q components (digital data in this embodiment) output from the antilogarithmic converters 50i and 50q, respectively. That is, first, π / 4-DQPSK
When data communication is performed by the system, 2-bit data (X, Y) can be transmitted at the same time. The encoding rule at the time of data transmission is, for example, as shown in FIG. ), The phase shift amount of the transmission signal is set. For example, when data (0, 0) and data (1, 1) are transmitted alternately and repeatedly, FIG.
As shown in the signal space diagram of (b), the phase of the transmission signal is + π / 4, −3π /
4, + π / 4, -3π / 4,...

Next, when the communication apparatus of this embodiment receives the π / 4-DQPSK signal thus phase-modulated, the signals of the I component and the Q component output from the quadrature demodulator 20 are: For example, the signal waveform is as shown on the upper left side of FIG. Therefore, from this signal waveform, the phase shift of the received signal can be accurately detected as illustrated in the upper right part of FIG. Therefore, if the signal from the quadrature demodulator 20 can always be amplified to a desired level, the phase shift of the received signal can always be detected accurately, and the transmission data transmitted by the base station can be accurately restored.

However, as in this embodiment, the quadrature demodulator 2
When the logarithmic amplifiers 30i and 30q are used to amplify the signal from 0 to a desired level, the logarithmic amplifier takes the absolute value of the input signal, and the output signal from the logarithmic amplifiers 30i and 30q is, for example, as shown in FIG. The signal waveform becomes as shown on the middle left side, and the polarity of the received signal is lost. Therefore, even if the DC component is removed from this signal and the inverse logarithmic conversion is performed, the phase shift of the received signal cannot be accurately detected as illustrated in the middle right of FIG. Data cannot be restored.

Therefore, in the present embodiment, as shown in the lower left part of FIG. 5, the amplitude limiting amplifiers 40i and 40q are used.
A polarity determination signal indicating the polarity of the signal from the quadrature demodulator 20 with respect to the zero cross point is generated, and the antilogarithmic converter 50i,
When the signal after logarithmic amplification and DC component removal is subjected to inverse logarithmic conversion at 50q, the polarity determination signal is used to specify the polarity of the signal after antilogarithmic conversion.

Therefore, the output signals (digital data in this embodiment) from the antilogarithmic converters 50i and 50q correspond to signal waveforms obtained by amplifying the output from the quadrature demodulator 20 to a predetermined level. In the control unit 12, the transmission data transmitted by the base station can be accurately restored from the data.

As shown on the lower right side of FIG.
Of the output signal waveforms from the quadrature demodulator, logarithmic amplifier, and amplitude limiting amplifier shown in (1), the signal waveform shown by the solid line represents the I component of the received signal, and the signal waveform shown by the dotted line is the Q of the received signal.
Represents a component. As mentioned above, although one Example of this invention was described, this invention is not limited to the said Example,
Various embodiments can be adopted.

For example, in the above embodiment, π / 4-DQP
Although the case where the present invention is applied to a communication device that transmits and receives a signal modulated by the SK method has been described, the received signal amplifying device of the present invention is a receiving device that receives a phase modulated wave such as π / 4-DQPSK. However, the present invention can be applied to a receiving device that receives a frequency-modulated wave or a receiving device that receives an amplitude-modulated wave.

In the above embodiment, the antilog converter is
The A / D converter and the ROM are used so that the logarithmically amplified signal is inversely logarithmically converted into a digital value and the digital value is directly input to a control unit that performs digital signal processing. The section performs analog signal processing, and when an analog signal is required as a signal after amplification, the output from the antilog converter is converted to an analog signal again using a D / A converter. Is also good. In this case, the antilogarithmic converter may be configured by an analog circuit using an operational amplifier or the like.

In the above embodiment, the capacitor is used as the DC component removing means for cutting the DC component from the output signal from the logarithmic amplifier. However, as the DC component removing means, an analog high-pass filter ( High-pass filter)
Or a DSP (digital signal processor) capable of removing a DC component by digital signal processing may be used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a receiving unit according to an embodiment.

FIG. 2 is a block diagram illustrating an overall configuration of a communication device according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of an antilog converter according to the embodiment.

FIG. 4 is an explanatory diagram showing an example of a coding rule and a phase shift of a transmission signal during data communication according to the π / 4-DQPSK method.

FIG. 5 is an explanatory diagram illustrating an output signal waveform of each unit of a receiving unit.

[Explanation of symbols]

10 receiving unit 20 quadrature demodulator 30i, 30q
... Logarithmic amplifiers 40i, 40q ... Amplitude limiting amplifiers 50i, 50q ...
Antilog converter Ci, Cq ... capacitor

Claims (4)

[Claims] 1. A logarithmic amplifier for amplifying a received signal, DC component removing means for removing a DC component from a signal after logarithmic amplification by the logarithmic amplifier, and an inverse logarithmic conversion for a signal passing through the DC component removing means And a logarithmic converter, comprising: a polarity determining means for determining whether the received signal has a positive polarity or a negative polarity with respect to a zero crossing point, and the inverse is performed according to the determination result. A reception signal amplifying device characterized in that the polarity of an output from a logarithmic converter is determined. 2. The apparatus according to claim 1, wherein said polarity determining means comprises an amplitude limiting amplifier for amplifying said received signal, and determines a polarity of an output from said antilogarithmic converter in accordance with an output signal level from said amplitude limiting amplifier. The receiving signal amplifying device according to claim 1, wherein the receiving signal amplifying device is configured. 3. An anti-logarithmic converter comprising: an A / D converter for converting a signal passed through the DC component removing means into digital data; and a digital data from the A / D converter, wherein the polarity determining means converts the digital data from the A / D converter into digital data. Storage means in which antilogarithmically converted data obtained by adding a polarity to the antilogarithmically converted value is stored in advance for each data to which the determination result is added, and output data from the A / D converter is stored from the storage means. And outputting antilogarithm conversion data corresponding to a result of the determination by the polarity determining means.
Or the received signal amplifying device according to claim 2. 4. The received signal amplifying device according to claim 1, wherein said received signal is a phase modulation signal.