JP4629408B2 - Radio and its automatic gain control program - Google Patents

Description

  The present invention relates to a radio used as, for example, a business transceiver, and more particularly to a radio having an automatic gain control function and an automatic gain control program thereof.

For example, in a commercial transceiver used as a communication means between staff members in a broadcasting station, automatic gain control (AGC: Automatic Gain Control) is used in order to make the fluctuation of the reception level of a radio signal generated due to the distance between the staff members and fading. Control) circuit is provided (see, for example, Patent Document 1).
JP 2000-22467 A

  However, in this type of conventional radio, the response speed of the AGC circuit is generally fixed at a constant value. For this reason, if the response speed of the AGC circuit is set in accordance with the fluctuation of the reception level during voice communication, the AGC circuit cannot follow the operation in which the signal level changes rapidly like the start of voice communication. There is a case where the beginning of the transmitted voice is cut off. On the other hand, if the response speed of the AGC circuit is set to a high speed in accordance with the start of voice communication, it will follow up too sensitively to fluctuations in the reception level during voice communication, making it difficult to hear the received voice. The reception quality is degraded.

  The present invention has been made paying attention to the above circumstances, and the object of the present invention is to exhibit good response characteristics both at the start of wireless communication and during wireless communication, thereby maintaining a high reception quality at all times. An object of the present invention is to provide a radio device and an automatic gain control program thereof.

  To achieve the above object, a radio according to the present invention and an automatic gain control program thereof are outputted from the variable gain amplifier in a radio having an automatic gain control function for adjusting a signal level of a received signal by a variable gain amplifier. A detection circuit for detecting a signal level of the received signal, and a control circuit connected to the detection circuit and the variable gain amplifier. The control circuit operates at a first control mode that operates at a preset first response speed and at a second response speed that is lower than the first response speed, according to the operating state of the radio. The second control mode to be selected is alternatively selected. When the first control mode is selected by this selection, the signal level detected by the detection circuit is integrated by the first integration coefficient, and the control voltage of the variable gain amplifier is based on the integration value. Is supplied to the variable gain amplifier. On the other hand, when the second control mode is selected by the selection, the signal level detected by the detection circuit is set to a second integration coefficient smaller than the first integration coefficient over a preset delay time. Integrate with. Then, a control voltage of the variable gain amplifier is generated based on the integrated value, and the generated control voltage is integrated by a third integration coefficient and smoothed, and then supplied to the variable gain amplifier. It is.

  By configuring in this way, an appropriate control mode is selected according to both the operation state at the start of wireless communication and during wireless communication, so that a good response characteristic can be exhibited. As a result, it is possible to absorb changes in the reception level and always maintain high quality reception quality.

The present invention is also characterized by having the following configuration.
In a radio having an automatic gain control function for adjusting the signal level of a received signal by a variable gain amplifier, the signal level of the received signal output from the variable gain amplifier is detected. By integrating the detected signal level with the first integration coefficient over a preset time, an integrated value subjected to delay processing is output. A control voltage for the variable gain amplifier is generated based on the integrated value output after the delay process. Further, the generated control voltage is output after being smoothed by integrating with the second integration coefficient. The output control voltage is supplied to the variable gain amplifier.

  With such a configuration, the delay process and the smoothing process can be controlled independently, so that the optimum response characteristic can be set more flexibly.

  Therefore, according to the present invention, it is possible to provide a radio device and an automatic gain control program for the radio device that exhibit good response characteristics both at the start of radio communication and during radio communication, and thereby can always maintain high reception quality. can do.

FIG. 1 is a circuit block diagram showing a configuration of a radio device having an automatic gain control function according to an embodiment of the present invention.
The wireless device includes an antenna 1, an RF (Radio Frequency) unit 2, a baseband module 3, a control unit 5, and a user interface 4. A radio signal arriving via a radio line is received by the antenna 1 and then input to the RF unit 2. In the RF unit 2, the input radio signal is amplified by a first high-frequency amplifier 22 including a variable gain amplifier after unnecessary wave components are removed by a first high-frequency filter 21. The amplified radio signal is further amplified by the second high-frequency amplifier 24 via the second high-frequency filter 23 and then input to the first mixer 25.

  In the first mixer 25, the input radio signal is mixed with the first local oscillation signal, and thereby converted into a first intermediate frequency signal. The first intermediate frequency signal output from the first mixer 25 is input to the second mixer 27 after unnecessary wave components are removed by the intermediate frequency filter 26. Then, the second mixer 27 mixes with the second local oscillation signal and converts it to a second intermediate frequency signal having a frequency lower than that of the first intermediate frequency signal. The converted second intermediate frequency signal is amplified by an intermediate frequency amplifier 28 composed of a variable gain amplifier and then input to the baseband module 3. The first and second local oscillation signals are generated by a local oscillator (LO) 29 made of, for example, a frequency synthesizer.

  In the baseband module 3, demodulation processing is first performed on the input second intermediate frequency signal, thereby reproducing the received baseband signal. Then, a decoding process is performed on the reproduced reception baseband signal, thereby reproducing the reception data. The reproduced received data is converted into an analog signal and then input to the user interface 4. The user interface 4 includes a speaker and an LCD display, and outputs the input received signal from the speaker.

  The baseband module 3 includes a reception level detector. In this reception level detector, the received signal strength is detected from the second intermediate frequency signal input from the RF unit 2 at a constant sampling period, and a received signal strength indication signal (RSSI) indicating the detected received signal strength is detected. : Received Signal Strength Indicator) to the control unit 5.

  The control unit 5 includes a central processing unit (CPU) 51 and a digital / analog (D / A) converter 52. The CPU 51 sets the AGC control mode to either the high speed mode or the low speed mode according to the operating state of the wireless device. Then, for each of the set modes, an AGC control voltage (digital signal) is calculated by performing an operation with a different algorithm based on the RSSI output from the baseband module 3, and the calculated AGC control voltage (digital signal) is calculated. Signal) to the D / A converter 52.

  The D / A converter 52 generates first and second AGC control voltages (analog signals) AGC1 and AGC2 having different ratios based on the AGC control voltage (digital signal) output from the CPU 51, respectively. The generated first and second AGC control voltages (analog signals) AGC1 and AGC2 are supplied to the intermediate frequency amplifier 28 and the first high frequency amplifier 22, respectively.

Next, the AGC operation in the radio device configured as described above will be described. FIG. 2 is a flowchart showing the AGC control voltage setting processing procedure and its processing contents in the CPU 51.
When a radio signal is received by the antenna 1, the second intermediate frequency signal down-converted by the RF unit 2 is input to the baseband module 3. In the baseband module 3, demodulation and decoding processing are performed on the input second intermediate frequency signal, signal strength is detected at a constant sampling period, and RSSI indicating the detected received signal strength is the CPU 51. Is output.

  On the other hand, CPU51 takes in RSSI output from the said baseband module 3 by step S2a. At the same time, in step S2b, it is determined whether to set "high speed mode" or "low speed mode" as the AGC control mode based on the operating state of the radio. For example, the “high speed mode” is set when high speed response is required, such as when voice communication starts or when a handoff is performed. On the other hand, when it is necessary to absorb a rapid change in the received signal level due to multipath fading or the like during the steady reception operation period, the “low speed mode” is set.

  For example, it is assumed that “high speed mode” is set in step S2b with the start of communication. In this case, the CPU 51 proceeds to step S2c and executes the high-speed mode process as follows. FIG. 3 is a flowchart showing the AGC control voltage calculation processing procedure and the processing content in the high-speed mode.

  That is, the CPU 51 first sets an integration coefficient α necessary for high speed pull-in in step S3a. Next, an integration process is executed in step S3b according to the set integration coefficient α. FIG. 5 shows an example of the contents of the integration process. For example, in the high speed mode, the integration coefficient α is set to α = 0.95, for example. Then, the weighting unit 61 weights the input current RSSI with the integration coefficient α, and the weighting unit 63 sets the integration coefficient 1-α to the integration output one sample period delayed by the delay unit 62. Perform weighting. Subsequently, the weighted current RSSI is added by the adder 64 to the weighted integrated output one sample period before, and the value after this addition is used as a new integrated output. In step S3c, an AGC control voltage (digital signal) is calculated based on the calculated new integrated output.

  When the integration process in the high-speed mode is completed, the CPU 51 then proceeds to step S2e, where the values of the first and second AGC control voltages AGC1, AGC2 are set based on the calculated AGC control voltage. . The values of the first and second AGC control voltages AGC1 and AGC2 are set to, for example, 1: 6 with respect to the calculated AGC control voltage value. The set control voltages AGC 1 and AGC 2 are applied to the D / A converter 52.

The D / A converter 52 converts the first and second AGC control voltages AGC1 and AGC2 supplied from the CPU 51 into analog signals, and then supplies them to the intermediate frequency amplifier 28 and the first high frequency amplifier 22, respectively. .
Thus, AGC control is performed in the high-speed mode using the integral coefficient α = 0.95 in an operation state where high-speed response is required, such as when voice communication is started or handoff is started.

  On the other hand, it is assumed that the reception operation state of the wireless device shifts to a steady state, and accordingly, the “low speed mode” is set in step S2b. In this case, the CPU 51 proceeds to step S2d and executes the low speed mode process as follows. FIG. 4 is a flowchart showing an AGC control voltage calculation processing procedure and processing contents in the low speed mode. The processing in the low speed mode includes delay processing and smoothing processing.

  That is, first, in step S4a, the CPU 51 sets an integral coefficient α necessary for delay processing and an upper limit value (for example, n = 10) of the count value n representing the delay time. Next, after resetting the counter in step S4b, the delay process in steps S4i, S4j and steps S4c to S4e is repeated until the value of the counter reaches a value corresponding to the delay time.

  That is, first, the count value n is initialized to 0 in step S4b. Next, in step S4i, RSSI is taken in, and in step S4j, it is determined whether or not the low-speed mode should be continued based on the operating state of the radio. If it is determined that the low-speed mode should be continued as a result of the determination, the process proceeds to step S4c, and the RSSI fetched is integrated according to the integration coefficient previously set in step S4a. At this time, the integration coefficient α is set to 0.05, for example, and the integration process shown in FIG. 5 is performed according to the integration coefficient α = 0.05. Subsequently, the count value n is incremented by 1 in step S4d. In step S4e, it is determined whether the count value n has reached the upper limit value (n = 10). As a result of the determination, if the count value n has not reached the upper limit value, the process returns to step S4c and the above steps S4c to S4e are repeated.

  On the other hand, when the count value reaches the upper limit value (n = 10), the CPU 51 proceeds to step S4f, where the AGC control voltage (digital signal) is calculated based on the calculated integrated output. If the high speed mode is determined in step S4j during the execution of the delay process, the high speed mode is immediately entered, and the high speed mode process described above is executed in step S4k.

  Next, CPU51 performs the smoothing process of AGC control voltage as follows by step S4g-step S4h. That is, first, in step S4g, an integral coefficient necessary for smoothing processing is set for the calculated AGC control voltage (digital signal). Subsequently, in step S4h, an integration process is performed according to the set integration coefficient. This integration processing is performed in the same manner as the processing described above with reference to FIG. In this case, however, the integration coefficient α is set to 0.05, for example.

  When the delay process and the smoothing process in the low speed mode are completed, the CPU 51 then proceeds to step S2e, where the first and second AGC control voltages AGC1 and AGC2 are obtained based on the calculated AGC control voltage. Set. Also in this case, as in the case of the high-speed mode described above, the values of the first and second AGC control voltages AGC1 and AGC2 are set to 1: 6 with respect to the calculated AGC control voltage value. The set control voltages AGC 1 and AGC 2 are applied to the D / A converter 52.

  Thus, after the radio reception operation state shifts to the steady state, AGC control is performed in the low-speed mode using the delay processing for RSSI and the smoothing processing for the calculated AGC control voltage.

  As described above, in this embodiment, the CPU 51 sets the AGC control mode to either the high speed mode or the low speed mode in accordance with the operating state of the wireless device. When the high-speed mode is set, the RSSI is integrated with an integration coefficient α = 0.95, an AGC control voltage (digital signal) is calculated based on the integration output, and based on the AGC control voltage. The gains of the intermediate frequency amplifier 28 and the first high frequency amplifier 22 are controlled. On the other hand, when the low speed mode is set, after delaying the RSSI, an AGC control voltage is calculated based on the integrated output, and further, a smoothing process is performed on the calculated AGC control voltage. The gains of the intermediate frequency amplifier 28 and the first high frequency amplifier 22 are controlled based on the AGC control voltage after the smoothing process.

  Therefore, AGC control is performed in the high-speed mode using the integration coefficient α = 0.95 in an operation state where high-speed response is required, such as when voice communication is started or handoff is started. High-quality voice communication can be performed without disconnection or the like. On the other hand, after the reception operation state of the radio device has shifted to a steady state, a low-speed mode is set, and a rapid change in reception level is tracked by combining delay processing for RSSI and smoothing processing for AGC control voltage. Stable reception level control can be realized. For this reason, it is possible to absorb a change in reception level due to fading or the like and maintain high quality reception quality.

In addition, in the low-speed mode, as described above, the delay process for RSSI and the smoothing process for the AGC control voltage can be controlled independently, so that the optimum response characteristic can be set more flexibly.
Furthermore, in this embodiment, AGC control processing is realized by software processing by the CPU 51. For this reason, it is possible to change various parameters for AGC control relatively easily, and it is possible to easily set optimal AGC control characteristics for each model of radio equipment or according to the usage form of the radio equipment.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, either the high-speed mode or the low-speed mode is adopted. However, the mode is not limited to the above two modes, and other modes such as the medium-speed mode are increased according to the operation state of the radio. May be. In the above embodiment, AGC control is realized by software processing by the CPU 51, but may be realized by hardware.
In addition, the type of wireless device, the circuit configuration of the wireless unit, the AGC control voltage calculation procedure, the processing content, and the like can be variously modified without departing from the scope of the present invention.

  In short, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

The circuit block diagram which shows the structure of the radio | wireless modulation / demodulation part provided in the radio | wireless machine provided with the AGC function concerning one Embodiment of this invention. The flowchart which shows the process sequence and processing content of AGC control voltage setting in the radio | wireless machine shown in FIG. The flowchart which shows the high-speed mode processing procedure and processing content shown in FIG. The flowchart which shows the low-speed mode processing procedure and processing content shown in FIG. The figure which shows an example of the processing content of the integration process shown to FIG. 3 and FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Antenna, 2 ... RF unit, 21 ... 1st high frequency filter, 22 ... 1st high frequency amplifier, 23 ... 2nd high frequency filter, 24 ... 2nd high frequency amplifier, 25 ... 1st mixer, 26 ... Intermediate frequency filter, 27 ... second mixer, 28 ... intermediate frequency amplifier, 29 ... local oscillator, 3 ... baseband module, 4 ... user interface, 5 ... control unit, 51 ... CPU, 52 ... D / A converter, 61 ... Weighter, 62 ... Delayer, 63 ... Weighter, 64 ... Adder.

Claims (2)

A radio having an automatic gain control function for adjusting a signal level of a received signal by a variable gain amplifier,
A detection circuit for detecting a signal level of a reception signal output from the variable gain amplifier;
A control circuit connected to the detection circuit and the variable gain amplifier,
The control circuit includes:
A first control mode that operates at a first response speed set in advance according to an operating state of the radio, and a second control mode that operates at a second response speed that is lower than the first response speed. Means for alternatively selecting
When the first control mode is selected, the signal level detected by the detection circuit is integrated with a first integration coefficient, and a control voltage for the variable gain amplifier is generated based on the integration value. Means for providing to the variable gain amplifier;
When the second control mode is selected, the signal level detected by the detection circuit is integrated with a second integration coefficient smaller than the first integration coefficient, and the number of integrations is counted. When the number of times reaches a predetermined number corresponding to the delay time, a control voltage of the variable gain amplifier is generated based on the integration value, and the generated control voltage is used as a third integration necessary for the smoothing process. Means for integrating and smoothing with a coefficient, and then applying to the variable gain amplifier. A radio comprising: a variable gain amplifier that adjusts the signal level of a received signal; a detection circuit that detects the signal level of the received signal output from the variable gain amplifier; and a processor connected to the detection circuit and the variable gain amplifier. An automatic gain control program used in a machine,
A first control mode that operates at a first response speed set in advance according to an operating state of the radio, and a second control mode that operates at a second response speed that is lower than the first response speed. Processing to select alternatively,
When the first control mode is selected, the signal level detected by the detection circuit is integrated with a first integration coefficient, and a control voltage for the variable gain amplifier is generated based on the integration value. Processing to the variable gain amplifier
When the second control mode is selected, the signal level detected by the detection circuit is integrated with a second integration coefficient smaller than the first integration coefficient, and the number of integrations is counted. When the number of times reaches a predetermined number corresponding to the delay time, a control voltage of the variable gain amplifier is generated based on the integration value, and the generated control voltage is used as a third integration necessary for the smoothing process. An automatic gain control program that causes the processor to execute processing that is integrated and smoothed by a coefficient and then applied to the variable gain amplifier.

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