JPH08181295A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE: To provide a nonvolatile memory device which facilitates the low voltage writing and a long charge holding time and, further, protects the ON- voltage Vth of its control gate from the influence of a drain voltage. CONSTITUTION: An insulating film 3 is formed on the surface of a substrate 2. A floating gate 4 is provided in the insulating film 3 so as to be approximately in parallel with the substrate 2 surface. Further, a gate 6 having a control gate 5 is provided on the insulating film 3. In a nonvolatile memory device 1 like this, the floating gate 4 is composed of a plurality of discrete electrode patterns 4a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate type charge storage nonvolatile memory element.

[0002]

2. Description of the Related Art A non-volatile memory element is an element that retains stored information even when power is turned off. Among these, a charge storage nonvolatile memory element is one in which charges are stored in the insulating film formed under the gate electrode of the MIS FET by some method and information is stored by the charges. The portion in which the above-mentioned charges are accumulated is a so-called charge accumulation node, and in this element, the ON voltage Vth of the gate electrode of the MIS FET is changed by the charges accumulated in the charge accumulation node, and this change is taken out as information. Therefore, the charge storage nonvolatile memory element is required to meet the following three conditions.

(1) The change in Vth is large when charge is accumulated in the charge accumulation node and when it is not accumulated. (2) The change in Vth when the drain voltage is changed is
Small compared to the change in Vth when charge is accumulated in the charge accumulation node and when it is not accumulated. (3) The charge accumulated in the charge storage node does not easily leak to the outside, and the charge does not easily enter the charge storage node from the outside.

Since the information stored in the charge storage node cannot be read if the change in Vth is small, (1) is the most basic condition in the charge storage nonvolatile storage element. If the condition (2) is not satisfied, the change in Vth when the drain voltage is changed is erroneously read as information, so (2) is a condition necessary for reading the information accurately. Furthermore, (3) is a condition necessary for long-term storage of the information stored in the charge storage node.

By the way, the widely known charge storage nonvolatile memory elements are roughly classified into a floating gate type (hereinafter referred to as FG type), an MNOS type and an M type.
There are two types, the ONOS type. As shown in FIG. 5, the FG type has an insulating film 52 on the surface of the semiconductor substrate 51, for example, a floating gate 53 made of polysilicon, and an insulating film 54.
The gate 57 has a structure of a gate 57 in which a control gate 55 as a gate electrode is sequentially stacked, and the floating gate 53 is used as a charge storage node.

On the other hand, the MNOS type has a gate structure in which a silicon oxide film 61, a silicon nitride film 62 and a gate electrode 63 are sequentially stacked on a surface of a semiconductor substrate 51, as shown in FIG. The MONOS type is shown in FIG.
As shown in (b), it further has a gate structure in which a silicon oxide film 64 is interposed between the silicon nitride film 62 and the gate electrode 63. Such MNOS type and M
In the ONOS type, a large number of interface states are generated at the interfaces between the silicon oxide films 61 and 64 and the silicon nitride film 62, so that holes are trapped at these interfaces to accumulate charges.

[0007]

By the way, in the FG type charge storage nonvolatile memory element shown in FIG. 5, since the floating gate 53 is embedded in the insulating films 52 and 54, sufficient charge can be obtained. Can be stored in Vth
Although it has the advantage of large changes, there are two major problems.

First, there is a problem that it is difficult to achieve both the reduction of the write voltage and the extension of the charge retention time. That is, in order to reduce the write voltage, the insulating film 5 between the floating gate 53 and the semiconductor substrate 51 is reduced.
2 needs to be thin, but the thickness of the insulating film 52 is about 1
Since there is a minute variation of about nm, when the insulating film 52 is thinned, a very thin portion locally occurs. Since the floating gate 53 is a conductor and the charge freely moves in the floating gate, if the insulating film 52 has a very thin portion, the charge leaks to the outside. In addition, the electric charge from the outside easily penetrates into the floating gate 53 through the thin portion of the insulating film 52, and as a result, the electric charge holding time is shortened. Therefore, in order to lengthen the charge retention time, it is necessary to secure a film thickness sufficient for accumulating charges, including the thinnest portion, and in that case, the writing voltage becomes high.

Another problem is that the Vth of this memory element is easily affected by the drain voltage. The floating gate 53 is made of polysilicon having a high dielectric constant, and the potential is substantially uniform in the floating gate 53.
This is because the influence of the portion of the diffusion layer 56 formed in 1 overlapping with the drain spreads over the entire floating gate 53. Especially when the width of the gate 57 becomes smaller, the floating gate 5 is
Since the ratio of the overlapping width of 3 and the drain becomes large, the influence of the drain voltage on Vth becomes remarkable.

On the other hand, in the MNOS type non-volatile memory element shown in FIG. 6A and the MONOS type non-volatile memory element shown in FIG. 6B, they are accumulated at the interface between the silicon oxide films 61 and 64 and the silicon nitride film 62. Since the electric charges hardly move due to the existence of the interface state, it is difficult for the electric charges to leak to the outside from the silicon oxide films 61 and 64. Therefore, the stored information can be stored for a long time, that is, the charge retention time can be extended, and the silicon oxide film 61 can be thinned, so that the writing voltage can be reduced. In addition, since the silicon nitride film 62 has a much lower dielectric constant than polysilicon,
Vth is unlikely to be affected by the drain voltage.

However, in this element, since the charges are accumulated at the interface between the silicon oxide films 61 and 64 and the silicon nitride film 62, the amount of accumulated charges is small. As a result, when the charges are accumulated and when the charges are not accumulated. Since the change in Vth is small, there is a big problem that the basic conditions required for the charge storage nonvolatile memory element are not satisfied. Therefore, the MNO can be written at a low voltage, the charge holding time is long, and the Vth is hardly influenced by the drain voltage.
It is desired to develop an FG type charge storage nonvolatile memory element having the advantages of S type and MONOS type.

[0012]

According to the present invention, an insulating film is formed on a surface of a substrate, a floating gate is provided in the insulating film substantially parallel to the surface of the substrate, and a control gate is provided on the insulating film. In the nonvolatile memory element having a gate formed with, the above floating gate is constituted by a plurality of independent electrode patterns. This electrode pattern is preferably formed by forming diffusion layers on both sides of the gate of the substrate and forming a stripe shape in a direction intersecting the direction connecting the diffusion layers, or in the direction connecting the diffusion layers and in the direction intersecting the diffusion layers. It is preferable that they are separated from each other.

[0013]

In the nonvolatile memory element of the present invention, since the floating gate is composed of a plurality of independent electrode patterns, the movement of accumulated charges is restricted within the electrode pattern for each electrode pattern. Therefore, even if the drain voltage is changed, the influence of the change does not reach the entire floating gate, so that the change in the on-voltage Vth of the control gate due to the change in the drain voltage can be suppressed low. In addition, since the movement of accumulated charge is restricted within each electrode pattern for each electrode pattern, when the insulating film between the substrate surface and the floating gate is thinned, a very thin portion is locally formed. However, the electric charge leaked from the floating gate to the outside is only the electric charge accumulated in the electrode pattern existing immediately above the thin portion. Further, the invasion of charges from the outside can be suppressed only by the electrode pattern existing immediately above the thin portion.

If the electrode pattern is formed in a stripe shape in a direction intersecting the direction connecting the diffusion layers, a channel formed between the diffusion layers by applying a voltage to the control gate is divided by the electrode pattern. Therefore, the movement of the accumulated charges is restricted within the individual electrode patterns. Therefore, even if the drain voltage is changed, the influence thereof is prevented from reaching the entire floating gate, so that the change in Vth when the drain voltage is changed can be surely suppressed to be low.

Further, if the electrode patterns are separated in the direction connecting the diffusion layers and in the direction intersecting the diffusion layers, the unit of one electrode pattern becomes smaller than that of the above electrode patterns, so that it floats on the substrate surface. Even if the insulating film between the gate and the gate is thinned, even if a very thin part is locally generated, leakage of charges from the floating gate to the outside or intrusion of charges from the outside to the floating gate is further increased. It will be kept low.

[0016]

Embodiments of the nonvolatile memory element of the present invention will now be described with reference to the drawings. Prior to this, the schematic structure of the present invention will be described with reference to FIG. That is, the nonvolatile memory element 1 of the present invention includes the insulating film 3 formed on the surface of the base 2, the floating gate 4 provided in the insulating film 3 substantially parallel to the surface of the base 2, and the insulating film 3. 3 has a gate 6 composed of a control gate 5 formed above the floating gate 3 and the floating gate 4 is constituted by a plurality of independent electrode patterns 4a.

A first embodiment of the nonvolatile memory element 1 having such a schematic structure will be described with reference to FIG. Figure 2
2A is a side sectional view, and FIG. 3B is a sectional view taken along the line AA in FIG.

In the nonvolatile memory element 11 shown in FIG. 2, the substrate 12 is made of single crystal silicon containing 10 ¹⁶ (atoms / cm ³ ) of boron. The insulating film 13 formed on the surface of the base 12 and made of silicon oxide and having a thickness of about 28 nm
A floating gate 14 made of polysilicon having a thickness of about 20 nm provided in the insulating film 13, and the insulating film 1
The gate 16 is formed by the control gate 15 having a thickness of about 100 nm formed on the gate electrode 3. At this time, the width of the gate 16 is formed to be about 600 nm.

The substrate 12 has a drain 16 and a source diffusion layer 1 in which arsenic is introduced on both sides of the gate 16.
7 and 17 are formed. The diffusion layers 17 and 17 are
It is formed from the surface of the substrate 2 to a depth of about 100 nm, and the concentration of arsenic in the diffusion layers 17, 17 is 10 at maximum.
^{It is 21} (atoms / cm ³ ).

The insulating film 13 is composed of a tunnel insulating film 13a having a thickness of about 3 nm formed on the surface of the substrate 12 and an under-gate insulating film 13b having a thickness of about 25 nm formed on the upper surface of the tunnel insulating film 13a. Are arranged on the tunnel insulating film 13a.

The floating gate 14 is composed of a plurality of independent electrode patterns 14a ... The electrode patterns 14a ... Are striped with a width of about 80 nm in the direction intersecting the direction connecting the diffusion layers 17, 17. Is formed in. Also, the electrode patterns 14a, 14a
The space between them is embedded in the under-gate insulating film 13b, and the insulating film 13b is formed from the upper surface of the electrode pattern 14a ...
The thickness of the lower gate insulating film 3b up to the upper control gate 15 is about 5 nm.

Nonvolatile storage element 1 having such a structure
In the case of forming, the element isolation region (not shown) is first formed in the base 12 by the LOCOS method. Then
A tunnel insulating film 13a having a thickness of about 3 nm is formed on the surface of the substrate 12 in the region surrounded by the element isolation regions by the thermal oxidation method.

Next, by thermal CVD, polysilicon for forming the floating gate 14 is deposited to a thickness of 20 nm on the tunnel insulating film 13a, and then polysilicon is formed on the stripe-shaped electrode pattern 14a by lithography and etching. . At this time, the diffusion layers 17, which will be formed in a later step, are stripe-shaped in a direction intersecting the direction connecting the diffusion layers 17, and the width of each electrode pattern 14a is about 8 mm.
The electrode pattern 14a is formed so as to have a thickness of 0 nm. Then, the surface of each electrode pattern 14a is oxidized.

Next, the under-gate insulating film 1 made of silicon oxide is formed on the electrode patterns 14a ... By thermal CVD.
3b is formed to a film thickness of about 5 nm. At this time, the under-gate insulating film 13 is formed so as to fill the gap between the electrode patterns 14a. Then, polysilicon for forming the control gate 15 is deposited to a thickness of 100 nm by the thermal CVD method, and then the tunnel insulating film 13a, the electrode pattern 14a, the under-gate insulating film 13b and the polysilicon layer are formed by lithography and etching. Laminated body 600n
The gate 16 having a width of m is formed.

Then, the substrate 1 is formed by using the gate 16 as a mask.
After introducing arsenic into the substrate 2, heat treatment is performed to form the diffusion layer 1 on the substrate 12.
7 and 17 are formed. Through the above steps, the non-volatile memory element 11 shown in FIG. 1 is formed.

Nonvolatile storage element 1 formed in this way
In 1, the floating gate 14 serves as a charge storage node and the control gate 15 serves as a gate electrode. Of these, the electrode patterns 14a forming the floating gate 14 are embedded in the insulating film 13, so that a sufficient charge storage amount can be secured.
Therefore, there is a large change in Vth when charge is accumulated in the floating gate 14 and when it is not accumulated.

Further, since the floating gate 14 is composed of a plurality of independent electrode patterns 14a ..., The movement of the accumulated charges is restricted within the pattern 14a for each electrode pattern 14a. Therefore, even if the drain voltage is changed, the floating gate 14 as a whole is not affected by the change, and thus the change in the on-voltage Vth of the control gate 15 due to the change in the drain voltage can be suppressed low.

Moreover, the electrode pattern 14a is the diffusion layer 1
Since the stripes are provided in the direction intersecting the direction connecting 7 and 17, the control gate 15
Channels generated between the diffusion layers 17 by applying a voltage to the electrodes are divided by the electrode patterns 14a. Therefore, the movement of the accumulated charges is individually restricted within the electrode pattern 14a, so that the change of the ON voltage Vth of the control gate 15 due to the change of the drain voltage can be surely suppressed to be low.

Therefore, even if the ratio of the overlapping width of the floating gate 14 and the diffusion layer 17 of the drain to the width of the gate 16 is large, the influence of the drain voltage on Vth can be suppressed to a low level. The information can be accurately read without erroneously reading the change in Vth as a change as information.

Further, the movement of the accumulated charge is caused by the electrode pattern 14
Since it is limited to the pattern 14a for each a,
Even if the tunnel insulating film 13a is thinned and a very thin portion is locally generated, the electric charge leaked from the floating gate 14 to the outside is present in the electrode pattern 14a immediately above the thin portion. All that is needed is the charge stored in. Further, the intrusion of charges from the outside into the floating gate 14 can be suppressed only to the electrode pattern 14a existing immediately above the thin portion. Therefore, the tunnel insulating film 13a can be thinned while ensuring the charge retention time.

Therefore, the non-volatile memory element 11 has the advantages of the conventional FG type, and can be written at a lower voltage than the conventional FG type, and the stored information can be stored for a long time. You will be able to.

Next, a second embodiment of the present invention will be described with reference to FIG. 3A is a side sectional view and FIG. 3B is a sectional view taken along the line BB. The second embodiment differs from the first embodiment in that a plurality of independent electrode patterns 24a forming the floating gate 24 are formed.
Are points separated in the direction connecting the diffusion layers 17 and the direction intersecting the diffusion layers 17, respectively.

That is, the floating gate 24 is formed so as to divide the channel direction, and
The electrode patterns 24a are also formed in a divided state in the direction intersecting the channel direction, and each electrode pattern 24a is provided in a dot shape in this example. The formation of such a non-volatile memory element 21 is similar to that of the first embodiment described above except that the polysilicon for forming the floating gate 24 deposited on the tunnel oxide film 13a is patterned into dots by lithography and etching. To do.

In the above-mentioned nonvolatile memory element 21, since the electrode patterns 24a of the floating gate 24 are provided in a dot shape, the unit of one electrode pattern 24a is smaller than that of the electrode pattern 14a of the first embodiment. . As a result, the movement of the charges accumulated in the floating gate 24 is further restricted within the electrode pattern 24a of a small unit, so that the influence on Vth when the drain voltage is changed can be further suppressed. Become. Therefore, the change in Vth when the drain voltage changes can be reliably prevented from being erroneously read as information, and the information can be read more accurately.

Further, since the electrode pattern 24a is provided in a dot shape, even if the tunnel insulating film 13a is thinned, even if a very thin portion is locally generated, the floating gate 24 is exposed to the outside. The electric charge leaked to the electrode is only the electric charge accumulated in the small unit electrode pattern 24a existing immediately above the thin portion. Further, the intrusion of electric charges from the outside can be suppressed only to the small unit electrode pattern 24a existing immediately above the thin portion. For this reason, it is possible to further suppress the leakage of accumulated charges to the outside and the intrusion of charges from the outside as compared with the case of the first embodiment, so that the tunnel insulating film 13 is secured while ensuring the charge retention time.
The film thickness of a can be further advanced. Therefore,
The nonvolatile memory element 21 has a lower write voltage,
Moreover, the memory of information can be preserved for a longer period of time.

Next, a third embodiment of the present invention will be described with reference to FIG. In addition, in FIG. 4, (a) is a side sectional view and (b) is a sectional view taken along the line CC. In the third embodiment, the plurality of independent electrode patterns 34a forming the floating gate 34 are separated in the direction connecting the diffusion layers 17 and the direction intersecting the diffusion layers 17, respectively. In contrast, these electrode patterns 34a are formed in a granular shape.

As the electrode pattern 34a, fine particles made of a semiconductor such as polysilicon or a metal such as silver are used. When forming the nonvolatile memory element 31 in which the electrode pattern 34a is made of granular polysilicon, first, L
An element isolation region (not shown) is formed in the base 12 by the OCOS method. Then, the tunnel insulating film 1 is formed on the surface of the substrate 12 in the region surrounded by the element isolation region by the thermal oxidation method.
3a is formed.

Next, after depositing amorphous silicon on the tunnel insulating film 13a by the thermal CVD method, the amorphous silicon is subjected to rapid heat treatment (RTA). As a result, the amorphous silicon is partially turned into particles, and minute polysilicon particles that will become the electrode pattern 34a of the floating gate 34 are formed. After that, the remaining amorphous silicon is thermally oxidized, and subsequently, similarly to the first embodiment, the under-gate insulating film 13b and the control gate 1 are formed.
5, diffusion layers 17 and 17 are formed.

Through the above steps, the nonvolatile memory element 31 shown in FIG. 4 is formed. The electrode pattern 34
When the nonvolatile memory element 31 in which a is made of a granular metal is formed, the granular metal is attached to the surface of the tunnel insulating film 13a by the sputtering method after forming the tunnel insulating film 13a. Then, oxidize the surface of the metal,
Then, the under-gate insulating film 13b and the control gate 1
5, diffusion layers 17 and 17 are formed.

In such a nonvolatile memory element 31, since the electrode patterns 34a of the floating gate 34 are granular, the unit of one electrode pattern 34a is smaller than that of the electrode pattern 24a of the second embodiment. Become. As a result, the movement of the charges accumulated in the floating gate 34 is caused by the electrode pattern 34a of a smaller unit.
Therefore, the influence on Vth when the drain voltage is changed can be further reduced. Therefore, Vth when the drain voltage changes
It is possible to read the information more accurately without erroneously reading the change in as information.

Further, since the electrode pattern 34a is provided in a granular shape, even if the tunnel insulating film 13a is thinned, even if a very thin portion locally occurs,
The charges leaked from the floating gate 34 to the outside are only the charges accumulated in the minute electrode pattern 34a.
In addition, the intrusion of electric charges from the outside also causes the minute electrode pattern 3
Only 4a will be suppressed. Therefore, the leakage of accumulated charges to the outside and the intrusion of charges from the outside can be suppressed to the minimum, so that the tunnel insulating film 13a can be further thinned while ensuring the charge retention time.
Therefore, the nonvolatile memory element 31 has a write voltage lower than that of the first and second embodiments and can store information for a long period of time.

[0042]

As described above, in the nonvolatile memory element of the present invention, since the floating gate is composed of a plurality of independent electrode patterns, the accumulated charge is transferred in each electrode pattern within the electrode pattern. Since it is limited, the change in the on-voltage Vth of the control gate when the drain voltage is changed can be suppressed low. Therefore, the change in Vth when the drain voltage changes is not erroneously read as information, and the information can be read accurately. In addition, since the movement of accumulated charge is restricted within each electrode pattern for each electrode pattern, when the insulating film between the substrate surface and the floating gate is thinned, a very thin portion locally occurs. However, the charges leaked from the floating gate to the outside are only the charges accumulated in the electrode pattern existing immediately above the thin film portion, and the invasion of charges from the outside does not occur in the thin film portion. Since it is possible to suppress only the electrode pattern existing immediately above, it is possible to reduce the thickness of the insulating film between the surface of the base and the floating gate while ensuring the charge retention time. Therefore, the conventional F
Writing can be performed at a lower voltage than that of the G type, and stored information can be stored for a long period of time.

Further, if the electrode pattern is formed in a stripe shape in a direction intersecting the direction connecting the diffusion layers, the channel generated between the diffusion layers is divided by the electrode pattern, so that the accumulated charge The movement can be individually restricted within the electrode pattern, and as a result, the change in Vth when the drain voltage is changed can be suppressed low. Therefore, Vth when the drain voltage changes
It is possible to reliably prevent erroneous reading of the change of the above as information, and it is possible to read the information more accurately.

Furthermore, if the electrode patterns are separated in the direction connecting the diffusion layers and in the direction intersecting the diffusion layers, the unit of one electrode pattern becomes smaller, so that insulation between the substrate surface and the floating gate is obtained. Even if a thin film is locally generated when the film is thinned, the charges leaked from the floating gate to the outside are limited to the charges accumulated in the electrode pattern of a small unit. Since the invasion of charges is suppressed only to the electrode pattern of a small unit, the leakage of accumulated charges to the outside and the intrusion of charges from the outside can be further suppressed. Therefore, the nonvolatile memory element has a lower write voltage and can store information for a longer period of time.

[Brief description of drawings]

FIG. 1 is a schematic structural diagram of the present invention.

2A is a side sectional view for explaining the first embodiment, and FIG. 2B is a sectional view taken along the line AA of FIG.

FIG. 3A is a side sectional view for explaining the second embodiment, and FIG. 3B is a sectional view taken along the line BB of FIG.

4A is a side sectional view for explaining a third embodiment, and FIG. 4B is a sectional view taken along the line CC of FIG. 4A.

FIG. 5 is a sectional view showing a conventional example (No. 1).

6A and 6B are cross-sectional views showing a conventional example (No. 2).

[Explanation of symbols]

 1, 11, 21, 31 Nonvolatile storage element 2, 12 Base body 3, 13 Insulating film 4, 14, 24, 34 Floating gate 4a, 14a, 24a, 34a Electrode pattern 5, 15 Control gate 17 Diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (3)

[Claims] 1. An insulating film formed on the surface of a substrate, a floating gate provided in the insulating film substantially parallel to the surface of the substrate, and a control gate formed on the insulating film. A nonvolatile memory element having a gate, wherein the floating gate is composed of a plurality of independent electrode patterns. 2. The substrate has diffusion layers formed on both sides of the gate, and the electrode pattern is formed in a stripe shape in a direction intersecting a direction connecting the diffusion layers. The nonvolatile memory element according to claim 1. 3. The non-volatile memory element according to claim 1, wherein the electrode patterns are separated in a direction connecting the diffusion layers and a direction intersecting the diffusion layers.