JP2793722B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same. Conventionally, a nonvolatile semiconductor memory device such as a floating gate avalanche MOS (hereinafter referred to as FAMOS) that accumulates electric charges in a storage electrode using avalanche breakdown has been limited to storage of binary data.

Incidentally, when information is stored in an integrated storage device, the amount of stored information is larger when stored as multi-valued data than when stored as binary data. This means that the storage capacity can be substantially increased by storing the multi-value data in the storage device, which is equivalent to the improvement in the degree of integration. The present invention, when used as a non-volatile storage device, stores information as multi-valued data and is capable of substantially increasing the storage capacity.
It is an object to obtain a nonvolatile semiconductor memory device such as S.

[0003]

2. Description of the Related Art A conventional storage electrode gate MOS semiconductor device is shown in FIG. In the figure, (a) shows a conventional n-channel F
The AMOS and its write operation are shown in FIG.
The operation of the channel FAMOS and its reading will be described.
28A and 28B, reference numeral 281 denotes a p-type silicon (p-
Si) substrate, 282 is an N ⁺ type source region, 283 is N
⁺ Type drain region, 284 is a storage electrode of a storage electrode, 2
85 is a control electrode, 286 is an insulating layer between the storage electrode and the substrate,
287 is an insulating layer between the storage electrode 284 and the control electrode 285.

The operation in the case of writing will be described with reference to FIG. For writing, a high voltage (6 to 8 V) is applied between the drain and the source while a high voltage (12.5 V) is applied to the control electrode 285 as shown in the figure. As a result, substrate 2
A high reverse bias voltage is applied to the PN junction of the drain region 281 and the drain region 283, causing avalanche breakdown. The resulting high-energy charge (hereinafter simply referred to as charge) is generated and stored in the storage electrode 284.

As a result of charging of the storage electrode 284, a threshold value (hereinafter simply referred to as a threshold value) for a gate voltage after writing becomes larger than before writing. Using this change in the threshold value, the presence or absence of writing can be determined. Figure
The read operation will be described with reference to (b). For reading, a low voltage (1 V) is applied between the drain and the source, and a reading voltage (5 V) is applied to the control electrode 285. Under this operating condition, the drain current does not flow in the state where the charge is stored in the storage electrode 284 because the threshold value is high, whereas the drain current flows in the state where the charge is not stored because the threshold value is low and the write operation is not performed. Presence or absence can be determined.

[0006]

As described above, since the conventional FAMOS can only write binary data,
When using a large-capacity storage device with FAMOS, FA
It is necessary to increase the degree of integration of the MOS integrated circuit. Since increasing the degree of integration of an integrated circuit makes processing technology difficult, it is desirable to reduce the degree of integration as much as possible and obtain a large-capacity storage device at low cost. SUMMARY OF THE INVENTION An object of the present invention is to provide a storage electrode gate MOS semiconductor device capable of substantially increasing the storage capacity when applied to a storage device.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a first conductive type.
Two second conductivity type regions (2) formed on a semiconductor substrate (1)
, (3) and the half between the two second conductivity type regions (2), (3).
Storage electrode formed on conductive substrate via first insulating layer
(4) and an insulating layer (7) formed on the storage electrode (4).
Control electrode (5) and the semiconductor substrate (1)
A high reverse via at the PN junction with the second conductivity type region.
Avalanche breakdown caused by applying
The generated high-energy charge is stored in the storage electrode (4).
In the nonvolatile semiconductor memory device described above,
The structures of the electric regions are different from each other or
The structure between the semiconductor substrates is formed on one side of the second conductivity type region.
It is different on the other side, and when you enter the first data
A write voltage is applied to one side of the second conductivity type region.
And input second data different from the first data
Write to the other side of the second conductivity type region.
The writing operation is performed by applying a voltage. This
As described above, the present invention relates to a method for forming a second conductive material,
No matter which is selected as the high voltage side for the
One side (drain side)
And the other (source
Side) and the case where writing was performed with the high voltage
To make multi-valued memory possible
I made it.

FIG. 1 shows the basic structure of the present invention,
In the AMOS, a low impurity concentration region (hereinafter simply referred to as a low concentration region) is formed between one of the second conductivity type regions (the source region in the figure) and the semiconductor substrate so that one of the regions has less avalanche breakdown than the other. A case where the structure is simple will be described as an example. In the present invention, one of the two second conductivity type regions may be selected as the drain region on the high voltage side, but in the following description, one of the second conductivity type regions will be used for convenience. The drain region,
The description will be made with the position fixed as the other source region.

FIG. 1A shows the FAMOS structure (1) of the present invention, FIG. 1B shows the case where avalanche breakdown is generated on the drain side and writing is performed from the drain side, and FIG. 1C shows the avalanche breakdown on the source side. This shows a case where the data is generated and written from the source side. In Figures (a), (b) and (c), 1
Is a substrate (p-Si), 2 is a source region (N ⁺ ), 3 is a drain region (N ⁺ ), 4 is a storage electrode, 5 is a control electrode,
Reference numerals 6 and 7 denote insulating layers, and 8 denotes a low concentration region (N ⁻ ).

[0010]

The writing in the present invention will be described with reference to FIGS. 1 (b) and 1 (c). FIG. 4B shows writing from the drain region. As shown, the drain region 3 and the source region 2
In the meantime, a voltage of about 6 to 8 V is applied with the drain region 3 side as a high voltage. Then, a high voltage of about 12.5 V is applied to the control electrode 5. As a result, a high voltage in the opposite direction is applied to the PN junction between the drain region 3 and the substrate 1 to cause avalanche breakdown. The charge generated by the avalanche breakdown is attracted to the storage electrode 4 and stored. Figure (c) shows writing from the source side. As shown, the source region 2
Between the drain region 3 and the source region 2 with a high voltage
A voltage of about 8 V is applied. The control electrode 5 has 1
A high voltage of about 2.5 V is applied. As a result, a reverse bias high voltage is applied to the PN junction between the source region 2 and the semiconductor substrate 1 to cause avalanche breakdown, and the generated charges are stored in the storage electrode 4.

By the way, in the present invention, the high impurity concentration region on the side of the source region 2 (N ⁺⁾ (hereinafter, simply referred to as high density regions) N and between the substrate 1 ^- the low density region 8 is provided Therefore, the concentration gradient is gentler than the PN junction between the drain region 3 and the substrate 1. For this reason, avalanche breakdown is more likely to occur on the drain region 3 side than on the source region 2 side, and the amount of generated charges is larger due to avalanche breakdown on the drain region 3 side. Therefore, the amount of charge stored in the drain region 3 is larger than that in the source region 2. As a result, when data is written from the drain region 3 side, the source region 2
The threshold value is higher than when writing from the side, and it is possible to store information as ternary data using the difference in the threshold characteristics.

FIG. 2 shows an example of drain current-gate voltage characteristics in the present invention. Refer to FIG. 1 as necessary.
In FIG. 2, Initial is a characteristic in the case where there is no writing, (1) is a case where writing is performed by avalanche breakdown on the drain region 3 side (when the writing characteristic is good), and (2) is an avalanche in the source region 2 side This shows characteristics when writing is performed by breakdown (when writing characteristics are poor). Operating conditions for obtaining the illustrated characteristics will be described later.

As shown in the figure, when writing is performed from the drain region 3 side, the threshold voltage is higher than when writing is performed from the source region 2 side. In the characteristics shown in FIG. 2, when the voltage applied to the control electrode is set to 5 V, In
In the initial state, a large current flows through the drain, and (2)
In the state written from the source region 2 side, a small current flows to the drain, and in the state written in (1) from the drain region 3 side, the drain current is 0. Thus, by detecting the drain current, ternary stored data can be sensed. As another sensing method, the first method
The sense level voltage applied to the control electrode may be set to, for example, two sense levels of 3 V and 7 V, and applied sequentially. In this case, it is sensed by the sense level voltage of 3 V whether or not there is a write in (1) or (2). Next, a sense voltage of 7 V is used to detect which of the states (1) and (2) has been written. According to the present invention, since the data can be stored as ternary data, the integration degree is substantially 3/2 times as compared with the case of storing as binary data.
In the above description, an n-channel FAMOS has been described.
Alternatively, another nonvolatile semiconductor memory device (SAMOS, E
PROM) can be realized by the same principle.

In the above description, a case is described in which a low-concentration region is provided at the PN junction between the source region and the substrate to make writing difficult, but the present invention generates avalanche breakdown on either the drain side or the source side. In this case, the amount of charge stored in the storage electrode may be different between the case where the charge is generated on the drain side and the case where the charge is generated on the source side. However, the structure between the storage electrode and the substrate may be different between the drain region side and the source region side so that the easiness of accumulating charges generated by avalanche breakdown may be different. Further, the configurations of the drain region and the source region for differentiating the conditions under which avalanche breakdown occurs are not limited to the above-described structures, and the voltages applied to the respective parts are also shown as examples, and are not limited thereto. .

[0015]

FIG. 3 shows the FAMOS structure of the present invention shown in FIG.
An example in which (1) is a cell array will be described. In the figure, (a) is a plane, (b) is a cross section in the direction parallel to the channel,
(c) shows a cross section in a direction perpendicular to the channel.

In the figure, 21 is a substrate (p-Si), 2
2 is a source region, 23 is a drain region, 24 is a storage electrode, 25 is a control electrode, 26 and 27 are insulating layers, 28 is a low concentration region (N ⁻ ), and 29 is an isolation region. The manufacturing method of the illustrated configuration will be described later.

FIG. 4 shows a block circuit diagram of the array of FIG. In the figure, 22 is a source, 23 is a drain, 24
Is a storage electrode, and 25 is a control electrode, which correspond to the numbers in FIG. Reference numeral 28 'denotes a region having good writing characteristics, and the region 28 and the substrate 21 shown in FIG.
The low-concentration region 28 side between them is shown. In the figure, B1, B
2, B3 and B4 are supply lines for drain voltage or source voltage. W1 and W2 are voltage supply lines (wart lines) to the control electrodes.

The voltages applied to the respective voltage supply lines when writing and reading are performed by selecting an element in a portion surrounded by a dotted line in the figure are as follows. (1) When writing is performed from the drain 23 side. W1 = float, W2 = approximately 12.5V, B1 = float , B2 = GND, B3 = 6-8V, B4 = float. (2) When writing from the source 22 side. W1 = float, W2 = approximately 12.5V, B1 = float, B2 = 6-8V, B3 = GND, B4 = float. (3) In the case of reading . W1 = float, W2 = about 5V, B1 = float, B2 = GND, B3 = about 1V, B4 = float. FIG. 2 shows an example of the drain current-gate voltage characteristics in each case. In FIG. 2, (1) and (2) show the cases under the above operating conditions (1) and (2), respectively. Thus, the write
Read only for both source and drain
Since writing is possible from
Unaffected memory cells are not affected
That's why.

FIGS. 5 to 8 show an embodiment in which the write characteristics are made different by making the structure between the storage electrode and the substrate asymmetric between the drain side and the source side. FIG. 5 shows a FAMOS structure (2) of the present invention. FIG. 5A shows the FA of the present invention.
The MOS structure (2), FIG. (B) shows the case of writing from the drain region 43, and FIG. (C) shows the case of writing from the source region. 4A, 4B and 4C, reference numeral 41 denotes a substrate (p-Si), 42 denotes a source region (N ⁺ ), 43 denotes a drain region (N ⁺ ), 44 denotes a storage electrode, and 45 denotes a storage electrode. Control electrode,
46 is an insulating layer, 46 'is a thick portion of the insulating layer 46,
46 "is a thin portion of the insulating layer 46, and 47 is an insulating layer.

FIG. 4 shows a case where data is written from the drain region 43.
As shown in (b), the drain region 43 is set to a high voltage (6 to 8).
V), the source region 42 is set to 0V. When writing from the source area 42, as shown in FIG.
Is set to a high voltage (6 to 8 V), and the drain region 43 is set to 0 V.

In this embodiment, four of the insulating layers 46 are used.
The portion 6 'is thicker and the portion 46 "is thinner. Writing on the thinner 46" side is better than writing on the thicker 46' side. The writing characteristics are improved. Therefore, when writing from the drain region 43 side as shown in FIG. 4B, the writing characteristics are better than when writing from the source region 42 side as shown in FIG. 5C, and in the case of FIG. Thus, in the case of FIG. (C), the threshold value is low (see FIG. 2).

FIG. 6 shows an embodiment in which the FAMOS structure (2) of the present invention is used as a cell array. Figure (a) is a plane, figure
(b) shows a cross section parallel to the channel direction, and (c) shows a vertical cross section. In the figure, 41 is a substrate, 42 is a source region,
43 is a drain region, 44 is a storage electrode, 45 is a control electrode, 46 'is a thick portion of the insulating film, and 46 "is a thin portion of the insulating film, each corresponding to the reference numeral in FIG. The manufacturing method will be described later.

FIG. 7 shows a FAMOS structure (3) of the present invention. FIG. 7A shows the FAMOS structure (3) of the present invention, and FIG.
Shows the case where data is written from the source side, and Fig. (C) shows the case where data is written from the drain side. In FIGS. 5A, 5B and 5C, reference numeral 61 denotes a substrate (p-Si), and 62 denotes a source region (N-type).
⁺ ), 63 is a drain region (N ⁺ ), 64 is a storage electrode,
65 is a control electrode, 66 and 67 are insulating layers, and 68 is an electrode overlapping portion.

When writing from the drain region 63,
As shown in (c), the drain region 63 is set to a high voltage (6 to 8).
V), the source region 62 is set to 0V. When writing from the source area 62, as shown in FIG.
Is set to a high voltage (6 to 8 V), and the drain region 63 is set to 0 V.

In this embodiment, by making the overlapping portion between the storage electrode 64 and the drain region 63 larger than the overlapping portion of the source region, the writing characteristics from the drain region 63 are improved. I tried to do better. Therefore, the threshold value due to writing from the drain region 63 as shown in FIG.
As shown in (c), the threshold value becomes larger than the threshold value by writing from the source region 62 (see FIG. 2).

FIG. 8 shows an embodiment in which the FAMOS structure (3) of the present invention is used as a cell array. Figure (a) is a plane, figure
(b) shows a cross section parallel to the channel direction, and (c) shows a cross section perpendicular to the channel direction. In the figure, 61 is a substrate, 62
Is a source region, 63 is a drain region, 64 is a storage electrode,
65 is a control electrode, 66 and 67 are insulating layers, and 68 is an overlapping portion of the data electrode, each corresponding to the number in FIG. The manufacturing method of the illustrated configuration will be described later.

FIGS. 9 to 11 show an embodiment of a method of manufacturing the FAMOS structure (1) (the structure of FIG. 1) of the present invention. FIG.
11 to 11, the left drawing shows a cross section perpendicular to the channel direction, and the right drawing shows a cross section parallel to the channel direction. 〜 In each figure indicates the order of the steps. The same numbers in the respective drawings indicate the same parts. The manufacturing method of the present invention will be described in numerical order with reference to FIGS.

A gate oxide film 112 (about 100 to 400 １００ in thickness) is formed on a silicon substrate 111. A conductive storage electrode layer (thickness 1000) is formed on the gate oxide film 112.
Å2000 °) 113 is provided and patterned. Further, an inter-electrode oxide film 114 is formed on the storage electrode layer 113. A resist film 115 is patterned on one side of each element to form an N ⁻ -type ion-implanted region 116 (dose amount: about 1 × 10 ¹⁴ to 10 ¹⁵ atom / cm ² ).
The resist film 115 is removed, and N ⁺ -type ion-implanted regions 117 are formed on both sides of each element (a dose of about 1 × 10
¹⁵ to 10 ¹⁶ atom / cm ² ). A conductive layer (thickness: about 1000 to 2000 Å) 118 for a control electrode is deposited. The conductive layer 118 for the control electrode is patterned, and the patterned conductive layer 118 for the control electrode is further patterned.
Is used as a mask to pattern the inter-electrode oxide film 114 and the storage electrode layer 113 by self-alignment.
An interlayer insulating oxide film (film thickness of about 100 to 400) is formed on the conductive layer 118.
Å) is formed, and ion implantation of the channel cut region 117 ′ is performed. Furthermore, an interlayer insulating film (5000-1 μm)
120 is formed. Formation of contact hole, Al
The patterning of the wiring 121 and the formation of the cover film 122 are performed, and the process ends.

FIGS. 12 and 13 show the FAMOS structure of the present invention.
(2) An embodiment of a method for manufacturing (FAMOS (2) in FIG. 5) will be described. The manufacturing method of the present invention will be described in numerical order with reference to FIGS.

A gate oxide film 112 (about 100 to 400 膜厚 in thickness) is formed on a silicon substrate 111. A part of the gate oxide film 112 on which the storage electrode is to be formed is etched, and a thin film oxide film (thickness of about 100
Å) Form 123. A conductive layer (thickness: about 1000 to 2000 の) of the storage electrode is deposited and patterned so as to cover edges of boundaries between thick and thin portions of the gate oxide films 112 and 123. An oxide film is formed on the storage electrode layer 113, and N ⁺ type ion implantation regions 117 are formed on both sides of each element. Depositing a control electrode conductive layer (thickness: about 1000 to 2000 Å) 118 The subsequent processing is the same as the processing (1) in FIGS.

FIGS. 14 and 15 show the FAMOS structure of the present invention.
(3) An embodiment of a method for manufacturing (FAMOS (3) in FIG. 7) will be described. The manufacturing method of the present invention will be described in numerical order with reference to FIGS.

A gate oxide film 112 (about 100 to 400 １００ in thickness) is formed on a silicon substrate 111. A conductive layer (thickness of about 1000 to 2000 Å) of the storage electrode is formed and patterned, and an inter-electrode oxide film (thickness of about 100 to 400 １１４) 114 is formed on the surface.
Then, a resist film 115 for N-type ion implantation is applied, and one side (region 124 in the drawing) of each element is patterned to form an ion implantation region 124. Then, annealing is performed to expand the region 124. The resist film 115 is removed, and ions are implanted into both sides (regions 125 and 124 in the drawing) of each device. Alternatively, a mask is applied to the region 124 that has already been ion-implanted, and ion implantation is performed to the region 125 that has not been ion-implanted.
Conductive layer for control electrode (thickness about 1000-2000mm)
118 is deposited. The subsequent processing is shown in FIGS.
3 is the same as the processing of (1) to (3).

[0033]

According to the nonvolatile semiconductor memory device of the present invention, information can be stored as multi-value data. Therefore, a storage device having a substantial storage capacity can be obtained by the conventional integrated circuit process technology without using a specially advanced process technology.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram illustrating an example of a drain current-gate voltage characteristic and an example of a second control electrode according to the present invention.

FIG. 3 is a view showing an embodiment of a cell array having a FAMOS structure (1) of the present invention.

FIG. 4 is a diagram illustrating an operation explanatory diagram of the present invention.

FIG. 5 is a diagram showing a FAMOS structure (2) of the present invention.

FIG. 6 is a diagram showing an embodiment of a cell array having a FAMOS structure (2) of the present invention.

FIG. 7 is a view showing a FAMOS structure (3) of the present invention.

FIG. 8 is a view showing an embodiment of a cell array having a FAMOS structure (3) of the present invention.

FIG. 9 is a view showing a method (No. 1) for manufacturing a FAMOS structure (1) of the present invention.

FIG. 10 is a diagram showing a method (No. 2) for manufacturing a FAMOS structure (1) of the present invention.

FIG. 11 is a view illustrating a method (No. 3) for manufacturing a FAMOS structure (1) according to the present invention;

FIG. 12 is a view showing a method (No. 1) for manufacturing a FAMOS structure (2) of the present invention.

FIG. 13 is a view illustrating a method (No. 2) of manufacturing a FAMOS structure (2) according to the present invention;

FIG. 14 is a view showing a method (No. 1) for manufacturing a FAMOS structure (3) of the present invention.

FIG. 15 is a view showing a method (part 2) for manufacturing a FAMOS structure (3) of the present invention.

FIG. 16 is a diagram showing a conventional storage electrode MOS semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate (p-Si) 2 Source region 3 Drain region 4 Storage electrode 5 Control electrode 6 Insulating layer 7 Insulating layer 8 Low concentration area (area with different writing characteristics)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (5)

(57) [Claims] 1. Two first conductivity type regions (2) and (3) formed on a first conductivity type semiconductor substrate (1), and the two second conductivity type regions (2) and (3). A storage electrode (4) formed on a semiconductor substrate between the storage electrodes via a first insulating layer, and a control electrode (5) formed on the storage electrode (4) via an insulating layer (7). And a PN between the semiconductor substrate (1) and the second conductivity type region.
In a nonvolatile semiconductor memory device in which a high-energy charge generated by an avalanche breakdown generated when a high reverse bias voltage is applied to a junction is stored in a storage electrode, the first insulating layer formed on a semiconductor substrate is formed. The thickness of the above
One of the two second conductivity type regions is different from the other on the other side.
A shall, when writing the first data, one of said second conductivity type
In a square the side of applying a write voltage, when writing a second data different from the first data
A write voltage is applied to the other side of the second conductivity type. 2. A semiconductor device according to claim 1, wherein said semiconductor substrate is of a first conductivity type.
The two second conductivity type regions (2) and (3) and the two second conductivity type regions.
A first insulating layer is interposed on the semiconductor substrate between the electronic regions (2) and (3).
Storage electrode (4) formed by
And the control electrode (5) formed via the edge layer (7).
And a PN between the semiconductor substrate (1) and the second conductivity type region.
Occurs when a high reverse bias voltage is applied to the junction
High energy charge generated by avalanche breakdown
Is stored in the non-volatile semiconductor memory device that stores the
And Overlap between the storage electrode and one of the second conductivity type regions
The length is alternated between one side and the other side of the two second conductivity type regions.
Are different. When writing the first data, one of the second conductivity type
Write voltage is applied to the other side, When writing second data different from the first data
Applies a write voltage to the other side of the second conductivity type.
A nonvolatile semiconductor memory device. 3. The two second conductivity type regions (2) and (3) are
With a certain area width They are arranged in parallel, and
And that the control electrode (5) is arranged vertically.
The nonvolatile semiconductor memory according to claim 1 or 2, wherein
Storage device. 4. A method for reading and writing data.
The two second conductivity type regions (2) in the memory cell array
 , (3), two adjacent rows from the area row
Select one, set one potential to LOW and the other to HIGH
And the unselected second conductivity type region is floating in potential.
3. The method according to claim 1 or 2, wherein
Non-volatile semiconductor storage device. 5. A semiconductor device according to claim 1, wherein said semiconductor substrate is of a first conductivity type.
The two second conductivity type regions (2) and (3) and the two second conductivity type regions.
A first insulating layer is interposed on the semiconductor substrate between the electronic regions (2) and (3).
Storage electrode (4) formed by
And the control electrode (5) formed via the edge layer (7).
And a PN between the semiconductor substrate (1) and the second conductivity type region.
Occurs when a high reverse bias voltage is applied to the junction
High energy charge generated by avalanche breakdown
Of non-volatile semiconductor memory device that accumulates
In the manufacturing method, Forming an oxide film on the silicon substrate surface, A storage electrode layer is formed on the oxide film and patterned,
Forming an oxide film on the storage electrode layer, One second conductivity type region is formed between every other adjacent storage electrode.
Forming and annealing to expand the area
About The storage power in which the second conductivity type region is not formed by the process
Form a second conductivity type region only between the electrodes, or between all the storage electrodes
The process of From the step of providing a control electrode on the storage electrode via an insulating layer
Become When writing one of the second conductivity type regions as the high voltage side
And writing when the other is at high voltage
The storage electrode and one of the second conductive
The overlap length between the second conductivity type region and the
It is characterized in that one side and the other side are different from each other
Of manufacturing a nonvolatile semiconductor memory device.