KR100399380B1 - Nonvolatile Semiconductor Memory, Method of Reading from and Writing to the Same and Method of Manufacturing the Same - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a floating gate formed on a semiconductor substrate via a first insulating film; A split gate formed at a predetermined distance from the floating gate via the second insulating film; A control gate formed on at least a floating gate via a third insulating film; And a dopant diffusion layer formed on the surface of the semiconductor substrate surface capacitively coupled to the floating gate at an end of the floating gate opposite to the split gate in the channel direction, the nonvolatile semiconductor memory device having at least two cells; A nonvolatile semiconductor memory device characterized in that a split gate is alternately arranged along a channel direction with a floating gate and a split gate of another adjacent cell, and an impurity diffusion layer of one cell is capacitively coupled with a split gate of another adjacent cell. do.

Description

Nonvolatile Semiconductor Memory, Method for Reading and Writing, and Method for Manufacturing thereof Nonvolatile Semiconductor Memory, Method of Reading from and Writing to the Same and Method of Manufacturing the Same

The present invention relates to a nonvolatile semiconductor memory device, a reading and writing method thereof, and a manufacturing method thereof. More specifically, the present invention relates to a highly integrated nonvolatile semiconductor memory device having a split gate (SPG) structure cell, a read and write method thereof, and a manufacturing method thereof.

As a method of reducing the memory cell size of a nonvolatile semiconductor memory device, a virtual grounding structure has been proposed. This virtual ground type structure does not require connection of the impurity diffusion layer 52 as a bit line and a drain, and can share the source of another cell and the drain of a cell adjacent to the cell, thus omitting one bit line. can do. Therefore, cell scaling is easy and the cell area in the NOR structure can be minimized. Therefore, the virtual grounding structure is suitable for large capacity. An example of the prior art of the virtual ground type structure is described in Japanese Patent Laid-Open No. 94-196711. Hereinafter, the prior art will be described with reference to FIG. 22.

In FIG. 22, the buried bit line 51 formed in the first conductive semiconductor substrate 50 has an asymmetric structure composed of the second conductive type low concentration impurity diffusion layer and the second conductive type high concentration impurity diffusion layer 53. The impurity diffusion layer 52 overlaps with the floating gate 54a of the adjacent memory cell, and the impurity diffusion layer 53 overlaps with the floating gate 54b of the other adjacent memory cell. In short, the embedded bit line 51 acts as a source of one cell and as a drain of a cell adjacent to that cell.

However, such a virtual ground type structure is known to be susceptible to the influence of a cell adjacent to a cell when a cell is read. Therefore, there is a problem in that satisfactory reading accuracy cannot be obtained and it is difficult to obtain a multi-valued circuit.

In connection with this problem, a virtual grounded structure using an SPG structure cell is known (see Japanese Patent Application Laid-Open No. 5-152579). Specifically, as shown in FIG. 23, floating gates 62a and 62b are provided on both sidewalls of the SPG 61 in the channel direction as sidewall spacers, and control gates 63 are provided along the channel direction. . The impurity diffusion layer 65a for capacitively coupling with the floating gate 62a and the impurity diffusion layer 65b for capacitively coupling with the floating gate 62b and the SPG 61 are provided on the surface layer of the semiconductor substrate 64. . The impurity diffusion layer 65b is also capacitively coupled to the floating gate 62a of the adjacent cells.

Here, as a method of rewriting a memory cell, various methods are known. For example, electrons are injected from a substrate to a floating gate or from a floating gate to a drain using a Fowler Nordheim (FN) tunnel current. A method of injecting electrons from a source to a floating gate or from a drain to a floating gate using channel thermal electrons (CHE). Of these methods, in the memory cell having the structure shown in Fig. 23, since floating gates are formed on both sidewalls of the SPG, rewriting cannot be performed by the method of injecting electrons into the drain from the floating gate using the FN tunnel current. There is a problem that the application range of the memory cell is narrowed.

Further, as the miniaturization further progresses and the gate length becomes shorter, the breakdown voltage between the source and the drain decreases, and a write error occurs. Therefore, it is difficult to reduce the cell area.

24A is a plan view for explaining that it is difficult to reduce the cell area in the conventional example, FIG. 24B is a cross-sectional view taken along line A-A 'of FIG. 24A, and FIG. 24C is a cross-sectional view taken along line B-B' of FIG. 24A. In FIGS. 24A to 24C, 71 shows a diffusion bit line, 72 shows a low concentration impurity diffusion layer, 73 shows a high concentration impurity diffusion layer, 74 shows a floating gate, and 75 shows a control gate. 24B is a sectional view in a direction parallel to the control gate, and FIG. 24C is a sectional view in a direction perpendicular to the control gate.

If the minimum processing dimension when fabricating the nonvolatile semiconductor memory device shown in Figs. 24A-24C is F (for example, F = 0.15 µm for a 0.15 µm process), the memory cell dimension in the direction parallel to the control gate is Lg (channel length between source / drain) + F (bitline width). In such a memory cell, in order to ensure the breakdown voltage between the source and the drain when a conventional write voltage is applied to an adjacent bit line, The value of Lg needs about 0.3 micrometer. That is, when the minimum machining dimension F value is 0.15 占 퐉, Lg = 2F. As a result, the dimension of the X-direction (direction parallel to the control gate) of the memory cell is 3F. On the other hand, the Y-direction (direction perpendicular to the control gate) is 2F, which is the sum of the dimension F of the region where the floating gate and the control gate overlap each other and the dimension F of the region between the memory cells.

Therefore, the memory cell area of the virtual ground type structure according to the prior art becomes 6F ² , and it is difficult to realize the actual minimum of 4F ² .

On the other hand, also in the structure of Fig. 23, since an additional transistor (SPG transistor) is required between the source and the drain, the area occupied by this transistor has been a major obstacle in scaling.

Therefore, as long as such a SPG structure cell is adopted, an SPG region always exists, and as in the above-described structure, it is difficult to realize 4F ² , which is the actual cell area minimum.

1A to 1D are each a schematic plan view and a sectional view of a memory cell of the nonvolatile semiconductor memory device according to the first embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram of the memory cell of FIG. 1. FIG.

3A to 3C are schematic cross-sectional views of a method of manufacturing the memory cell of FIG.

4A to 4D are schematic cross-sectional views of a method of manufacturing the memory cell of FIG.

Fig. 5 is an equivalent circuit diagram when the memory cell of Fig. 1 is a 3 × 2 bit array.

6A to 6C are schematic cross-sectional views of a method of manufacturing a memory cell of Example 2 of the present invention;

7A to 7D are schematic cross-sectional views of a method of manufacturing a memory cell of Example 2 of the present invention;

8A to 8D are schematic plan and sectional views of a memory cell of the nonvolatile semiconductor memory device according to the third embodiment of the present invention, respectively.

FIG. 9 is a schematic diagram for describing a memory cell region of FIG. 8; FIG.

10A and 10B are schematic cross-sectional views of a method of manufacturing a memory cell of Example 3 of the present invention;

11A and 11B are schematic cross sectional views of a method of manufacturing a memory cell of Example 3 of the present invention;

12A and 12B are schematic cross-sectional views of a method of manufacturing a memory cell of Example 3 of the present invention;

13A and 13B are schematic cross sectional views of a method of manufacturing a memory cell of Example 3 of the present invention;

14 is a schematic cross-sectional view of a method of manufacturing a memory cell of Example 3 of the present invention;

15A and 15B are schematic cross-sectional views of a method of manufacturing a memory cell of Example 4 of the present invention;

16A and 16B are schematic cross-sectional views of a method of manufacturing a memory cell of Example 5 of the present invention;

Fig. 17 is a schematic cross sectional view of a method of manufacturing a memory cell of Example 6 of the present invention;

18A and 18B are schematic cross sectional views of a method of manufacturing a memory cell of Example 8 of the present invention;

19A and 19B are schematic cross sectional views of a method of manufacturing a memory cell of Example 8 of the present invention;

20A and 20B are schematic cross sectional views of a method of manufacturing a memory cell of Example 8 of the present invention;

21A and 21B are schematic cross sectional views of a method of manufacturing a memory cell of Example 8 of the present invention;

Fig. 22 is a schematic sectional view of a memory cell of a conventional nonvolatile semiconductor memory device.

Fig. 23 is a schematic sectional view of a memory cell of a conventional nonvolatile semiconductor memory device.

24A and 24B are schematic plan and cross-sectional views, respectively, of a memory cell of a conventional nonvolatile semiconductor memory device;

According to the present invention, there is provided a semiconductor device comprising: a floating gate formed on a semiconductor substrate via a first insulating film; A split gate SPG formed at a distance from the floating gate through the second insulating layer; A control gate formed on at least a floating gate via a third insulating film; And a dopant diffusion layer formed on a semiconductor substrate surface layer capacitively coupled to the floating gate at an end of the floating gate opposite to the split gate in a channel direction, comprising: a floating gate of one cell; A nonvolatile semiconductor memory device is provided in which split gates are alternately arranged along the channel direction with floating gates and split gates of other adjacent cells, and an impurity diffusion layer of one cell is capacitance-defective with the split gate of another adjacent cell. do.

In addition, the present invention provides a method for reading data from the nonvolatile semiconductor memory device, the method comprising: grounding a dispersion diffusion layer of one cell and applying a potential to an impurity diffusion layer of another adjacent cell, or a dispersion diffusion layer of one cell; Provided is a method of reading data from one cell by applying a potential to the impurity diffusion layer of another adjacent cell to ground.

Further, according to the present invention, in the method of reading data from the nonvolatile semiconductor memory device of claim 1, the potential is applied by applying a potential to the split gate of one cell and not applying the potential to the split gate of another adjacent cell. By isolating one cell from another adjacent cell, a method is provided for reading data from one cell.

Further, according to the present invention, in the method for writing and writing data to or from the nonvolatile semiconductor memory device, the FN tunnel current flowing between the floating gate and the semiconductor substrate or between the floating gate of one cell and the impurity diffusion layer is used. A method of writing / erasing data is provided.

Further, according to the present invention, in the method of writing data to the nonvolatile semiconductor memory device, a current is applied by applying a predetermined potential to the impurity diffusion layer of one cell and grounding the impurities diffusion layer of another cell, In addition, a method of writing data into a cell by applying a first current to a split gate to scan hot electrons from an end portion of the split gate with the channel region facing the split gate in an inverted state is provided.

According to the present invention, in the method of writing data to the nonvolatile semiconductor memory device of claim 1, a current is applied by applying a predetermined potential to the impurity diffusion layer of one cell and grounding the impurity diffusion layer of another cell. In addition, a method of writing data of one cell by applying a second current to the split gate to scan hot electrons from the impurity diffusion layer of the one cell with the channel region opposing the split gate in a strongly energized state is provided.

According to the present invention, (a1) forming at least two cells on a semiconductor substrate by forming at least two floating gates with a predetermined gap in a channel direction through a first insulating film; (b1) forming two split gates on one side of each floating gate in the channel direction on the semiconductor substrate via a second insulating film; (c1) By forming an impurity diffusion layer in the surface layer of the semiconductor substrate between the floating gate of one cell and the split gate of another cell, the impurity diffusion layer is capacitively coupled to both the floating gate of one cell and the split gate of another cell. Making it possible; (d1) A method of manufacturing a nonvolatile semiconductor memory device is provided, which includes forming a control gate on each floating gate via a third insulating film.

According to the present invention, (a2) forming at least two cells on a semiconductor substrate by forming at least two floating gates at predetermined intervals in a channel direction through a first insulating film; (b2) forming an impurity diffusion layer in the semiconductor substrate surface layer on one side of each floating gate by using a floating gate as a mask or implanting impurities from an oblique direction using a mask formed on the floating gate; (c2) forming two trenches in the semiconductor substrate including a portion of the impurity diffusion layer using each floating gate as a mask or using a mask formed on the floating gate; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate with a third insulating film interposed therebetween.

In addition, according to the present invention, (a2) to form at least two cells on a semiconductor substrate, forming at least two floating gates at predetermined intervals in a channel direction via a first insulating film; (b2) forming an impurity volatilization layer on the semiconductor substrate surface layer on one side of each floating gate by implanting impurities from an oblique direction using a floating gate as a mask or a mask formed on the floating gate; (c2) 'forming a sidewall spacer on the sidewall of each floating gate, and using the floating gate and the sidewall spacer as a mask to form two trenches in the semiconductor substrate including a portion of the impurity diffusion layer; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate with a third insulating film interposed therebetween.

In addition, according to the present invention, (a2) to form at least two cells on a semiconductor substrate, forming at least two floating gates at predetermined intervals in a channel direction via a first insulating film; (b2) "implanting and annealing at least a region between the floating gates using a floating gate as a mask or a mask formed on the floating gate; (c2)" sidewalls on the sidewalls of each floating gate Providing a floating impurity diffusion layer and an impurity diffusion layer in the semiconductor substrate surface layer below each sidewall spacer by forming a spacer and also forming two trenches using the floating gate and the sidewall spacers as masks; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate with a third insulating film interposed therebetween.

According to the present invention, (a2) forming at least two cells on a semiconductor substrate by forming at least two floating gates at predetermined intervals in a channel direction through a first insulating film; (b2) "implanting and annealing at least a region between the floating gates using a floating gate as a mask or a mask formed on the floating gate; (c2)" 'two trenches between at least the floating gates Providing a floating impurity diffusion layer and an impurity diffusion layer, respectively, below the ends of the floating gate extending along the sides of the trench; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate with a third insulating film interposed therebetween.

These and other objects of the present invention will be more readily understood from the following detailed description. However, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as the detailed description and the specific embodiments are merely for illustrative purposes.

According to the present invention described above, in the virtual ground type structure using the SPG structure cell, a method using FN tunnel current and a method using CHE can be used for writing data. Therefore, a nonvolatile semiconductor memory device capable of high reliability and high speed writing can be provided.

In addition, by filling the trench with an SPG transistor composed of an SPG and an impurity diffusion layer, the memory cell area can be 4F ² , which is a physical minimum, without being affected by the SPG, thereby providing a large capacity nonvolatile semiconductor memory device. Can be.

Hereinafter, the present invention will be described in more detail, but the present invention is not limited thereto.

Example 1

1A is a schematic plan view showing an example of a memory cell of the nonvolatile semiconductor memory device of the present invention. 1B is a cross-sectional view of the X1-X1 'plane (a plane parallel to the channel direction), FIG. 1C is a cross-sectional view of the Y1-Y1' plane (a plane perpendicular to the channel direction), and FIG. 1D is a Y2-Y2 'plane. It is sectional drawing of (channel direction and a perpendicular direction). 2 is an equivalent circuit of the memory cell of FIG. 1A.

1A to 1D, in the memory cell of the nonvolatile semiconductor memory device, N ⁺ impurity diffusion layers 2 and 3 are formed on the surface layer of the semiconductor substrate 1 made of P-type silicon. On the semiconductor substrate 1 between the impurity diffusion layers 2 and 3, a floating gate 5 made of polysilicon is formed via a tunnel oxide film (first insulating film 4), and the SPG 7 made of polysilicon is formed. Is formed via a gate oxide film (second insulating film) 6 made of SiO ₂ . Further, the control gate 9 is formed on the floating gate via a third insulating film made of the ONO film 8.

In addition to the above examples, the first to third insulating films may be oxide films, nitride films, and laminates thereof. The conductivity type of the semiconductor substrate and the impurity diffusion layer may be opposite to that described above. In addition, the memory cell itself may be formed in a well.

The impurity diffusion layer 2 has a function as a source in one cell and a drain in another cell adjacent to this cell. The film thickness of the tunnel oxide film may be 3 to 10 nm (for example, 9 nm) and the gate oxide film may be 5 to 30 nm (for example, 20 nm).

Hereinafter, a method of manufacturing a memory cell of the nonvolatile semiconductor memory device of FIG. 1A will be described with reference to FIGS. 3A to 4D.

First, a tunnel oxide film 4 is formed on the first conductive semiconductor substrate 1 by thermal oxidation. Next, the polysilicon layer 5a of 10 to 200 nm (eg 50 nm), the oxide film 10 of 5 to 50 nm (eg 20 nm), and 10 to 500 nm (eg 200 nm) are formed on the entire surface of the tunnel oxide film 4. The nitride films 11 are sequentially stacked. After the resist mask 12 is formed thereon, predetermined portions of the nitride film 11, the oxide film 10, the polysilicon layer 5a, and the tunnel oxide film 4 are etched away (see FIG. 3 (a)).

After the resist mask 12 is removed, thermal oxidation is performed at 600 to 1100 ° C. to form sidewall spacers 13 made of a silicon oxide film on both side walls of the polysilicon layer 5a. After the polysilicon layer 7a for SPG formation is deposited between the sidewall spacers 13, an etch back is performed until the nitride film 11 is exposed to planarize (see FIG. 3 (b)). . The nitride film 11 functions as an etch stopper.

Next, a resist mask 14 having an opening is formed on the sidewall spacer 13 between the polysilicon layer 7a of one cell and the polysilicon layer 5a of another cell adjacent in the channel direction. The semiconductor substrate 1 is exposed by removing the sidewall spacers 13 using the resist mask 14 as a mask. Next, for example, arsenic (As) is ion-implanted to form impurity diffusion layers 2 and 3 in the semiconductor substrate surface layer (see FIG. As the conditions for ion implantation at this time, the acceleration voltage is 5 to 30 kev (for example, 15 kev), and the implantation amount is 1x10 ¹³ to 1x10 ¹⁶ cm ^-2 (for example, 1x10 ¹⁴ cm ^-2 ).

Subsequently, the resist mask 14 is removed and then heat treated at 600 to 1100 ° C. (for example, 800 ° C.) to remove the sidewall spacers 13 and the silicon oxide film (insulating film) on the polysilicon layer 7a. ) (See FIG. 4D). By this heat treatment, crystallinity recovery of the implanted region and activation of the implanted impurities can be performed. In addition, the polysilicon layer 7a becomes SPG7.

Next, the nitride film 11 and the oxide film 10 are sequentially removed by etching (see FIG. 4E). This etching slightly rounds the edges of the insulating film 15, which is preferable because it helps to reduce the level difference.

Next, a polysilicon layer 5b of 40 to 400 nm (for example, 100 nm) is deposited and patterned using the resist mask 16 (see FIG. 4F). This step increases the overlapping area of the floating gate and the control gate. As a result, the gate capacitance coupling ratio is increased to enable lower voltage. In the present embodiment, the polysilicon layer 5b is formed for the same reason as above, but the polysilicon layer 5b can be omitted.

The resist mask 16 is then removed. Then, after the third insulating film and the polysilicon layer 9a made of the ONO film 8 are deposited, patterning is performed to form a word line. Accordingly, the polysilicon layers 5a, 5b, and 9a and the ONO film 8 are successively etched to form floating gates and control gates in self-alignment (see FIG. 4D).

Finally, a protective film (not shown) such as BPSG (Boron Phosphorus Silicate Glass) is deposited.

After the above steps, the nonvolatile semiconductor memory device of the present invention is completed.

Next, reading and writing operations in the memory cell will be described with reference to FIG. 5, Table 1, and Table 2. FIG. In the table, CG means control gate and FG means floating gate.

Write / erase rescue CG SPG drain sauce Board Entry 1 FN FG-substrate 20 V 0 0 0 0 Entry 2 FN FG-substrate -20V 0 0 0 0 Entry 3 FN FG-substrate -12V 0 4V 0 0 Entry 4 CHE sauce 12 V 2 V 4V 0 0 Entry 5 CHE drain 12 V 12 V 6 V 0 0

Table 1 shows the read operation, and Table 2 shows the rewrite operation. Since each of these operations is capable of a plurality of different modes, such modes will be described below.

1) Read method

As shown in the read 1 of Table 1, the drain is grounded, and the threshold value of the control gate transistor is applied when a sense voltage of 3V is applied to the control gate with 1V at the source, 3V at the SPG, and the substrate grounded. Is 3V or more, the memory cell is in an OFF state, and if it is 3V or less, the memory cell is in an ON state.

In addition, as shown in the read 2 of Table 1, the readout is similarly possible even if the voltages applied to the drain and the source are reversed.

2) Rewreiing

The memory cell according to the present invention can write data by changing the threshold voltage of the transistor by injection or discharge of electrons into the floating gate. In addition, in the data rewriting mechanism of such a memory cell, both using FN tunnel current or using CHE is applicable.

First, rewriting using the FN tunnel current will be described below.

2-1) between floating gate and substrate

Regarding the operation in this mode, as shown in writing 1 of Table 2, the drain and the substrate are grounded, and when a positive high voltage (20 V) is applied to the control gate, the channel region under the floating gate is The substrate surface becomes the drain voltage (ground potential) and the coin phase, and a high electric field of about 10 MV / cm is applied between the floating gate and the substrate, and electrons are injected from the substrate to the floating gate. On the other hand, since 0 V is applied to the source, electrons are not injected into the floating gate. As a result, only the selected memory cell increases the threshold voltage of the control gate transistor including the control gate, the floating gate, and the impurity diffusion layer. At this time, the SPG is grounded to prevent a write error to an adjacent cell.

On the other hand, as shown in writing 2 of Table 2, when the drain, the source, and the substrate are grounded and a negative high voltage (-20 V) is applied to the control gate, about 10 MV / cm between the floating gate and the substrate. A high electric field of is applied and electrons are injected into the substrate from the floating gate, so that the threshold voltage of the control gate transistor is reduced.

2-2) Between Floating Gate and Drain

As for the operation in this mode, as shown in writing 3 of Table 2, when the high potential (-12 V) is applied to the control gate with 4 V, the source and the substrate as the ground potential, and the control gate, the floating gate A high field of about 10 MV / cm is applied between the drain and the drain, and electrons are injected into the drain from the floating gate, thereby lowering the threshold voltage of the control gate transistor. At this time, the SPG is grounded to prevent a write error in an adjacent cell.

Next, rewriting using CHE will be described below.

2-3) between source side and floating gate

As shown in writing 4 of Table 2, with 4 V applied to the drain, the substrate and the source at ground potential, and a positive high voltage (12 V) applied to the control gate, the SPG was close to the threshold voltage. By applying a voltage (2 V) to make the channel region under the SPG weakly inverted, a high electric field is generated on the source side of the control gate transistor and hot electrons are injected from the source to the floating gate, thereby raising the threshold voltage of the control gate transistor. .

2-4) between drain and floating gate

As shown in writing 5 of Table 2, while the 6V is applied to the drain, the substrate and the source are at the ground potential, and the positive high voltage (12V) is applied to the control gate, the SPG is sufficiently above the threshold voltage. When a high voltage (8 V) is applied, a high electric field is generated in the drain of the control gate transistor, hot electrons are injected into the floating gate from the drain, and the threshold voltage of the control gate transistor is increased.

As described above, some operation modes have been described, and the operation modes have the following characteristics.

For example, the write / erase method combining the write 1 and write 2 modes is called a bipolarity writing / erasing system, and has a very excellent reliability. In addition, when the write 3 mode is used, the voltage can be reduced. In addition, when the write 4 mode is used, ultra-fast writing becomes possible. Write 5 is the most standard operating system, and conventional techniques are available.

In this way, one device can satisfy the required device performance, thereby extending the application range of the device.

Next, an operation when the memory cells are arranged in an array configuration will be described.

Fig. 5 shows a case where the memory cells of this embodiment are arranged in a 3x2 bit array. The array is composed of six cells of C11 to C23. Cell C12 is the selected cell. In the case of the arrangement in the array structure, a read error and a write error by adjacent cells are problematic. Here, the bias conditions between the selected cell and the unselected cell will be described below. Read conditions are shown in Table 3 and rewrite conditions are shown in Table 4.

Write / erase rescue WL1 WL2 SPG1 SPG2 SPG3 BL1 BL2 BL3 BL4 Board Entry 1 FN FG-substrate 20 V 0 0 0 0 6 V 0 6 V 6 V 0 Entry 2 FN FG-substrate -20V 0 0 0 0 0 0 0 0 0 Entry 3 FN FG-drain -12V 0 0 0 0 0 4V 0 0 0 Entry 4 CHE sauce 12 V 0 0 2 V 0 0 4V 0 0 0 Entry 5 CHE drain 12 V 0 0 8V 0 0 6 V 0 0 0

3) Read error by adjacent cell

Table 3 shows bias conditions of the selected cells C12 and adjacent non-selected cells C11, C13, and C22. As shown in the read 1 of Table 3, the unselected cell C22 connected to the word line WL2 by grounding the word line WL2 cannot affect the selection cell C12. On the other hand, reading errors of the unselected cells C11 and C13 connected to the word line WL1 can be avoided by grounding the SPG 1 and the SPG 3.

In addition, as shown in the read 2 of Table 3, even when the voltages applied to the BL2 and the BL3 are reversed, the read can be performed in the same manner and the read error by the adjacent cell can be prevented.

4) Write error to neighbor cell (FN tunneling mode)

4-1) Between Floating Gate and Substrate

Table 4 shows bias conditions of the selected cells C12 and adjacent non-selected cells C11, C13, and C22. As shown in writing 1 (electron injection from the substrate to the floating gate) in Table 4, the writing error of the unselected cell C22 connected to the word line WL2 can be prevented by grounding the word line WL2. . For the non-selected cells C11 and C13, SPG1, SPG2 and SPG3 are grounded to turn off all SPG transistors, and BL2 is grounded and a positive voltage (6 V) is applied to other BL1, BL3, BL4. The tunnel electric field of the drain regions of the selection cells C11 and C13 is relaxed to prevent electron injection into the floating gate of the non-selection cells. In this way, the problem of the write error can be solved by applying the bias voltage.

In addition, as shown in writing 2 (emission of electrons from the floating gate to the substrate) of Table 4, the writing error of the unselected cell C22 can be prevented by grounding WL2. However, since the unselected cells C11 and C13 share the word line WL1, electrons are discharged from the floating gate to the substrate in all cells connected to the same word line. In this case only batch erasing is applicable.

4-2) Between Floating Gate and Drain

As shown in write 3 (electron discharge from the floating gate to the drain) of Table 4, the write error of the unselected cell C22 can be prevented by grounding WL2. For the unselected cells C11 and C13 connected to the word line WL1, SPG1, SPG2 and SPG3 are grounded to turn off the SPG transistor, 4 V is applied to BL2, and other BL1, BL3 and BL4 are grounded. The tunnel electric field in the drain regions of the unselected cells C11 and C13 is relaxed, and electron injection into the floating gate of the unselected cells is prevented. The above application of bias can solve the problem of write error. In this case, erasing can be performed in units of bits.

4-3) Between Source-Floating Gate (CHE Mode)

As shown in write 4 (electron injection from the source to the floating gate) in Table 4, the write error of the non-selected cell C22 can be prevented by grounding WL2.

In addition, for the unselected cells C11 and C13 connected to the word line WL1, the SPG transistors of the unselected cells C11 and C13 are turned off with 2 V, SPG1 and SPG3 at SPG2 as the ground potential, and the source and the Current flow between the drains is prevented, preventing electron injection into the floating gate of the unselected cells. The above application of bias can solve the problem of read error.

4-4) Drain to Floating Gate (CHE Mode)

As shown in writing 5 (electron injection from the drain to the floating gate) in Table 4, a read error of the unselected cell C22 can be prevented by grounding WL2.

In addition, for the unselected cells C11 and C13 connected to the word line WL1, the SPG transistors of the unselected cells C11 and C13 are turned OFF with 8 V, SPG1 and SPG3 at SPG2 as the ground potentials. Current between the drains is blocked, preventing electron injection into the floating gate of the unselected cells. The above application of bias can solve the problem of write error.

Example 2

A manufacturing method in the case where a floating impurity diffusion layer is additionally provided in the nonvolatile semiconductor memory device of Fig. 1A will be described with reference to Figs. 6A to 7D.

First, the same process as in FIGS. 3A and 3B is repeated (see FIGS. 6A and 6B).

Next, the sidewall spacers 13 between the polysilicon layer 7a and the polysilicon layer 5a are removed to expose the semiconductor substrate 1. Subsequently, impurity ions are implanted under the same conditions as in FIG. 3 (c), and the impurity diffusion layers 2 and 3 and the floating impurity diffusion layer 17 are formed on the semiconductor substrate surface layer (see FIG. 6 (c)).

Then, the same process as shown in Figs. 4A to 4D is repeated to produce the nonvolatile semiconductor memory device of the present invention having the floating impurity diffusion layer 17 (see Figs. 7A to 7D). ).

The nonvolatile semiconductor memory device of the second embodiment can also use the same writing and reading methods as those of the first embodiment.

Example 3

Fig. 8A is a schematic plan view of an example of a memory cell of the nonvolatile semiconductor memory device of the present invention. 8B is a cross-sectional view of the X1-X1 'plane (the plane parallel to the channel direction (X direction)), FIG. 8C is a cross-sectional view of the Y1-Y1' plane (the plane perpendicular to the channel direction), and FIG. 8D is Y2. A cross-sectional view of the plane -Y2 '(plane perpendicular to the channel direction).

In FIGS. 8A to 8B, in the memory cell of the nonvolatile semiconductor memory device, a trench 18 is formed on a semiconductor substrate 1 made of P-type silicon, and an N ⁺ impurity diffusion layer is formed on the sidewall of the trench 18. 2 and 3) are formed. In the trench 18, an SPG 7 made of polysilicon is embedded through a gate oxide film 6 made of SiO ₂ . Further, on the flat surface of the semiconductor substrate 1 sandwiched in the trench 18, a floating gate 5 made of polysilicon is formed via the tunnel oxide film 4, and the ONO film 8 is formed on the floating gate. The control gate 9 is formed through the third insulating film formed.

In addition to the above examples, the first to third insulating films may be oxide films, nitride films and their laminating agents. The conductivity type of the semiconductor substrate and the impurity diffusion layer may be opposite to that described above. Furthermore, memory cells may be formed in the wells.

The impurity diffusion layer 2 functions as a source of one cell and as a drain in another adjacent cell. The film thickness of the tunnel oxide film may be 3 to 10 nm (for example, 9 nm), and the film thickness of the gate oxide film may be 5 to 30 nm (for example, 20 nm).

Next, the area of this memory cell will be described with reference to FIG.

As can be seen from FIG. 9, the dimension in the X direction of the memory cell is the sum of the length F of the region where the floating gate is located and the length F of the region where the embedded SPG is located. That is, the dimension of the X direction is 2F.

The dimension in the Y direction is the sum of the length F of the region where the floating gate and the control gate overlap each other and the length F of the isolation region between the memory cells. In other words, the Y direction dimension of the memory cell is 2F.

Therefore, the memory cell structure of the present invention can realize 4F ² which is the actual minimum memory cell area.

Hereinafter, the manufacturing method of the nonvolatile semiconductor memory device of the third embodiment will be described with reference to FIGS. 10A to 14.

First, a tunnel oxide film 4 is formed on the first conductive semiconductor substrate 1 by thermal oxidation at 600 to 1100 ° C. Next, the polysilicon layer 5a of 10 to 200 nm (for example, 50 nm), the oxide film 10 of 5 to 50 nm (for example, 20 nm) on the entire surface of the tunnel oxide film 4, 10 The nitride films 11 of ˜500 nm (for example, 200 nm) are sequentially stacked. After the resist mask 12 is formed, the nitride film 11, the polysilicon layer 5a, and the oxide film 10 are etched away (see FIG. 10 (a)).

After the tunnel oxide film 4 is etched away and the resist mask 12 is removed, an impurity diffusion layer may be further implanted, for example, by oblique ion implantation of arsenic so as to overlap with one of the polysilicon layers 5a in at least the X direction. 2a and 3a) (see FIG. 10B).

The injection conditions at this time are an acceleration voltage of 5 to 30 kev (for example, 15 kev) and an injection amount of 1 x 10 ^13-1 x 10 ¹⁶ cm ^-2 (for example, 1 x 10 ¹⁴ cm ^-2 ).

Subsequently, heat treatment is performed at 600 to 1100 ° C. (for example, 800 ° C.) to recrystallize the injection region. In this case, although a laminated film of an oxide film / nitride film is used as the insulating film on the floating gate, only the nitride film may be used.

Using the nitride film 11 as a mask, the trench 18 is formed by etching the semiconductor substrate. At this time, the impurity diffusion layer remains only in the region overlapping with the gate to become the impurity diffusion layers 2 and 3, respectively (see Fig. 11A).

The surface of the trench 18 is thermally oxidized to form a gate oxide film 6, and the polysilicon layer 7a having a degree of filling the trench 18 (e.g., 100 nm) is deposited, followed by CMP method. By this, planarization is achieved (see FIG. 11B). At the time of forming the gate oxide film 6, the sidewalls of the polysilicon layer 5a are also oxidized to form the insulating portion 6a. This insulating portion 6a serves to prevent a short circuit between the floating gate and the SPG.

Then, the polysilicon layer 7a embedded in the trench 18 is removed by etching back, at which time the level of the remaining polysilicon layer 7a is equal to the surface level of the semiconductor substrate 1. Or higher (see FIG. 12E).

Thereafter, after thermally oxidizing the surface of the SPG at 600 to 1100 ° C (for example, 800 ° C), the HDP oxide film (insulation film) 15 is deposited and the oxide film on the floating gate is removed by the CMP method or the etching back method. . At this time, the nitride film 11 becomes an etching stopper. As the oxide film removal method, wet etching can also be used in addition to the CMP method or the etching back method.

Subsequently, the nitride film 11 is removed by hot phosphoric acid or chemical dry etching, and then the oxide film 10 on the floating gate 5 is lightly immersed in an HF solution. At this time, since the insulating film 15 has a larger etching rate than the thermal oxide film or the like, the edges of the remaining insulating film 15 can be tapered (see FIG. 13A). This tapering facilitates the formation of the control gate and the floating gate in subsequent steps.

Next, the polysilicon layer 5b of 10 to 200 nm (for example, 50 nm) is deposited and patterned by the resist mask 16 (see FIG. 13B). This step is to increase the overlap area of the floating gate and the control gate. As a result, the gate capacitance coupling ratio is increased and the voltage consumption is lowered. In this embodiment, the polysilicon layer 5b is adopted for this reason, but may be omitted.

Next, the resist mask 16 is removed. Subsequently, the third insulating film and the polysilicon layer 9a made of the ONO film 8 are deposited. Then, the polysilicon layers 5a, 5b, and 9a and the ONO film 8 are successively etched to form word lines, thereby forming floating gates and control gates in self-alignment (see Fig. 14). Finally, a protective film (not shown) such as BPSG is deposited.

Through the above steps, the nonvolatile semiconductor memory device of the present invention is completed.

The writing and reading method as employed in Example 1 is also applicable to the nonvolatile semiconductor memory device of Example 3. FIG.

Example 4

By increasing the overlap area of the floating gate and the control gate, the gate capacitance coupling ratio is increased, resulting in lower voltage. Therefore, in Examples 1 to 3, the polysilicon layer 5b is laminated on the polysilicon layer 5a as shown in FIG. However, in this manufacturing method, the polysilicon layer 5b may be misaligned with respect to the polysilicon layer 5a. Therefore, photolithography below the sub rule (using a resist mask having an opening smaller than F) is adopted to obtain a cell area of 4F ² .

In Embodiment 4 of the present invention, a method of realizing a memory cell region of 4F ² without using a subrule is provided.

First, the process of Example 3 is repeated as described in FIGS. 10A to 13A.

Next, after depositing the polysilicon layer 5b and further depositing the nitride film 18 thereon, the nitride film 18 is patterned using the resist mask 19 formed without using a subrule (Fig. 15a).

Next, the resist mask 19 is removed, and the nitride film is further deposited and etched back to form the spacer 18b on the sidewall of the nitride film 18a. Due to the width of the spacer 18b, mismatching is prevented. Next, the polysilicon layer 5b is patterned using the nitride film 18a and the spacer 18b as a mask (see FIG. 15B).

Then, in the same manner as in FIG. 14, the polysilicon layer 9a is deposited and patterned to form a word line, thereby forming the polysilicon layers 5a, 5b and 9a, the nitride film 18a and the spacer 18b. ) Is continuously etched. Thus, the floating gate and the control gate are formed self-aligned.

Finally, a protective film (not shown) such as BPSG is deposited.

Through the above steps, the nonvolatile semiconductor memory device of the present invention is completed.

The writing method and the reading method employed in the first embodiment are also applicable to the nonvolatile semiconductor memory device of the fourth embodiment.

Example 5

In Embodiment 5, as in Embodiment 4, a method of realizing a memory cell region of 4F ² without using a subrule is provided.

First, the same process as in Example 3 is repeated from FIGS. 10A to 13A (see FIG. 16A).

Next, after the polysilicon layer 5b is deposited, planarization is performed by CMP until the insulating film 15 is exposed. Thus, the laminated floating gate structure can be formed self-aligning (see FIG. 16B).

Subsequently, after the ONO film 8 and the polysilicon layer 9a are deposited in the same manner as in FIG. 14, the polysilicon layers 5a, 5b and 9a and ONO are formed by patterning to form a word line. The film 8 is continuously etched. Thus, the floating gate and the control gate are formed self-aligning.

Finally, a protective film such as BPSG is deposited (not shown).

Through the above steps, the nonvolatile semiconductor memory device of the present invention is completed.

The read method and the write method employed in the first embodiment are also applicable to the nonvolatile semiconductor memory device of the fifth embodiment.

Example 6

In Examples 1 to 5, the impurity diffusion layer is provided so as to overlap only the floating gate. Increasing the resistance of the impurity diffusion layer is a factor of increasing the array noise due to the CR (return) delay and the substrate bias effect at the time of reading. Therefore, it is preferable to reduce the resistance of the impurity diffusion layer. Hereinafter, the manufacturing method of the structure which can reduce the resistance of an impurity diffused layer is demonstrated.

First, FIGS. 10A and 10B repeat the same process as in Example 3. FIG.

After the resist mask 12 is removed, a silicon oxide film is deposited and etched back using CVD to form sidewall spacers 20 on the sidewalls of the laminated structure in the channel direction. Using the polysilicon layer 5a and the sidewall spacers 20 as masks, trenches are formed in a self-aligning manner (see Fig. 17). Since the sidewall spacers 20 are formed, the widths of the impurity diffusion layers 2 and 3 become larger than those of the third embodiment. As a result, the resistance of the impurity diffusion layer is reduced.

Then, the process of Example 3 is repeated to complete the nonvolatile semiconductor memory device of the present invention in which the memory cell region of 4F ² is realized.

The writing method and reading method employed in the first embodiment are also applicable to the nonvolatile semiconductor memory device according to the sixth embodiment.

Example 7

Example 7 is a modification of Example 6 above.

First, FIG. 10A repeats the same process as Example 3. FIG.

Next, after removing the resist mask 12, ion implantation of, for example, arsenic is further performed to form an impurity diffusion layer between the floating gates. The injection conditions at this time include an acceleration voltage of 5 to 30 kev (for example, 15 kev) and an injection amount of 1 x 10 ¹³ to 1 x 10 ¹⁶ cm ^-2 (for example, 1 x 10 ¹⁴ cm ^-2 ). Thereafter, annealing is performed at 600 to 1100 ° C (for example, 800 ° C).

Next, thermal oxidation is performed at 600 to 1100 ° C. (for example, 800 ° C.) to form sidewall spacers on sidewalls of the laminated structure of the substrate in the channel direction. Then, using the laminated structure and sidewall spacers as a mask, a trench is formed self-aligning. At the same time, an impurity diffusion layer serving as a source and a drain, respectively, is formed.

Thereafter, the process of Example 3 is repeated to complete the nonvolatile semiconductor memory device of the present invention in which the memory cell region of 4F ² is realized.

The writing method and reading method employed in the first embodiment are also applicable to the nonvolatile semiconductor memory device according to the seventh embodiment.

Example 8

In Embodiment 8, there is provided a nonvolatile semiconductor memory device in which a memory cell region of 4F ² is realized, which includes an SPG formed in a trench and a floating impurity diffusion layer.

A method of manufacturing the nonvolatile semiconductor memory device of Example 8 will be described with reference to FIGS. 18A to 21B.

First, a tunnel oxide film 4 is formed on the first conductive semiconductor substrate 1 by thermal oxidation. Next, the polysilicon layer 5a of 10 to 200 nm (for example, 50 nm), the oxide film 10 of 5 to 50 nm (for example, 20 nm) and 10 to 10 nm to 200 nm (for example, 50 nm) on the entire surface of the tunnel oxide film 4. The nitride film 11 of 500 nm (for example, 200 nm) is sequentially stacked. After the resist mask 20 is formed, the nitride film 11, the polysilicon layer 5a, and the oxide film 10 are etched away (see FIG. 18 (a)).

The tunnel oxide film 4 is etched away, the resist mask 12 is removed, and then, for example, arsenic ions are implanted in a direction perpendicular to the semiconductor substrate 1 to impart impurities to the exposed surface layer of the semiconductor substrate 1. The diffusion layer 21 is formed (see FIG. 18B). The impurity diffusion layer 21 extends from the surface layer of the semiconductor substrate and is connected to the end of the tunnel oxide film 4.

In this case, the injection conditions include an acceleration voltage of 5 to 30 kev (for example, 15 kev) and an injection amount of 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ^-2 (for example, 1 × 10 ¹⁴ cm ^-2 ).

Subsequently, heat treatment is performed at 600 to 1100 ° C (for example, 800 ° C) to achieve recrystallization of the injection region. In this case, although a laminated film of an oxide film / nitride film is used as the insulating film on the floating gate, only a nitride film may be used.

The trench 18 is formed by etching the semiconductor substrate using the nitride film 11 as a mask. At this time, the impurity diffusion layer remains only in the region overlapping with the gate, and becomes the impurity diffusion layers 2 and 3 and the floating impurity diffusion layer 22 (see Fig. 19 (a)).

The surface of the trench 18 is thermally oxidized to form a gate oxide film 6. The polysilicon layer 7a is deposited to fill the trench 18 (eg 100 nm), and then planarization is performed by CMP (see FIG. 19B).

Next, the polysilicon layer 7a embedded in the trench 18 is etched back so that the level of the remaining polysilicon layer 7a is preferably equal to or higher than that of the semiconductor substrate 1. (See FIG. 20A).

Next, after thermally oxidizing the surface of SPG at 600-1100 degreeC (for example, 800 degreeC), the HDP oxide film (insulating film) 15 is deposited. The oxide film on the polysilicon layer 5a is removed by the CMP method or the etching back method. At this time, the nitride film 11 functions as an etching stripper. Instead of the CMP and the etching back, the oxide film may be removed by wet etching (see Fig. 20 (b)).

Subsequently, the nitride film 11 is removed by hot phosphoric acid or chemical dry etching, and then, the oxide film 10 on the polysilicon layer 5a is lightly immersed in an HF solution and removed. At this time, since the etching rate of the insulating film 15 is larger than that of the thermal oxide film, the edges of the remaining insulating film 15 are tapered (see Fig. 21 (a)). This tapered shape facilitates the formation of the control gate and the floating gate in subsequent steps.

Next, the polysilicon layer 5b of 10 to 200 nm (for example, 50 nm) is deposited and patterned using the resist mask 16 (see Fig. 21 (a)). By this process, the overlap area of the floating gate and the control gate can be increased. As a result, the gate capacitance coupling ratio increases and the voltage consumption decreases. This embodiment employs the polysilicon layer 5b for this reason, but may be omitted.

Then, the floating gate 5 and the control gate 9 are formed in the same manner as in FIG.

Through these steps, the nonvolatile semiconductor memory device of the present invention is completed.

The writing method and the reading method as employed in the first embodiment are also applicable to the nonvolatile semiconductor memory device of the eighth embodiment.

According to the present invention, since data rewriting is performed using FN tunnel current or CHE, a nonvolatile semiconductor memory device capable of high reliability and high speed data writing is provided. Further, in a device having a virtual grounded structure using a cell of the SPG structure, the SPG transistor is embedded in the trench so that the memory cell region can be made to have a physical minimum of 4F ² .

Claims (57)

A nonvolatile semiconductor memory device comprising at least two cells, Each cell; A floating gate formed on the semiconductor substrate via a first insulating film; A split gate formed on the conductive substrate which is spaced apart from the floating gate by a second insulating film; A control gate formed on at least a floating gate via a third insulating film; And An impurity diffusion layer formed on the surface layer of the semiconductor substrate and capacitively coupled to an end portion of the floating gate opposite to the split gate in the channel direction, Here, the floating gate and the split gate of one cell are alternately arranged along the channel direction with the floating gate and the split gate of another adjacent cell, and the impurity diffusion layer of one cell is capacitively coupled with the split gate of another adjacent cell. Nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1, wherein a split gate of one cell is formed in a self-aligning manner at a predetermined distance from the floating gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the impurity diffusion layer of one cell is capacitively coupled to the floating gate of the cell, while the cell is not capacitively coupled to the split gate of the cell. The nonvolatile semiconductor memory device according to claim 1, wherein a split gate is formed in a trench formed in a semiconductor substrate between adjacent floating gates via a second insulating film. The nonvolatile semiconductor memory device according to claim 4, wherein the impurity diffusion layer of one cell extends from the semiconductor substrate surface layer along the sidewall of the trench and is disposed adjacent to the split gate. 2. A sidewall spacer according to claim 1, wherein sidewall spacers are formed on the sidewalls of floating gates of one cell and another adjacent cell, a trench is formed between the sidewall spacers of one cell and another adjacent cell and an impurity diffusion layer is provided below each sidewall spacer. A nonvolatile semiconductor memory device formed on a surface layer of a semiconductor substrate. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of cells are formed along the channel direction, and an impurity diffusion layer of one cell functions as a drain of the cell and as a source of another adjacent cell. 2. The nonvolatile venous conductor memory device according to claim 1, wherein a plurality of cells are formed along a channel direction, and control gates of the plurality of cells are composed of a single control gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of cells are formed along the Y direction orthogonal to the channel direction, and the plurality of cells are electrically connected through a single impurity diffusion layer. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of cells are formed along a Y direction orthogonal to the channel direction, and the plurality of cells are electrically connected through a single split gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the floating impurity diffusion layer is formed in a semiconductor substrate surface layer between the split gate and the floating gate of one cell. 12. The cell of claim 11, wherein the impurity diffusion layer of one cell functions as a drain, the impurity diffusion layer of another adjacent cell functions as a source of the one cell, and the floating impurity diffusion layer of the one cell can read data from the cell. And a nonvolatile semiconductor memory device serving as an extension of the drain of the cell. 12. The method of claim 11, wherein the impurity diffusion layer of one cell functions as a drain, the impurity diffusion layer of another adjacent cell functions as a source of the one cell, and the floating impurity diffusion layer of the one cell when reading data from the cell. A nonvolatile semiconductor memory device which functions as an extension of the source of the cell. A method of reading data from a nonvolatile semiconductor memory device according to claim 1, Data reading from one cell is performed by grounding the impurity diffusion layer of one cell and applying a voltage to the impurity diffusion layer of another cell or applying a voltage to the impurity diffusion layer of the one cell and grounding the impurity diffusion layer of another adjacent cell. A method of reading data from a nonvolatile semiconductor memory, characterized in that. A method of reading data from a nonvolatile semiconductor memory device according to claim 1, Non-volatile semiconductor, characterized in that the reading of data from one cell is achieved by isolating the one cell from another adjacent cell by applying a voltage to the splitgate of that cell and not applying a voltage to the splitgate of another adjacent cell. How to read data from storage. A method of writing data into a nonvolatile semiconductor memory device according to claim 1, A method of writing data into a nonvolatile semiconductor memory device, characterized in that the data is written by using an FN tunnel current flowing between the floating gate and the impurity diffusion layer of one cell or between the floating gate and the semiconductor substrate. As a method of erasing data from a nonvolatile semiconductor memory device, After writing the data by the method of claim 16. A method for erasing data from a nonvolatile semiconductor memory device, characterized in that the data is erased using a FN tunnel current flowing between the floating gate and the impurity diffusion layer of the selected desired cell or between the floating gate and the semiconductor substrate. A method of writing data into a nonvolatile semiconductor memory device according to claim 1, Writing data into one cell causes a current to flow by applying a predetermined potential to the impurity diffusion layer of one cell, grounding the impurity diffusion layer of another cell, and applying a first current to the splitgate to face the splitgate. A method of writing data into a nonvolatile semiconductor memory device, characterized by injecting hot electrons from an end portion of a split gate with the channel region in a weakly inverted state. As a method of erasing data from a nonvolatile semiconductor memory device, 19. After writing data by the method of claim 18, the data is erased by using an FN tunnel current flowing between the floating gate and the impurity diffusion layer of the selected desired cell or between the floating gate and the semiconductor substrate. Method of erasing data from the device. A method of writing data into a nonvolatile semiconductor memory device according to claim 1, Writing data into one cell causes a current to flow by applying a predetermined potential to the impurity diffusion layer of one cell and grounding the impurity diffusion layer of another cell, and applying a second potential to the splitgate to face the splitgate. A method of writing data into a nonvolatile semiconductor memory device, characterized by injecting hot electrons from an end portion of a split gate of one cell with an area in an inverted state. As a method of erasing data from a nonvolatile semiconductor memory device, 21. After writing data by the method of claim 20, the data is erased by using an FN tunnel current flowing between the floating gate and the impurity diffusion layer of the selected desired cell or between the floating gate and the semiconductor substrate. Method of erasing data from the device. As a manufacturing method of a nonvolatile semiconductor memory device, (a1) forming at least two floating gates at a predetermined interval therebetween in the channel direction via the first insulating film to form at least two cells on the semiconductor substrate; (b1) forming two split gates on the semiconductor substrate via a second insulating film on one side of each floating gate in a channel direction; (c1) forming an impurity diffusion layer in the surface layer of the semiconductor substrate between the floating gate of one cell and the split gate of another cell so that the impurity diffusion layer is capacitively coupled with the floating gate of one cell and the split gate of another cell; step; And (d1) A method of manufacturing a nonvolatile semiconductor memory device comprising forming a control gate on each floating gate via a third insulating film. 23. The floating impurity diffusion layer of claim 22, wherein the floating impurity diffusion layer is formed on the semiconductor substrate surface layer between the floating gate and the split gate of one cell at the same time as the formation of the impurity diffusion layer in step (c1). And a capacitively coupled with the split gate. The method of claim 22, The floating gate is a laminated structure consisting of two conductive layers, Forming a first conductive layer; Depositing a layer of conductive material on at least the first conductive layer; Forming a nitride film of a desired shape on the conductive material layer and forming sidewall spacers on sidewalls of the nitride film; And And a floating gate is formed by self-aligning a second conductive layer by etching a conductive material using a nitride film and sidewall spacers as a mask. The method of claim 22, The floating gate is a laminated structure consisting of two conductive layers, Sequentially forming a first conductive material layer, an oxide film, and a nitride film, and etching the films in a desired shape using a mask to form a first conductive layer; Embedding an insulating film in a space formed in the first conductive layer, and removing the oxide film and the nitride film; And A method of manufacturing a nonvolatile semiconductor memory device, characterized in that the floating gate is formed by embedding a conductive material in a portion where an oxide film and a nitride film are removed to form a second conductive layer in a self-aligning manner. As a manufacturing method of a nonvolatile semiconductor memory device, (a2) forming at least two floating gates at a predetermined interval therebetween in the channel direction via the first insulating film to form at least two cells on the semiconductor substrate; (b2) forming an impurity diffusion layer in the semiconductor substrate surface layer on one side of each floating gate by using a floating gate as a mask or implanting impurities from an oblique direction using a mask formed on the floating gate; (c2) forming two trenches in the semiconductor substrate including a part of the impurity diffusion layer using each floating gate as a mask or using a mask formed on the floating gate; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by embedding a conductive material in the trench; And (f2) forming a control gate on each floating gate with a third insulating film interposed therebetween. 27. The method of claim 26, wherein the trench is formed self-aligning using a floating gate as a mask. 27. The method of claim 26, wherein the splitgate is formed self-aligning using the floating gate as a mask. 27. The method of claim 26, wherein step (f2) comprises removing the conductive material embedded in the trench by a predetermined thickness to provide a split gate and embedding an insulating film in the portion where the conductive material has been removed to thereby form an upper surface of the split gate. Covering the step. 27. The method of claim 26, wherein the surface level of the floating gate is approximately equal to the surface level of the insulating film on the split gate and the insulating film does not overlap with the floating gate. 27. The method of claim 26, wherein the surface level of the split gate is lower than the surface level of the semiconductor substrate. 27. The method of claim 26, wherein the floating gate is a laminated structure consisting of two conductive layers, wherein the floating gate is: Forming a first conductive layer; Depositing a conductive material on at least the first conductive layer; Forming a nitride film of a desired shape on the conductive material layer and forming sidewall spacers on sidewalls of the nitride film; And And self-aligning the second conductive layer by etching the conductive material using the nitride film and the sidewall spacer as a micro. 27. The method of claim 26, wherein the floating gate is a laminated structure consisting of two conductive layers, wherein the floating gate is: Sequentially forming a first conductive material layer, an oxide film, and a nitride film, and etching the films in a desired shape using a mask to form a first conductive layer; Embedding an insulating film in a space formed in the first conductive layer, and removing the oxide film and the nitride film; And And embedding a conductive material in a portion where the oxide film and the nitride film are removed to form a second conductive layer in a self-aligning manner. As a manufacturing method of a nonvolatile semiconductor memory device, (a2) forming at least two floating gates at a predetermined interval therebetween in the channel direction via the first insulating film to form at least two cells on the semiconductor substrate; (b2) forming an impurity diffusion layer in the semiconductor substrate surface layer on one side of each floating gate by implanting impurities from an oblique direction using a floating gate as a mask or a mask formed on the floating gate; (c2) 'forming sidewall spacers on the sidewalls of each floating gate and forming two trenches in the semiconductor substrate including a portion of the impurity diffusion layer using the floating gate and the sidewall spacers as masks; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate via a third insulating film. 35. The method of claim 34, wherein the trench is formed self-aligning using a floating gate and sidewall spacers as a mask. 36. The method of claim 35, wherein the splitgate is formed self-aligning using a floating gate and sidewall spacers as a mask. 36. The method of claim 35, wherein step (f2) comprises removing the conductive material embedded in the trench by a predetermined thickness to provide a split gate, and embedding an insulating film in the portion where the conductive material has been removed to form an upper surface of the split gate. Covering the process. 36. The method of claim 35, wherein the surface level of the floating gate is approximately equal to the surface level of the insulating film on the split gate and the insulating film does not overlap with the floating gate. 36. The method of claim 35, wherein the surface level of the split gate is lower than the surface level of the semiconductor substrate. 36. The method of claim 35 wherein The floating gate has a laminated structure consisting of two conductive layers, The floating gate is: Forming a first conductive layer; Depositing a conductive material on at least the first conductive layer; Forming a nitride film of a desired shape on the conductive material layer and forming sidewall spacers on sidewalls of the nitride film; And And self-aligning the second conductive layer by etching the conductive material using the nitride film and the sidewall spacers as a mask. 36. The method of claim 35 wherein The floating gate is a laminated structure consisting of two conductive layers, The floating gate is: Sequentially forming a first conductive material layer, an oxide film, and a nitride film, and etching the films in a desired shape using a mask to form a first conductive layer; Embedding an insulating film in a space formed in the first conductive layer, and removing the oxide film and the nitride film; And And embedding a conductive material in a portion where the oxide film and the nitride film are removed to form a second conductive layer in a self-aligning manner. A method of manufacturing a nonvolatile semiconductor memory device, (a2) forming at least two floating gates at a predetermined interval therebetween in the channel direction via the first insulating film to form at least two cells on the semiconductor substrate; (b2) implanting and annealing at least the region between the floating gates using a floating gate as a mask or a mask formed on the floating gate; (c2) ″ forming a sidewall spacer on the sidewall of each floating gate, and forming two trenches using the floating gate and the sidewall spacer as a mask, thereby forming a floating impurity diffusion layer in the semiconductor substrate surface layer below each sidewall spacer. And providing an impurity diffusion layer; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate via a third insulating film. 43. The method of claim 42, wherein the trenches are formed self-aligning using floating gates and sidewall spacers as masks. 43. The method of claim 42 wherein the splitgate is formed self-aligning using a floating gate and sidewall spacers as a mask. 43. The method of claim 42, wherein step (f2) comprises removing the conductive material embedded in the trench by a predetermined thickness to provide a split gate, and embedding an insulating film in the portion where the conductive material has been removed, thereby removing the upper surface of the split gate. Covering the step. 43. The method of claim 42 wherein the surface level of the floating gate is approximately equal to the surface level of the insulating film on the split gate and wherein the insulating film does not overlap with the floating gate. 43. The method of claim 42, wherein the surface level of the split gate is lower than the surface level of the semiconductor substrate. 43. The method of claim 42, wherein the floating gate is a laminated structure consisting of two conductive layers, wherein the floating gate is: Forming a first conductive layer; Depositing a conductive material on at least the first conductive layer; Forming a nitride film of a desired shape on the conductive material layer and forming sidewall spacers on sidewalls of the nitride film; And And self-aligning the second conductive layer by etching the conductive material using the nitride film and the sidewall spacers as a mask. 43. The method of claim 42, wherein the floating gate is a laminated structure consisting of two conductive layers, wherein the floating gate is: Sequentially forming a first conductive material layer, an oxide film, and a nitride film, and etching them into a desired shape using a mask to form a first conductive layer; Embedding an insulating film in a space formed in the first conductive layer, and removing the oxide film and the nitride film; And And embedding a conductive material in a portion from which the oxide film and the nitride film are removed to form a second conductive layer in a self-aligning manner. As a manufacturing method of a nonvolatile semiconductor memory device, (a2) forming at least two floating gates at a predetermined interval therebetween in the channel direction via the first insulating film to form at least two cells on the semiconductor substrate; (b2) implanting and annealing at least the regions between the floating gates using a floating gate as a mask or a mask formed on the floating gate; (c2) '' 'forming a trench between at least the floating gate, thereby providing a floating impurity diffusion layer and an impurity diffusion layer, respectively, below the end of the floating gate extending along the side of the trench; (d2) forming a second insulating film on the side and bottom of the trench; (e2) forming two split gates by filling the trench with a conductive material; And (f2) forming a control gate on each floating gate via a third insulating film. 51. The method of claim 50, wherein the trench is formed self-aligning using a floating gate as a mask. 51. The method of claim 50, wherein the splitgate is formed self-aligning using the floating gate as a mask. 51. The method of claim 50, wherein step (f2) comprises removing the conductive material embedded in the trench by a predetermined thickness to provide a split gate, and embedding an insulating film in the portion where the conductive material has been removed to cover the upper surface of the split gate. Covering the step. 51. The method of claim 50, wherein the surface level of the floating gate is approximately equal to the surface level of the insulating film on the split gate and the insulating film does not overlap with the floating gate. 51. The method of claim 50, wherein the surface level of the split gate is lower than the surface level of the semiconductor substrate. 51. The method of claim 50, wherein the floating gate is a stacked structure consisting of two conductive layers, wherein the floating gate is: Forming a first conductive layer; Depositing a conductive material on at least the first conductive layer; Forming a nitride film of a desired shape on the conductive material layer and forming sidewall spacers on sidewalls of the nitride film; And And self-aligning the second conductive layer by etching the conductive material using the nitride film and the sidewall spacers as a mask. 51. The method of claim 50, wherein the floating gate is a stacked structure consisting of two conductive layers, wherein the floating gate is: Sequentially forming a first conductive material layer, an oxide film, and a nitride film, and etching them into a desired shape using a mask to form a first conductive layer; Embedding an insulating film in a space formed in the first conductive layer, and removing the oxide film and the nitride film; And And embedding a conductive material in a portion from which the oxide film and the nitride film are removed to form a second conductive layer in a self-aligning manner.