JP2010129990A - Nonvolatile semiconductor storage element, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage element which has a simple structure, is reducible in element size and suitable to high integration, and hardly has a defect. <P>SOLUTION: The nonvolatile semiconductor storage element 10 stores data of one bit or multiple bits, and includes: a source region 12 and a drain region 13 arranged across a channel region 14; gate insulating films 15 and 18; a plurality of floating gate electrodes 16 and 17 buried in a protective insulating film 20, arranged side by side on the channel region 14, and opposed to neither the source region 12 nor the drain region 13; and a control gate 19 arranged on the gate insulating films 15 and 18 opposite the channel region 14. The floating gate electrodes 16 and 17 are physically or electrically as large as or larger than the channel width. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electrically writable / erasable nonvolatile semiconductor memory element such as a flash memory and an EEPROM, and a manufacturing method thereof.

  As a nonvolatile semiconductor memory element, an EEPROM, a flash memory, and the like having a floating gate insulated from others are known. In these semiconductor memory elements, the threshold value changes in accordance with the amount of charge accumulated in the floating gate, and data is stored by the change in the threshold value.

  The injection of the charge of the floating gate and the extraction of the charge from the floating gate are performed through a thin tunnel insulating film.

  In the conventional semiconductor memory element, the tunnel insulating film may be deteriorated due to initial defects, aging deterioration, or the like, and it may be difficult to accumulate charges in the floating gate.

In order to solve this problem, Patent Document 1 discloses a nonvolatile semiconductor element including two floating gates.
In this nonvolatile semiconductor element, even if the charge stored in one floating gate is lost, the stored data can be held by the charge stored in the other floating gate.

Japanese Patent No. 3264365

  In the configuration disclosed in Patent Document 1, two floating gates arranged side by side in the channel length direction are routed to the impurity diffusion region connected to the source / drain region, and the impurity diffusion is performed through the thin tunnel oxide film. Opposite the area. For this reason, the structure of the element is complicated, which affects the manufacturing yield. In addition, since the entire area of the device becomes large, it is not suitable for high integration. In addition, the ratio of hot electrons to electrons injected into the floating gate is high, and the tunnel insulating film is greatly deteriorated by the electron injection, so that element defects are likely to occur.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory element that has a simple structure, can be reduced in overall size, and is less prone to defects.

In order to achieve such an object, the nonvolatile semiconductor memory element of the present invention includes:
A source region and a drain region disposed through the channel region;
A first gate insulating film formed to cover at least the channel region;
A plurality of floating gate electrodes formed on the first gate insulating film so as to face the channel region and be insulated from each other, avoiding the source region and the drain region;
A second gate insulating film that is formed on the plurality of floating gate electrodes and insulates the plurality of floating gate electrodes from each other and from the other together with the first gate insulating film;
A gate electrode disposed on the second gate insulating film so as to face the channel region;
Is provided.

  For example, each of the plurality of floating gate electrodes is formed over the entire channel width, either physically or electrically equal to or wider than the channel width.

  For example, the plurality of floating gate electrodes are arranged at the same level on the channel, and the surface of the first gate insulating film is formed flat.

  For example, storage control means for injecting electrons from the channel region into the plurality of floating gate electrodes and extracting the injected electrons to align the accumulation state of electrons in the plurality of floating gate electrodes may be further arranged.

In addition, a method for manufacturing a nonvolatile semiconductor memory element of the present invention includes
Forming a first gate insulating film on the source region, the channel region, and the drain region;
Forming a conductor layer or a semiconductor layer on the first gate insulating film;
Patterning the conductor layer or the semiconductor layer to form a plurality of floating gate electrodes arranged at the same layer level, respectively facing the channel region and avoiding the source region and the drain region; ,
Forming a second gate insulating film covering each of the plurality of floating gate electrodes;
Forming a gate electrode opposite to the channel region on the second gate insulating film;
It is characterized by providing.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory element that has a simple configuration, can be highly integrated with a small size, and is less prone to defects.

A nonvolatile semiconductor memory element 10 according to an embodiment of the present invention will be described below with reference to FIG.
Here, FIG. 1A is a cross-sectional view of the nonvolatile semiconductor memory element 10, and FIG. 1B is a plan layout view of the main part of the nonvolatile semiconductor memory element 10.
As shown in the figure, the nonvolatile semiconductor memory element 10 of the present embodiment is a nonvolatile semiconductor memory element that stores data of 1 bit, and includes a semiconductor substrate 11, a source region 12, a drain region 13, a channel A region 14, a first gate insulating film 15, first and second floating gate electrodes 16 and 17, a second gate insulating film 18, a control gate 19, and a protective insulating film 20 are provided.

  The semiconductor substrate 11 includes, for example, a P-type silicon single crystal substrate, a P-type well region formed in the N-type single crystal substrate, a P-type epitaxial layer formed on the N-type silicon single crystal substrate, and the like. Is done.

The source region 12 is formed in the surface region of the semiconductor substrate 11 by diffusing N-type impurities, for example, in a rectangular shape.
The drain region 13 is an N-type region formed on the surface region of the semiconductor substrate 11 so as to face the source region 12.

  The channel region 14 is composed of a P-type region between the N-type source region 12 and the N-type drain region 13. The channel region 14 has a length (channel length) of, for example, 1 nm to 200 μm, and the channel region 14 has a width (channel width) of 1 nm to 100 μm.

  The source region 12, the drain region 13, and the channel region 14 are isolated from each other by LOCOS (LOCal Oxidation of Silicon).

  The first gate insulating film 15 functions as a tunnel insulating film, is made of an insulator such as a silicon oxide film or a silicon nitride film, and is disposed on the semiconductor substrate 11. The first gate insulating film 15 has a substantially uniform thickness and a flat surface of about 2 to 5 nm, for example.

  The first and second floating gate electrodes 16 and 17 are made of polysilicon or the like, and are arranged side by side in the channel length direction (source-drain direction) so as to face the channel region 14. Controlled to the accumulation state (accumulation or non-accumulation of electrons). The first and second floating gate electrodes 16 and 17 are each formed to be equal to or wider than the channel width (that is, across the entire width direction of the channel region 14). The first and second floating gate electrodes 16 and 17 are not only physically formed wider than the channel width, but are physically equal to or narrower than the channel width. The electric field (lines of electric force) from the two floating gate electrodes 16 and 17 may be formed so as to be wider than the channel width. That is, it may be electrically formed wider than the channel width.

  The first floating gate electrode 16 and the second floating gate electrode 17 are located at the same layer level and do not extend on the source region 12 and the drain region 13. That is, a gap ΔL1 is arranged between the edge of the source region 12 and the first floating gate electrode 16, and a gap ΔL2 is arranged between the edge of the drain region 13 and the second floating gate electrode 17. Yes.

  The second gate insulating film 18 is formed on the first gate insulating film 15 with a thickness of about 18 nm so as to cover the first and second floating gate electrodes 16 and 17. The floating gate electrodes 16 and 17 are insulated from each other and from other members.

  The control gate 19 is made of polysilicon or the like, and is formed on the second gate insulating film 18 so as to face the channel region 14 and cover the first and second floating gate electrodes 16 and 17. Yes.

  The protective insulating film 20 covers and protects the whole.

  Next, an operation of writing data “0” in the nonvolatile semiconductor memory element 10 having the above-described configuration, that is, injecting electrons into the first and second floating gate electrodes 16 and 17 will be described.

  First, as shown in FIG. 2, a positive voltage V (VW >> V) is applied to the drain region 13 while a high voltage VW for writing, for example, 4 (2 to 5) V is applied to the control gate 19. For example, 1 V is applied, and a reference voltage Vr (VW >> V >> Vr), for example, a ground voltage is applied to the source region 12.

Thereby, electrons flow in the channel region 14 from the source region 12 toward the drain region 13.
Further, due to the high voltage VW applied to the control gate 19, a part of the electrons (tunnel current) flowing through the channel region 14 pass through the first gate insulating film 15 due to the tunnel effect. The first and second floating gate electrodes 16 and 17 are both injected with electrons.

  Next, when data stored in the nonvolatile semiconductor memory element 10 is erased, that is, when the charges injected into the first and second floating gate electrodes 16 and 17 are extracted, as shown in FIG. An erase voltage VE (VW> 0> VE), for example, −2 to −3 V, is applied to the gate 19, and a ground voltage is applied to the source region 12 and the drain region 13. As a result, a tunnel current flows between the first and second floating gate electrodes 16 and 17 and the channel region 14 via the first gate insulating film 15, and the first and second floating gate electrodes 16 and 17. The electrons (negative charges) accumulated in the first and second floating gate electrodes 16 and 17 are both released.

  Next, when reading data stored in the nonvolatile semiconductor memory element 10, as shown in FIG. 4, a read voltage VR (VW> VR> VE) is applied to the control gate 19, and a ground voltage, A positive voltage V is applied to the drain region 13.

  Then, when electrons (negative charges) are accumulated in the first and second floating gate electrodes 16 and 17, an N-type channel is difficult to be generated, and the electron flow from the source region 12 to the drain region 13 is relatively Become smaller. Conversely, when negative charges are not accumulated in the first and second floating gate electrodes 16 and 17, the electron flow from the source region 12 to the drain region 13 is relatively large. For this reason, it is possible to determine whether the data stored in the memory cell is “1” or “0” from the difference in magnitude of the electron current, that is, the difference in current.

This point will be described more specifically.
When the applied voltage Vg of the control gate 19 is 0 (grounded) between the state where electrons are injected into the first and second floating gate electrodes 16 and 17 and the state where electrons are not injected, a predetermined positive polarity 5A to 5D show potential distributions in the channel direction when the voltage V is V. A ground voltage is applied to both the source region 12 and the drain region 13.

  As shown in FIGS. 5A and 5C, when Vg = 0 v is applied to the control gate 19, the potential barrier is high, and a voltage V is applied between the source region 12 and the drain region 13. However, no current flows in the channel region 14.

  On the other hand, as shown in FIGS. 5B and 5D, in the state where Vg = VR (positive voltage) is applied to the control gate 19, the potential barrier is lowered, and the source region 12 and the drain region 13 A current flows through the channel region 14 in accordance with the voltage V applied therebetween.

  However, the height of the potential barrier varies greatly depending on whether electrons are accumulated in the first and second floating gate electrodes 16 and 17, and the current flowing through the channel region 14 from the drain region 13 toward the source region 12. The amount of Based on this current difference, it can be determined that the current is small as “0” (with accumulation of electrons) and the current is large as “1” (without accumulation of electrons).

  Here, it is assumed that there is a defect in the first gate insulating film 15 and the accumulated charge in the first floating gate electrode 16 leaks out. However, it is assumed that there is no leakage or the like in the accumulated charge of the second floating gate electrode 17. In this case, the potential of the channel region is as shown in FIGS. 5E and 5F, and the erasure shown in FIGS. 5C and 5D is present in the portion where the first floating gate electrode 16 exists. In the portion where the potential distribution similar to that of the nonvolatile semiconductor memory element 10 in the state exists and the second floating gate electrode 17 exists, the nonvolatile semiconductor memory element in the memory state shown in FIGS. A potential distribution similar to 10 exists. That is, a potential barrier similar to that in the normal state exists in the channel region 14 between the source region 12 and the drain region 13. For this reason, in the channel region between the source region 12 and the drain region 13, current is less likely to flow than when no charge is accumulated in the first and second floating gate electrodes 16 and 17. Therefore, it can be determined that negative charges are injected into the first and second floating gates 16 and 17, that is, the stored data is “0”.

  Therefore, the nonvolatile semiconductor memory element 10 can retain stored data even if one accumulated charge of the two floating gate electrodes 16 and 17 leaks due to dielectric breakdown or the like.

  Further, unlike the configuration described in Patent Document 1, the element structure is simple, and element miniaturization and high yield are possible. Further, since the first and second floating gate electrodes 16 and 17 are not overlapped with the source region 12 and the drain region 13, the first and second floating gate electrodes 16 and 17 and the first gate insulating film 15 are formed on the first and second floating gate electrodes 16 and 17. The proportion of hot electrons in the injected electrons decreases. Therefore, it is possible to reduce the incidence of defects due to hot electrons.

Next, a method for manufacturing the nonvolatile semiconductor memory element 10 having the above configuration will be described.
First, the source region 12 and the drain region 13 are formed in the semiconductor substrate 11 by ion implantation or the like.

Next, a LOCOS insulating film that partitions the source region 12, the drain region 13, and the channel region 14 is formed by selective oxidation or the like.
Next, as shown in FIG. 6A, an insulating film such as a silicon oxide film having a uniform film thickness of about 2 to 5 nm is formed by thermal oxidation or the like. This film becomes the first gate insulating film 15.

  Next, as shown in FIG. 6B, a semiconductor film or conductor made of a metal such as polycrystalline silicon, amorphous silicon, or aluminum is formed on the first gate insulating film 15 by CVD, vapor deposition, or the like. A film 101 is formed.

  As shown in FIG. 6C, the semiconductor film or conductor film 101 is patterned into a shape that is located on the channel region 14 and does not overlap with the source region 12 and the drain region 13. The floating gate electrodes 16 and 17 are formed.

  Next, as shown in FIG. 7A, an insulating film such as a silicon oxide film having a thickness of about 15 to 20 nm is formed on the entire surface by CVD or the like. This insulating film becomes the second gate insulating film 18.

  Next, as shown in FIG. 7B, a conductor film 102 made of a metal such as polycrystalline silicon, amorphous silicon, or aluminum is formed on the second gate insulating film 18 by CVD, vapor deposition, or the like. Form.

The conductor film 102 is patterned to form a control gate 19 that faces the channel region 14.
Subsequently, an insulating film is formed to form a protective film.

An example of the configuration of a nonvolatile semiconductor memory device 100 using the nonvolatile semiconductor memory element 10 is shown in FIG.
As illustrated, the nonvolatile semiconductor memory elements 10 are arranged in a matrix of m rows × n columns.
Word lines WL (WL1 to WLm) are connected to the control gates of the nonvolatile semiconductor memory elements 10 in the same row.
Bit lines BL (BL1 to BLn) are connected to the drains of the nonvolatile semiconductor memory elements 10 in the same column.

Voltage setting lines SL (SL1 to SLm) are connected to the sources of the nonvolatile semiconductor memory elements 10 in the same row.
Each voltage setting line SL (SL1 to SLm) is connected to voltage setting circuits SV1 to SVm.
Each bit line BL (BL1 to BLn) is connected to a corresponding sense amplifier SA1 to SAn via a transfer gate TG (TG1 to TGn).
Further, each bit line BL (BL1 to BLn) is connected to the write circuit WC via the write gate WG (WG1 to WGn).

An operation of the nonvolatile semiconductor memory device 100 configured as described above will be described.
First, in the normal state, the write enable signal WE is at a low level, and the write gates WG1 to WGn are all turned off. The write circuit WC is also turned off. The voltage setting circuits SV1 to SVm set all the voltage setting lines SL1 to SLm to a low level (ground level). As a result, the source region 12 of the nonvolatile semiconductor memory element 10 is at the ground level.

Write Operation The word line WL of the write target row is set to the write voltage VW, and the write gate voltage Vg = VW is applied to the control gate 19 of the nonvolatile semiconductor memory element 10 of the corresponding row.
The write enable signal WE is set to the high level, and all the write transfer gates TG are turned on. The transfer gate TG connected to the bit line BL connected to the nonvolatile semiconductor memory element 10 in which “0” is written is selectively turned on. The write circuit WC sets the output voltage to a positive voltage V.
The output of the voltage setting circuit SV of the row to be written is set to the ground level, and the others are opened. The source region 12 of the nonvolatile semiconductor memory element 10 in the write target row is set to the ground level, and the others are set to the open state. As a result, the voltage shown in FIG. 2 is set in the nonvolatile semiconductor memory element 10 to which “0” is written, and electrons are injected into the first and second floating gate electrodes 16 and 17.

Erase Operation The word line WL of the row of the nonvolatile semiconductor memory element 10 to be erased is set to a negative (minus) voltage, and the gate voltage Vg <for erasing is applied to the control gate 19 of the nonvolatile semiconductor memory element 10 of the corresponding row. Apply 0.
The write enable signal WE is set to the high level, and all the write transfer gates TG are turned on. The transfer gate TG connected to the bit line BL connected to the non-volatile semiconductor memory element 10 to be erased (write “1”) is selectively turned on (all transfer gates TG may be turned on). . The write circuit WC and the voltage setting circuit set the output voltage to the level V +.
The output voltage of the voltage setting circuit SV in the row to be erased is set to V +, and the others are set to the ground level.
As a result, the voltage shown in FIG. 3 is set in the nonvolatile semiconductor memory element 10 to which “1” is written, and electrons are extracted from the first and second floating gate electrodes 16 and 17.

Data read operation When data is read, the selection voltage Vg = VR is applied to the word line WL connected to the nonvolatile semiconductor memory element 10 to be read, and the non-selection voltage Vg = 0 is applied to the other word lines. To do.
Further, the voltage setting circuit SV provided in the row of the nonvolatile semiconductor memory element 10 to be read applies a ground voltage to the corresponding voltage setting line SL, and the source region of the nonvolatile semiconductor memory element 10 in the corresponding row. Drop 12 to the ground. For example, the other voltage setting circuit SV opens the voltage setting line SL.
Further, a high level read signal Y is supplied to the transfer gate TG connected to the bit line BL connected to the nonvolatile semiconductor memory element 10 to be read, and the corresponding transfer gate TG is turned on.
The sense amplifiers SA1 to SAn set the bit lines BL1 to BLn to a predetermined voltage. Each of the sense amplifiers SA1 to SAn measures a current flowing through the bit lines BL1 to BLn, that is, a channel current flowing through the corresponding nonvolatile semiconductor memory element 10, and discriminates stored data.

As described above, according to this embodiment, the element structure of each nonvolatile semiconductor memory element 10 has a simple configuration, which can be easily manufactured and miniaturized, and can increase the yield.
In addition, the nonvolatile semiconductor memory element 10 can be integrated on a large scale to form a nonvolatile semiconductor memory device.

  Note that the configurations, operations, numerical values, and the like in the above embodiments are examples, and the present invention is not limited to these.

  For example, although the source region 12 and the drain region 13 and the channel region 14 have the same width, the channel region 14 may be formed narrower than the source region 12 and the drain region 13 as shown in FIG. Also in this case, the first and second floating gate electrodes 16 and 17 are desirably formed so as to physically or electrically cover the entire width direction of the channel.

  In addition, when the source region 12 and / or the drain region 13 includes an impurity diffusion region between the channel region 14, the first and second floating gate electrodes 16 and 17 do not overlap the impurity diffusion region. Is desirable.

  In the above embodiment, the source region 12, the drain region 13, and the channel region 14 are formed in the semiconductor substrate 11. For example, as shown in FIG. The region 13, the channel region 14 and the like may be disposed. That is, an SOI structure may be adopted.

  Furthermore, the number of floating gate electrodes is arbitrary as long as it is two or more. For example, as shown in FIG. 10, three floating gate electrodes 16, 17, 31 may be arranged.

  In the above description, an example in which 1-bit data is stored in one memory cell has been described. The present invention is not limited to this, and a plurality of bits of data may be stored in one nonvolatile semiconductor memory element 10. In this case, for example, at the time of writing, a voltage VW having a magnitude corresponding to the value of the data to be written is applied to the control gate 19 and an amount corresponding to the writing data is applied to the first and second floating gate electrodes 16 and 17. Inject electrons. The amount of electrons injected into the first and second floating gate electrodes 16 and 17 may be controlled by controlling the time during which the write voltage VW is applied to the control gate 19. On the other hand, at the time of reading, a predetermined voltage V is applied between the source region 12 and the drain region 13, and a reading voltage VR is applied to the control gate 19. At this time, the amount of current flowing through the channel region 14 changes according to the amount of electrons injected into the first and second floating gate electrodes 16 and 17. Therefore, the current flowing through the channel region 14 is measured, and the measured current amount is converted into data.

  The present invention can be applied to a nonvolatile semiconductor element that can be electrically written, read, erased, such as a flash memory and an EEPROM.

It is a figure for demonstrating the structure of the non-volatile semiconductor element which concerns on one Embodiment of this invention, (a) is sectional drawing, (b) is a plane arrangement | positioning figure of the principal part. FIG. 2 is a diagram for explaining a write operation to the nonvolatile semiconductor element shown in FIG. 1. FIG. 2 is a diagram for explaining an erase operation of the nonvolatile semiconductor element shown in FIG. 1. FIG. 2 is a diagram for explaining a read operation of the nonvolatile semiconductor element shown in FIG. 1. FIG. 2A is a diagram showing a potential distribution on a channel region of the memory cell shown in FIG. 1, wherein FIG. 1A shows a potential distribution when electrons are injected into the floating gate electrodes 16 and 17 and a ground voltage is applied to the control gate. (B) shows the potential distribution when electrons are injected into the floating gate electrodes 16 and 17 and the read voltage V is applied to the control gate, and (c) shows the electrons injected into the floating gate electrodes 16 and 17. The potential distribution when the ground voltage is applied to the control gate, (d) is the potential distribution when the electrons are not injected into the floating gate electrodes 16 and 17 and the read voltage V is applied to the control gate. , (E), electrons are not injected into the floating gate electrode 16, but electrons are injected into the floating gate electrode 17. The potential distribution when a ground voltage is applied to the roll gate, (f) shows that no electrons are injected into the floating gate electrode 16, electrons are injected into the floating gate electrode 17, and the read voltage V is applied to the control gate. The potential distribution when applied. (A)-(c) is sectional drawing for demonstrating the manufacturing process of a non-volatile semiconductor memory device. (A)-(c) is sectional drawing for demonstrating the manufacturing process of a non-volatile semiconductor memory device. It is a figure which shows the structural example of the non-volatile semiconductor memory device using the non-volatile semiconductor memory element shown in FIG. It is a top view which shows the other structure of a non-volatile semiconductor memory element. It is sectional drawing which shows the other structure of a non-volatile semiconductor memory element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Nonvolatile semiconductor memory element 11 Semiconductor base body 12 Source region 13 Drain region 14 Channel region 15 1st gate insulating film 16 1st floating gate electrode 17 2nd floating gate electrode 18 2nd gate insulating film 19 Control gate 20 Protective insulating film 32 Insulator 100 Nonvolatile semiconductor memory device 101 Semiconductor film or conductor film 102 Conductor film

Claims (5)

A source region and a drain region disposed through the channel region;
A first gate insulating film formed to cover at least the channel region;
A plurality of floating gate electrodes formed on the first gate insulating film so as to face the channel region and be insulated from each other, avoiding the source region and the drain region;
A second gate insulating film that is formed on the plurality of floating gate electrodes and insulates the plurality of floating gate electrodes from each other and from the other together with the first gate insulating film;
A gate electrode disposed on the second gate insulating film so as to face the channel region;
A nonvolatile semiconductor memory element. Each of the plurality of floating gate electrodes is physically or electrically equal to or wider than the width of the channel region, and is formed over the entire channel width.
The nonvolatile semiconductor memory element according to claim 1. The plurality of floating gate electrodes are arranged at the same level on the channel,
The surface of the first gate insulating film is formed flat.
The nonvolatile semiconductor memory element according to claim 1 or 2.   The apparatus further comprises storage control means for injecting electrons into the plurality of floating gate electrodes from the channel region and extracting the injected electrons to align the accumulation state of electrons in the plurality of floating gate electrodes. The nonvolatile semiconductor memory element according to any one of 1 to 3. Forming a first gate insulating film on the source region, the channel region, and the drain region;
Forming a conductor layer or a semiconductor layer on the first gate insulating film;
Patterning the conductor layer or the semiconductor layer to form a plurality of floating gate electrodes arranged at the same layer level, respectively facing the channel region and avoiding the source region and the drain region; ,
Forming a second gate insulating film covering each of the plurality of floating gate electrodes;
Forming a gate electrode opposite to the channel region on the second gate insulating film;
A method for manufacturing a nonvolatile semiconductor memory element.

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