JPH08181204A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To form a contact hole easily by a self-alignment method by using a substrate containing a group IVa element as an insulating layer on the insulating layer formed on a side face on at least a wiring. CONSTITUTION: An insulating layer 14 consisting of silicon dioxide containing a group IVa element such as Ge or silicon nitride is formed on insulating layers 3, 5, 6b covering wiring layers 4a, 4b formed on a semiconductor substrate 1. Accordingly, even when a contact hole is made in a narrow region in an extremely small manufacture margin by a self-alignment method. etching is not conducted through to the wiring layers 4a, 4b and the formation of a contact at a place near the wiring layers 4a, 4b can be inhibited by forming the insulating layer 14 having excellent etching resistance, thus acquiring a device having high accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a semiconductor device and a method of manufacturing the same that facilitates formation of contact holes by a self-alignment method.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated and elements have been miniaturized, resulting in misalignment in the photolithography process and difficulty in miniaturizing contacts for connecting wirings and active regions of a semiconductor substrate. It is said that. Therefore, in a conventional semiconductor device, a wiring layer such as a word line formed on a semiconductor substrate surrounds the periphery of the wiring layer so that it does not come into contact with a conductive substance such as another wiring layer and is electrically separated. As described above, a silicon dioxide layer or a silicon nitride film is formed as an insulating layer to serve as an etching protection film.
At this time, as described above, since the design margin is reduced due to the high integration of the semiconductor device, when the contact hole is formed so as to be in contact with the active region between the wiring layers, it is formed around the wiring layer. A contact hole forming method using a self-alignment technique is used in which a contact is formed in an active region that is narrower than the actual size of the contact hole by using the pattern (sidewall, etc.) that is provided. When forming the above contact holes, the side wall, which is an insulating layer formed on the side surface of the wiring layer (word line), serves as an etching protection film that protects the wiring layer so that the wiring layer is not etched. I was doing

Next, FIG. 25 shows a sectional view of a structure of a semiconductor device using a conventional technique. In the figure, the semiconductor substrate 1,
The LOCOS isolation region 2 formed on the semiconductor substrate 1, the gate insulating layer 3 formed on one main surface of the semiconductor substrate 1, the word line 4a which is a wiring layer formed on the gate insulating layer 3, and the gate electrode. Word line 4b, LOCOS above
Adhesion to the word lines 4a and 4b formed on the isolation region 2, the insulating layer 5 formed to adhere to the word lines 4a and 4b, the word lines 4a and 4b, the gate insulating layer 3 and the insulating layer 5, respectively. The side wall 6b made of an insulating material, the insulating layer 10 formed on the entire surface so as to cover the above components, and the insulating layer 1 formed on the insulating layer 10.
1, the upper surface of which is further provided with an insulating layer 12 whose upper surface is approximately flattened, and the word line 4a,
An upper portion of the semiconductor substrate 1 between 4b shows a source / drain region 9 composed of a low concentration impurity region 7 and a high concentration impurity region 8.

In the source / drain region 9 of the semiconductor device configured as described above, it is necessary to form a contact hole at the time of forming a contact between the source / drain region 9 and a bit line or the like. When the contact holes are formed by the method, if the insulating layers 3, 5, 6b covering the wiring layers (word lines) 4a, 4b are partially removed due to the misalignment, the wiring layers and the wiring layers are formed in the contact holes. If the contact formed in close contact is brought into conduction, or the potential of the conductive material formed in the contact and the wiring layer are close to each other, a change in electric potential may hinder the operation of the semiconductor device. It was becoming.

Next, sectional views of steps in forming a contact hole by the self-alignment method are shown. FIG. 26
In the figure, reference numeral 13 is a resist pattern formed through a photoengraving process, and the same reference numerals as those used in FIG. 25 indicate the same or corresponding portions. The resist pattern 13 in FIG. 27 is not formed on the source / drain regions 9, and the resist pattern 1
Formed as an etching mask for forming a contact hole in a portion not covered with 3.
By using this as an etching mask, anisotropic etching is performed to form contact holes reaching the source / drain regions 9.

However, when the resist pattern 13 serving as an etching mask at the time of forming this contact hole is accurately formed, it has a groove having a width as shown by symbol A in FIG. Actually, assuming that a misalignment occurs in the photoengraving process, resulting in a pattern having a groove having a width as shown by symbol B, anisotropic etching is performed using this resist pattern 13 as an etching mask. Consider the etching situation.
In this case, first, anisotropic etching proceeds to a state as shown in FIG. 27, the insulating layer 11 surrounding the wiring layer is partially removed at a point C in the figure, and an insulating layer formed below the insulating layer 11 is removed. 10 is exposed. The point C is inclined, and the sputtering of ions is larger than that in the flat portion, so that the state described above is obtained. From this, further etching was performed until one main surface of the semiconductor substrate 1 was exposed, and as shown in FIG. 28, a contact hole having a portion such as point D in the figure, which was very close to the word line 4b, was formed. It becomes a state. In this case, still word line 4
Since it is not deeply etched until reaching b, even if a conductive material is buried inside the contact hole in a later process, the word line 4b and the source / source line forming the gate electrode are formed.
Although the contact in contact with the drain region 9 does not make direct electrical contact, it is undeniable that the two conductive materials are in close proximity to each other and thus have an electrical influence on each other. Further, when the misalignment of the resist pattern serving as the etching mask is further large, contact hole etching proceeds to the wiring layer (word line) 4b, and when a conductive material is buried in this contact hole, direct electrical contact occurs. This increases the possibility that a malfunction of the device will occur.

[0007]

Since the conventional semiconductor device is configured as described above, when contact hole etching is performed by anisotropic etching using RIE by the self-alignment method, ion sputtering occurs at the inclined portion. Since the insulating film formed as the etching stopper film is more easily etched than the flat part, the insulating layer formed so as to surround the periphery of the wiring layer is also etched, and the effect as the etching stopper There was a problem that I could hardly expect.

The present invention has been made in order to solve the above problems, and it is an object of the present invention to facilitate the formation of contact holes by the self-alignment method and to obtain a semiconductor device which operates reliably. The purpose is to obtain a manufacturing method suitable for this device.

In the case of etching by sputtering,
The sputter rate depends on the mass of the film to be etched and its surface binding energy. Therefore, the source / drain region 9
The upper part of the wiring layer protective film such as the sidewall is etched by changing the mass and the binding energy of the film from silicon dioxide, which is a general insulating material. It is considered to be effective in forming a difficult etching protection film.

[0010]

A semiconductor device according to claim 1 of the present invention uses a substance containing a group IVa element as an insulating layer on at least an insulating layer formed on a side surface of a wiring layer.

Further, in the semiconductor device according to claim 2 of the present invention, IVa is formed on the wiring layer and on the insulating layer formed on the side surface.
Silicon dioxide containing a group element or a silicon nitride film is used as an insulating layer.

According to a third aspect of the present invention, in the semiconductor device, silicon dioxide containing a group IVa element or a silicon nitride film is used as an insulating layer, and is formed as a sidewall at a position in contact with an upper portion and a side surface portion of the wiring layer. To do.

Further, in the method of manufacturing a semiconductor device according to a fifth aspect of the present invention, the step of further forming an insulating layer containing a group IVa element on an insulating layer such as a sidewall formed on the wiring layer and the side surface. Is included.

A semiconductor device manufacturing method according to a sixth aspect of the present invention includes a step of forming an insulating layer containing a group IVa element as a sidewall on the wiring layer and on the side surface.

[0015]

The semiconductor device according to the present invention functions as an etching protection film for the wiring layer by forming the insulating layer containing the group IVa element formed so as to cover the wiring layer and the side surface, and At least the insulating layer containing the group IVa element formed on the upper portion of the inclined portion of the sidewall is a film having a thickness in the vertical direction.
It is a stronger etching protection layer.

Further, in the semiconductor device of the present invention, since the silicon dioxide film containing the group IVa element or the silicon nitride film is formed on the wiring layer and on the insulating layer formed on the side surface, the semiconductor device serves as an etching protection film for the wiring layer. Insulating layers that function, and in particular, the insulating layer containing the group IVa element formed in the inclined portion of the sidewall is an insulating layer having a thickness in the vertical direction. Has become.

Further, in the semiconductor device of the present invention, since the insulating layer on the upper portion of the wiring layer and the side wall which is conventionally formed of silicon dioxide or the like are formed of the insulating layer containing the group IVa element on the side surface of the wiring layer, the wiring is formed. The insulating layers on the upper and side surfaces of the layer are less likely to be etched, and the etching resistance of the wiring layer is improved.

Further, in the semiconductor device of the present invention, the insulating layer above the wiring layer and the side wall of the wiring layer are provided with the side wall which is conventionally formed of silicon dioxide or the like by the silicon dioxide or silicon nitride film containing the group IVa element. Since it is formed, the insulating layers on the upper and side surfaces of the wiring layer are less likely to be etched, and the etching resistance of the wiring layer is improved.

Further, since the method for manufacturing a semiconductor device of the present invention includes the step of forming an insulating layer containing a group IVa element on the insulating layer such as the sidewall formed on the wiring layer and the side surface, Since the insulating layer that functions as an etching protection film for the wiring layer and that particularly includes the group IVa element formed in the inclined portion of the sidewall is an insulating layer having a thickness in the vertical direction, Is
It will become a stronger etching protection layer.

Since the method of manufacturing a semiconductor device of the present invention includes a step of forming an insulating layer containing a group IVa element as a sidewall on the wiring layer and the side surface, the insulating layer on the wiring layer upper and side surfaces is It is difficult to be etched, and the etching resistance of the wiring layer is improved.

[0021]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a semiconductor device of the present invention. In the figure, 14 is an insulating layer made of silicon dioxide containing a group IVa element or silicon nitride containing a group IVa element. The same symbols as those used for indicate the same or corresponding parts. The process of forming this semiconductor device will be described step by step. First, as shown in FIG. 2, a LOCOS (LOCAL OXIDATION OF) made of silicon dioxide is formed on a portion of the main surface of the semiconductor substrate 1 containing P-type impurities to be an inactive region.
SILICON) Isolation area 2 is formed. Next, a silicon dioxide layer to be the gate insulating layer 3 is formed using a technique such as thermal oxidation of a silicon substrate, and then a sputtering method or a CVD method is used to form a poly containing impurities to be the word lines 4a and 4b. The silicon layer 4 is laminated. Further, an insulating layer 5 made of silicon dioxide is formed in contact with the upper layer (FIG. 3).

Next, a resist pattern is formed by photolithography on regions other than the portions where the polysilicon layer is to be left as the word lines 4a and 4b, and then RIE (REACTI
The word lines 4a and 4b, which can serve as gate electrodes, are formed by patterning by anisotropic etching by the VE ION ETCHING method (FIG. 4). Next, as shown in FIG.
The low-concentration impurity layer 7 which is a constituent element of the source / drain region 9 is formed by implanting N-type ions (P, As, etc.). The arrow shown in the figure is the ion implantation direction, which indicates that the ions are implanted vertically downward.
Also, although not shown here for simplification of description,
In a semiconductor device such as a normal DRAM (DYNAMIC RUNDAM ACCESS MEMORY), a CMOS (COMPLEMENTARY META
L OXIDE SEMICONDUCTOR) structure is generally adopted, and a structure such as shown in FIG. 1 in which only N-channel transistors are formed is not possible. Therefore, when forming the low-concentration impurity region 7 which is a constituent element of the source / drain region 9 shown in FIG. 5, in the actual process, the source / drain region including the N-type impurity in the N-channel transistor forming region is formed. Process and source / source containing P-type impurity in P-channel transistor formation region
Two steps of forming the drain region are required. Also,
Similarly, for forming the high-concentration impurity regions, different types of ions must be implanted in the ion implantation.

After that, a silicon dioxide layer 6a is formed on the entire surface of the semiconductor substrate 1 by the CVD technique or the like (FIG. 6). After that, anisotropic etching is performed until one main surface of the semiconductor substrate 1 in which the source / drain regions 9 are formed is exposed, and at least contacts the side surfaces of the word lines (wiring layers) 4a and 4b capable of forming gate electrodes. Thus, the sidewall 6b is formed (FIG. 7). Next, as in the case shown in FIG. 4, N-type impurity ions are implanted into the semiconductor substrate 1 in a direction perpendicular to the semiconductor substrate 1 (in the direction of symbol 16) to increase the impurity concentration of the source / drain regions 9. A concentration impurity region 8 is formed (FIG. 8).

Next, as shown in FIG. 9, an insulating layer 10 made of silicon dioxide is laminated on the entire surface of the semiconductor substrate 1 to a thickness of 50 nm or less by a CVD technique or a sputtering method (FIG. 9). Further, as shown in FIG. 10, an insulating layer 14 containing a group IVa element is formed. In the conventional technique, the layer 11 made of silicon dioxide or silicon nitride was simply formed in place of the silicon dioxide layer 14 containing the IVa group element. By using the contained silicon dioxide, it becomes possible to obtain a wiring layer (word line) protective film that is less likely to be etched than conventional and has good etching resistance. The inclusion of the IVa group element improves the etching resistance, which means that the film has a low sputtering rate. Since the sputter rate depends on the mass of the film to be etched and its surface binding energy, by controlling the amount of group IVa element contained in the insulating film, the mass and surface binding energy are changed to control the sputter rate. Because you can. Further, the silicon dioxide layer 14 containing Ge element, which is one of the insulating layers containing Group IVa element, has a dimethylgermane content in an atmosphere in which SiH ₄ and N ₂ O are mixed in a ratio of 1:10 to 1: 100. In the gas added with 1 to 50% of the total gas flow rate,
It can be formed using the CVD technique under the conditions of pressure of 1 to 10 Torr and temperature of 600 to 800 ° C.

On the semiconductor device thus formed, an insulating layer 17 made of silicon dioxide is further laminated by using a CVD technique or a sputtering method, and the top surface of the insulating layer 17 is flattened by etching back or reflowing by heat treatment. And flatten (Fig. 11). Next, the insulating layer 1
In order to form a contact hole for electrically contacting the wiring layer to be formed on the wiring layer 7 and the source / drain region 9 formed below the one main surface of the semiconductor substrate 1, the contact of the insulating layer 17 is formed. A resist pattern 13 is formed on the area other than the hole forming area by photolithography (FIG. 12).

The formation position of the resist pattern 13 is determined by alignment with reference to the positions of the components of the semiconductor device that have already been formed.
It is undeniable that the constituent elements of the reference semiconductor device cannot be formed exactly in exactly the same manner as the design, and some dimensional deviation may occur. Therefore, there is a high possibility that the formation position of the resist pattern used as the etching mask will be displaced when compared with the designed structure. Also, when the alignment in the photolithography process is not accurate, the formation position of the resist pattern that will be the etching mask is also the same.
Misalignment may occur when compared to the designed structure.

If the position of the contact hole originally formed is the position indicated by the symbol E in FIG. 12, it is determined that the resist pattern 13 is formed in the region other than the region indicated by the symbol F by being displaced by the distance X due to misalignment or the like. I assume. By using this resist pattern 13 as a mask, a RIE (REACTIVE ION ETCHING) method using a gas such as C ₄ F ₈ is used.
Etching is performed perpendicularly to the semiconductor substrate 1. The etching conditions at this time are such that the selection ratio of the insulating layer 17 to the silicon dioxide layer 14 containing the group IVa element (Ge) is at least 5 or more. FIG. 13 shows a cross-sectional view of the semiconductor device when etching is performed until the silicon dioxide layer 14 containing the group IVa element (Ge) on the source / drain regions 9 is exposed by the method with the above selection ratio. .

Silicon dioxide, which was introduced in the prior art,
Alternatively, a semiconductor device in which any one of silicon nitride is formed as an insulating layer, which corresponds to FIG.
Comparing the etching conditions with No. 3, in the case of this embodiment,
Since the silicon dioxide layer 14 containing the IVa group element (Ge) is used as the insulating layer which is the etching protection film of the wiring layer, the insulating layer 11 or 14 above the source / drain region 9 is exposed at each stage. The portion corresponding to the point C in FIG. 27 of the conventional technique and the point G in FIG. 13 are in a state where they are hardly etched and remain.

Further, FIG. 14 shows a cross-sectional view at the stage when the contact holes are completed by etching until the main surface of the semiconductor substrate 1 on which the source / drain regions 9 are formed is exposed. A point H in the drawing is a portion corresponding to the point G in FIG. 13 and a portion corresponding to the point D in FIG. 28 showing the conventional technique. In this conventional technique, the sidewall 6b formed by using the silicon oxide film and the silicon nitride film is largely scraped off by anisotropic etching, whereas in the present embodiment, the insulating film made of silicon dioxide is used. The insulating layer 14 having etching resistance five times or more that of the layer 17 is formed as an etching protection film for the wiring layers (word lines) 4a and 4b so that the wiring layers 4a and 4b are not etched, or Wiring layer 4a,
It is possible to prevent the contact from being formed in the vicinity of 4b. Thus, even when the contact hole diameter and the dimension of the source / drain region 9 in the gate width direction are almost the same, and the etching mask for forming the contact hole is deviated, the wiring layer (word line) is formed. ) Since the etching protection film for protecting 4a and 4b is formed, it is possible to form the contact hole in a self-aligned manner with a sufficient distance from the wiring layer.

Further, in the above embodiment, the silicon dioxide layer 14 containing the IVa group element is formed as the wiring layer protection film, but even if the silicon nitride film containing the IVa group element is formed, a semiconductor having the same effect is obtained. The device can be obtained.

Embodiment 2 FIG. Next, an embodiment of the present invention will be described with reference to FIGS. 15 to 24 and the drawings of the first embodiment. As shown in FIG. 15, the present invention forms an insulating layer 18 by laminating an insulating material containing a group IVa element as used in the construction of the semiconductor device in Example 1 on the wiring layers 4a and 4b. In Example 1, the sidewall 6b
Was formed of a silicon oxide film or a silicon nitride film, which is a commonly used insulating material, but in the present embodiment, an insulating material such as a silicon oxide film containing a group IVa element or a silicon nitride film is used. The side wall 19 is composed of.

Next, a method of manufacturing the above semiconductor device will be briefly described. First, as in the case of FIG. 2 of the first embodiment, L is formed in a region that is an inactive region on one main surface of the semiconductor substrate 1.
The OCOS isolation region 2 is formed. Next, an insulating layer 3 made of a silicon dioxide layer to be a gate insulating film is formed on the entire surface of the semiconductor device by using a technique such as thermal oxidation of a silicon substrate. Further, a polysilicon layer 4 to be the gate electrodes (word lines) 4a and 4b is formed on the insulating layer 3. Further, a silicon dioxide layer 18 containing a Ge element which is one of the IVa group elements is formed on the polysilicon layer 4 with SiH.
_In an atmosphere in which ₄ and N ₂ O are mixed in a ratio of 1:10 to 1: 100, the pressure is 1-10T in a gas in which dimethylgermane gas is added by 1-50% with respect to the total gas flow rate.
CVD under conditions of orr and temperature of 600 ° C to 800 ° C
It is formed by using a technique (FIG. 16).

After that, a resist pattern is formed so that only the regions to be left as word lines are exposed, and anisotropic etching is performed using this as an etching mask to form word lines 4a and 4b (FIG. 17). Next, as shown in FIG. 18, a low-concentration impurity layer 20 which is a constituent element of the source / drain regions 9 is formed by implanting N-type ions (P, As, etc.). At this time, it is shown that the semiconductor substrate 1 is ion-implanted vertically downward (in the direction of the arrow 22). Although not shown here for simplification of description, as in the case of the first embodiment, a normal DRAM (DYNAMIC RUNDAM ACCESS MEMOR) is used.
In semiconductor devices such as Y), CMOS (COMPLEMENTA)
A RY METAL OXIDE SEMICONDUCTOR) structure is generally adopted, and a structure such as that shown in FIG. 15 in which only N-channel transistors are formed is not possible. Therefore, when forming the low-concentration impurity region 20 of the source / drain region 9 shown in FIG. 18, in the actual process, the process of forming the source / drain region containing the N-type impurity of the N-channel transistor forming region, P Two steps of forming source / drain regions containing P-type impurities in the channel transistor forming region are required. The same applies to the formation of the high-concentration impurity region, and at least 2
Ion implantation steps are required.

Thereafter, a silicon oxide film 19a (or a silicon nitride film) containing a group IVa element is formed by the CVD technique or the like (FIG. 19), and the source / drain regions 9 are formed.
Anisotropic etching is performed until one main surface of the semiconductor substrate 1 on which the gates are formed is exposed, and sidewalls 19 are formed so as to contact at least the side surfaces of the word lines 4a and 4b capable of forming gate electrodes (FIG. 20). ). Next, as in the case shown in FIG. 18, N-type impurity ions are added to the semiconductor substrate 1.
Impurity ion implantation is performed in the vertical direction (direction of symbol 23) (FIG. 21) to form the high-concentration impurity region 21 which is a constituent element of the source / drain region 9 to form the semiconductor device shown in FIG. It becomes possible to do.

On the upper layer of the semiconductor device thus formed,
Whether the silicon oxide film 17 is laminated by the CVD technique or the sputtering method so as to fill the insulating layer 18, the sidewall 19 and the like, and the unevenness on the upper surface of the silicon oxide film 17 is etched back or reflowed by heat treatment. And flatten (Fig. 22). Next, the insulating layer 1
First, in order to form a contact hole for electrically connecting the wiring layer to be formed on 7 and the source / drain region 9 formed under the one main surface of the semiconductor substrate 1, the insulating layer 17 is first formed. A resist pattern 13 serving as a contact hole etching mask is formed by photolithography on a region other than the contact hole forming region (FIG. 2).
3).

Next, as in Example 1, R using a gas such as C ₄ F ₈ was used with this resist pattern 13 as a mask.
By the IE method, anisotropic etching is performed so that a groove can be formed perpendicularly to the semiconductor substrate 1. Further, the etching conditions at this time are that the silicon oxide film 17 and the insulating layer 18 containing the IVa group element, and the sidewalls made of the same material have a selectivity of 1: 5 or more, and that the insulating layer containing at least the IVa group element is A contact hole is formed by performing anisotropic etching so as to have etching resistance five times or more that of a simple silicon oxide film or silicon nitride film (FIG. 2).
4).

Silicon dioxide, which was introduced in the prior art,
Alternatively, comparing the etching state of FIG. 28 showing a semiconductor device in which any of silicon nitride is formed as an insulating layer and FIG. 24 of this embodiment, in the case of this embodiment (FIG. 24),
Insulating layers 18 and 19 having etching resistance five times or more that of the insulating layer 17 made of silicon dioxide containing the IVa group element (Ge) are formed as sidewalls for protecting the wiring layers (word lines) 4a and 4b. Therefore, the portion corresponding to the point D in FIG. 28 and the point J (the upper surface of the side wall) in FIG. Thus, in this embodiment,
By forming the insulating layers 18 and 19 containing the IVa group element so as to surround the wiring layers (word lines) 4a and 4b, the contact hole diameter and the size of the source / drain region in the gate width direction are almost the same value. Also, even if the etching mask used to form the contact hole is misaligned, the structure has an etching protection film that protects the wiring layer. Can be formed.

In the above embodiment, the silicon dioxide layer containing the IVa group element is formed as the wiring layer protective film.
The same effect can be obtained by forming a silicon nitride film containing a group IVa element.

[0039]

As described above, according to the present invention, a silicon oxide film containing a group IVa element is formed in an insulating layer formed on the wiring layer or an insulating layer such as a sidewall formed so as to cover the wiring layer. Or, since it is configured by using a silicon nitride film, even if a contact hole is formed in a narrow region with a very small manufacturing margin by using the self-alignment method, the wiring layer is not penetrated and etched, and Further, it is possible to suppress the formation of a contact at a position close to the wiring layer, and it is possible to obtain a highly accurate semiconductor device.

According to the present invention, the insulating layer formed on the wiring layer or the insulating layer such as the sidewall formed so as to cover the wiring layer has a silicon oxide film containing a group IVa element or a silicon nitride film. Since the manufacturing method includes a step of using a film, even if a contact hole is formed with a very small manufacturing margin in a small area by using the self-alignment method, the wiring layer will be penetrated and etched. In addition, it is possible to suppress the formation of a contact at a position close to the wiring layer, and it is possible to obtain a highly accurate semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 11 is a sectional view necessary for explaining Embodiment 1 of the present invention.

FIG. 12 is a sectional view necessary for explaining Embodiment 1 of the present invention.

FIG. 13 is a sectional view necessary for explaining Embodiment 1 of the present invention.

FIG. 14 is a cross-sectional view necessary for explaining Embodiment 1 of the present invention.

FIG. 15 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 20 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 22 is a sectional view necessary for explaining Embodiment 2 of the present invention.

FIG. 23 is a sectional view necessary for explaining Embodiment 2 of the present invention.

FIG. 24 is a sectional view necessary for explaining Embodiment 2 of the present invention.

FIG. 25 is a diagram showing a conventional semiconductor device.

FIG. 26 is a diagram necessary for explaining a conventional technique.

FIG. 27 is a diagram necessary for explaining a conventional technique.

FIG. 28 is a diagram necessary for explaining a conventional technique.

[Explanation of symbols]

1. Semiconductor device, 2. LOCOS isolation region, 3. Gate insulating layer, 4a, 4b. Word line (wiring layer), 5. Insulating layer, 6a. Insulating layer, 6b. Sidewalls, 7. Low concentration impurity layer, 8. High concentration impurity layer, 9. Source / drain regions 10, 11, 12. Insulating layer, 13. Resist pattern, 14. Insulating layer containing IVa group element, 15, 16. Ion implantation direction, 17. Insulating layers 18 ,. Insulating layer containing IVa group element, 19. Sidewalls, 20. Low concentration impurity layer, 21. High concentration impurity layer, 22, 23. Ion implantation direction

Claims (6)

[Claims] 1. A semiconductor substrate having an active region formed on one main surface, a silicon layer formed on the semiconductor substrate via a first insulating layer, and formed so as to cover at least an upper surface and a side surface of the silicon layer. And a third insulating layer containing a group IVa element formed on the side surface of the silicon layer of the second insulating layer. 2. The semiconductor device according to claim 1, wherein the third insulating layer is formed of silicon dioxide containing a group IVa element or silicon nitride. 3. A semiconductor substrate, a silicon layer formed on the semiconductor substrate via a first insulating layer, and an IVa formed in contact with and covering the upper surface and the side surface of the silicon layer.
A semiconductor device having a second insulating layer containing a group element. 4. The semiconductor device according to claim 3, wherein the second insulating layer is formed of silicon dioxide containing a group IVa element or silicon nitride. 5. A step of forming a silicon layer via a first insulating layer on a semiconductor substrate having an active region formed on one main surface, and a second step of covering at least an upper surface and a side surface of the silicon layer. A method of manufacturing a semiconductor device, comprising: a step of forming an insulating layer; and a step of forming a third insulating layer containing a group IVa element on a side surface of a silicon layer of the second insulating layer. 6. A step of forming a silicon layer on a semiconductor substrate having an active region formed on one main surface thereof with a first insulating layer interposed between the group IVa element and at least the upper surface and the side surface of the silicon layer. A method of manufacturing a semiconductor device, comprising the step of forming a second insulating layer containing: