JPH0818063A - Manufacture of film transistor, and film transistor and liquid crystal display - Google Patents

Abstract

PURPOSE:To provide the manufacture of a high-quality TFT having favorable property. CONSTITUTION:In the manufacture of a film transistor, which grows and stacks the gate insulating layer 3 and the semiconductor layer 4 of a film transistor by plasma CVD method, when growing and stacking the semiconductor layer on the gate insulating layer, the interval between discharge electrodes is changed, with the plasma discharge maintained, after growing the gate insulating layer, and then the semiconductor layer is grown.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of manufacturing a thin film transistor used as a switching element of a liquid crystal display device.

[0002]

2. Description of the Related Art Thin film transistor (TFT)
Transistor) has already been put to practical use in liquid crystal display devices and contact sensors. In particular, the liquid crystal display device has features such as portability, thinness, light weight, and space saving, and its future potential has attracted great attention. Among these liquid crystal display devices, a thin film transistor type liquid crystal display device capable of high contrast, high image quality, halftone display and fast response is becoming mainstream.

As the TFT of the above liquid crystal display device, an amorphous silicon (a-Si) based semiconductor is used, which has a large active layer area and can be formed at a relatively low temperature. In this a-Si TFT, a semiconductor layer made of an a-Si film which is an active layer is sandwiched on a transparent insulating substrate,
An inverted staggered structure or a positive staggered structure in which a gate electrode is arranged on one side and a source electrode and a drain electrode are arranged on the other side is often adopted.

The layer between the gate insulating layer and the semiconductor layer of such a TFT corresponds to the channel portion of the TFT and is extremely important for improving the switching characteristics of the TFT. In addition, a TFT is provided between the semiconductor layer and the semiconductor protective layer.
It is extremely important to improve the switching characteristics of the TFT in the rear channel portion of the TFT, like the interlayer between the gate insulating layer and the semiconductor layer.

Conventionally, for example, a TFT having an inverted staggered structure
In the plasma CVD method, a gate insulating layer forming gas is introduced into the reaction chamber to form a gate insulating layer on the glass insulating substrate on which the gate electrode is formed. After that, the discharge is stopped once, the reaction chamber is evacuated to a vacuum, and then a semiconductor layer forming gas is introduced to form semiconductor layers in layers. Furthermore, when a semiconductor protective layer is laminated on the semiconductor layer,
After the semiconductor layer is formed, the discharge is temporarily stopped, the reaction chamber is evacuated to a vacuum, and then a semiconductor protective layer forming gas is introduced to form a semiconductor protective layer in a stacked film.

In the case of a TFT having a positive staggered structure,
The lamination of the gate insulating layer and the semiconductor layer is opposite.

[0007]

As described above, in the method of manufacturing a TFT, after forming the gate insulating layer or the semiconductor layer, the discharge is stopped once to form the semiconductor layer or the gate insulating layer. The initial discharge during the formation of the semiconductor layer or the gate insulating layer becomes unstable, and the defect density (dangling bond: near the interface between the gate insulating layer and the semiconductor layer:
Dangling bonds) are generated, the interface between the gate insulating layer and the semiconductor layer is not formed well, and there is a problem that a TFT with good characteristics cannot be obtained. Also, when forming a semiconductor protective layer on a semiconductor layer, if the semiconductor layer is formed and then the discharge is stopped and the semiconductor protective layer is formed, the initial discharge during the formation of the semiconductor protective layer becomes unstable. There is a problem that a defect density is generated in the vicinity of the interface between the semiconductor layer and the semiconductor protective layer, the interface between the semiconductor active layer and the semiconductor protective layer is not formed well, and a TFT having good characteristics cannot be obtained.

In some cases, film swelling or film peeling may occur at the interface between the gate insulating layer and the semiconductor layer or between the semiconductor layer and the semiconductor protective layer, resulting in a problem of reduced yield.

In addition, in the conventional manufacturing method, since the interval between the discharge electrodes is not changed when the discharge is continued, the plasma state becomes unstable when forming each layer, and the discharge is interrupted on the way. There is a problem that the state cannot be obtained.

The present invention has been made in order to solve the above-mentioned problems, and has excellent characteristics by forming an excellent interface between the gate insulating layer and the semiconductor layer, and further between the semiconductor layer and the semiconductor protective layer. An object of the present invention is to provide a method of manufacturing a thin film transistor which can obtain a high quality thin film transistor, a thin film transistor obtained by the manufacturing method, and a liquid crystal display device using the thin film transistor.

[0011]

[Means for Solving the Problems]

First Means: Plasma CVD of a gate insulating layer and a semiconductor layer of a thin film transistor having at least a gate insulating layer and a semiconductor layer laminated on the gate insulating layer
In the method for manufacturing a thin film transistor in which a semiconductor film is laminated by the method, when a semiconductor layer is laminated on the gate insulating layer,
After forming the gate insulating layer, the interval between the discharge electrodes was changed while maintaining the plasma discharge, and then the semiconductor layer was formed.

More specifically, when a semiconductor layer is laminated on the gate insulating layer, the gate insulating layer is formed and then H
The distance between the discharge electrodes was changed while maintaining the plasma discharge of the _two gases, and then the semiconductor layer was formed.
Further, after forming the gate insulating layer, the interval between the discharge electrodes was changed while maintaining the plasma discharge containing a non-film forming gas as a main component, and then the semiconductor layer was formed. In addition, after forming the gate insulating layer, H ₂ , He, Ar, N
The distance between the discharge electrodes was changed while maintaining the plasma discharge containing at least one of the ₂ and NH ₃ gases as the main component, and then the semiconductor layer was formed. Also,
After forming the gate insulating layer, a discharge period at a pressure lower than the pressure at the time of forming the gate insulating layer was provided, and the interval between the discharge electrodes was changed while maintaining plasma discharge, and then the semiconductor layer was formed. Second means: A semiconductor layer of a thin film transistor having at least a semiconductor layer and a semiconductor protective layer laminated on the semiconductor layer, and a thin film transistor manufacturing method for laminating a semiconductor protective layer by plasma CVD. When the semiconductor protective layer was laminated and formed, the semiconductor layer was formed, and then the interval between the discharge electrodes was changed while maintaining the plasma discharge, and then the semiconductor protective layer was formed.

More specifically, when the semiconductor protective layer is laminated on the semiconductor layer, after the semiconductor layer is formed, the distance between the discharge electrodes is changed while maintaining the plasma discharge of H ₂ gas, The semiconductor protective layer was formed. Further, after forming the semiconductor layer, the interval between the discharge electrodes was changed while maintaining the plasma discharge containing the non-film forming gas as a main component, and then the semiconductor protective layer was formed. Also,
After forming the semiconductor layer, H ₂ , He, Ar, N ₂ , NH
The interval of the discharge electrodes is changed while maintaining the plasma discharge containing at least one of the _three gases as the main component,
After that, the semiconductor protective layer was formed. Further, after forming the semiconductor layer, a discharge period lower than the pressure at the time of forming the semiconductor layer is provided, and the interval between the discharge electrodes is changed while maintaining the plasma discharge, and then the semiconductor protective layer is formed. . Third means: Plasma CVD of the above semiconductor layer and gate insulating layer of a thin film transistor having at least a semiconductor layer and a gate insulating layer formed on the semiconductor layer.
In the method for manufacturing a thin film transistor in which a gate insulating layer is laminated on a semiconductor layer,
After forming the semiconductor layer, the interval between the discharge electrodes was changed while maintaining plasma discharge, and then the gate insulating layer was formed.

More specifically, when the gate insulating layer is laminated on the semiconductor layer, the gap between the discharge electrodes is changed while the plasma discharge of H ₂ gas is maintained after the semiconductor layer is formed. The gate insulating layer was formed. Further, after forming the semiconductor layer, the interval between the discharge electrodes was changed while maintaining the plasma discharge containing a non-film forming gas as a main component, and then the gate insulating layer was formed. Also,
After forming the semiconductor layer, H ₂ , He, Ar, N ₂ , NH
The interval of the discharge electrodes is changed while maintaining the plasma discharge containing at least one of the _three gases as the main component,
After that, a gate insulating layer was formed. In addition, after forming the semiconductor layer, a discharge period at a pressure lower than the pressure at the time of forming the semiconductor layer is provided, and the interval between the discharge electrodes is changed while maintaining plasma discharge, and then the gate insulating layer is formed. .

[0015]

According to the present invention, the initial discharge can be stabilized and a good TFT can be obtained when the next layer is formed with respect to the layer formed first. At that time, by changing the interval between the discharge electrodes, the discharge until the next film formation can be optimized and stably maintained, and the initial discharge during the film formation of the gate insulating layer, the semiconductor layer and the semiconductor protective layer can be suppressed. Can be more stable. Thereby, the defect density in the vicinity of the interface between the gate insulating layer and the semiconductor layer and in the vicinity of the interface between the semiconductor layer and the semiconductor protective layer can be reduced, and a TFT having good characteristics can be obtained. In addition, it is possible to prevent film swelling and film peeling that occur at the interface, thus improving productivity.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings.

Embodiment 1. FIG. 1 shows a TFT of an active matrix type liquid crystal display device according to the first embodiment. This TFT is a molybdenum-tantalum (Mo-) formed integrally with a gate line (not shown) on the glass insulating substrate 1.
Ta) having a predetermined shape made of Ta) and a film thickness of 0..T formed on the insulating substrate 1 so as to cover the gate electrode 2.
A gate insulating layer 3 made of a SiN _x film having a thickness of 3 μm and an a-Si film having a thickness of 0.05 μm or a microcrystalline silicon film which is laminated so as to cover the gate insulating layer 3 corresponding to the gate electrode 2 or A semiconductor layer 4 of a predetermined shape made of a polycrystalline silicon film, a semiconductor protection layer 5 of a predetermined shape made of a SiN _x film having a film thickness of 0.3 μm laminated so as to cover a part of the semiconductor layer 4, An n ⁺ a-Si film having a thickness of 0.05 μm, which is laminated to cover the semiconductor protective layer 5 and the source and drain regions on the semiconductor layer.
An n-type semiconductor layer 6 made of a film, and chrome (Cr) or aluminum (A) laminated on the n-type semiconductor layer 6 and partially extending to the source region on the gate insulating layer 3.
1) and a source electrode 7 formed of the same, and Cr or Al integrated with a signal line (not shown) which is also laminated on the n-type semiconductor layer 6 and a part of which extends to the drain region on the gate insulating layer 3. And a source electrode 7, a drain electrode 8 and an insulating protective layer 9 made of a SiN _x film covering the channel region on the n-type semiconductor layer 6. The source electrode 7 is connected to a pixel electrode 10 made of ITO (Indium Tin Oxide) laminated on the gate insulating layer 3.

As shown in FIG. 2 (a), this TFT is manufactured by first forming an M on the glass insulating substrate 1 by a sputtering method.
A metal film made of o-Ta is formed, and this metal film is etched by photolithography to form a gate electrode 2 having a predetermined shape together with the gate line.

Next, the glass insulating substrate 1 on which the gate electrode 2 is formed is heated to 350 ° C., and silane (Si
H ₄ ), ammonia (NH ₃ ), and nitrogen (N ₂ ) for forming a gate insulating layer are introduced, and a plasma CVD method by glow discharge (plasma discharge) described later is performed.
As shown in (b), a gate insulating layer 3 made of a SiN _x film having a thickness of 0.3 μm is formed. Then, while maintaining the glow discharge at the time of forming the gate insulating layer 3, the introduced gas is switched from the gas for forming the gate insulating layer to hydrogen (H ₂ ) or helium (He) gas to continue the glow discharge. Then, SiH ₄ gas is introduced together with H ₂ or He gas to form a- for forming a semiconductor layer having a thickness of 0.05 μm.
The Si film 4a is formed. After that, while maintaining the glow discharge at the time of forming the a-Si film 4a, the introduction of SiH ₄ gas is stopped, and the H ₂ or He gas is switched to the semiconductor protective layer forming gas composed of SiH ₄ and N _2. , Film thickness 0.3μ
A SiN _x film 5a for forming a semiconductor protective layer of m 2 is formed. Then, the SiN _x film 5a is etched by a photolithography method to produce a SiN _x film 5a, as shown in FIG.
It is formed on the semiconductor protective layer 5 having a predetermined shape.

Next, the glass insulating substrate 1 on which the semiconductor protective layer 5 and the like are formed is heated to form phosphine (P
An n-type semiconductor layer forming gas composed of H ₃ ), SiH ₄ is introduced, and an n ⁺ a-Si film having a thickness of 0.05 μm is formed by plasma CVD so as to cover the semiconductor protective layer 5. Then, as shown in FIG. 2D, by photolithography, the n ⁺ a-Si film is etched to form the n-type semiconductor layer 6 having a predetermined shape, and the underlying a-Si film is etched. Thus, the semiconductor layer 4 having a predetermined shape is formed.

After that, a transparent conductive film of ITO is formed on the glass insulating substrate 1 on which the n-type semiconductor layer 6 and the like are formed by a sputtering method, and is etched by a photolithography method to form a predetermined film on the gate insulating layer 3. A pixel electrode 10 of a predetermined shape made of a transparent conductive film is formed at the position.

Further, a metal film made of Cr or Al is formed on the glass insulating substrate 1 on which the pixel electrode 10 and the like are formed by a sputtering method. Then, etching is performed by photolithography to integrally form the source electrode 7 connecting the n-type semiconductor layer 6 and the pixel electrode 10 and the drain electrode 8 connected to the n-type semiconductor layer 6 together with the signal line. Then, using the source electrode 7 and the drain electrode 8 as a mask, etching is performed by photolithography to remove the n-type semiconductor layer 6 in the channel region. After that, these source electrode 7 and drain electrode 8
Plasma CV is formed on the glass insulating substrate 1 on which
It is manufactured by forming an insulating protective layer made of a SiN _x film by the D method (see FIG. 1).

FIG. 3 is a plasma CVD used for forming the SiN _x film for forming the gate insulating layer, the a-Si film for forming the semiconductor layer and the SiN _x film for forming the semiconductor protective layer. The principal part structure of an apparatus is shown. This plasma CVD apparatus is a parallel plate type plasma CVD apparatus, and a disk-shaped high-frequency electrode 13 having a diameter of about 15 cm is installed in the reaction chamber 12 of the plasma CVD apparatus. Disc-shaped ground electrode 14 having almost the same diameter
Is installed. The ground electrode 14 can be moved up and down by an elevating device 15 provided outside the reaction chamber 12 so that the distance between the ground electrode 14 and the high frequency electrode 13 can be arbitrarily changed with an accuracy of ± 0.01 mm. The reaction chamber 12 can be evacuated by a vacuum exhaust device 16. Further, outside the reaction chamber 12, a gas introduction device 17 for introducing the film forming gas and the discharge maintaining gas into the reaction chamber 12 from the high frequency electrode 13 side is provided. Furthermore, in the ground electrode 14,
The glass insulating substrate 1 placed on the ground electrode 14 is
A resistance heater 18 that heats with an accuracy of 10 ° C. is provided. A high frequency power source 19 is connected to the high frequency electrode 13.

SiN for forming a gate insulating layer
_{The x} film, the a-Si film for forming the semiconductor layer, and the SiN _x film for forming the semiconductor protective layer are formed by first reacting the glass insulating substrate 1 on which the gate electrode is formed with the reaction of the plasma CVD apparatus. Fixed on the ground electrode 14 of the chamber 12,
The inside of the reaction chamber 12 is evacuated. Then, the glass insulating substrate 1 is heated to 3 by the resistance heater 18 provided on the ground electrode 14.
After heating to 50 ° C., SiH ₄ gas of 10 sccm and NH ₄ was used in the reaction chamber 12 as a gas for forming a gate insulating layer.
Gas at a flow rate of 60 sccm and N ₂ gas at a flow rate of 400 sccm were introduced to adjust the pressure of the gas atmosphere in the reaction chamber 12 to 0.8.
Set to Torr. The high frequency electrode 13 and the ground electrode 14
Set the electrode distance between and to 30 mm,
Electric power of 0 W is supplied to generate glow discharge between the electrodes to form a gate insulating layer made of a SiN _x film.

Then, at the same time when the introduction of the gas for forming the gate insulating layer is stopped, H ₂ gas is introduced at a flow rate of 500 sccm so that the pressure of the gas atmosphere in the reaction chamber 12 is 0.3 T.
Orr is set, the electrode interval is set to 35 mm, and the high frequency power supply 19 supplies 35 W of electric power to continue the glow discharge between the electrodes without stopping the glow discharge at the time of forming the gate insulating layer. The plasma discharge during film formation at this time is appropriately 3 seconds or more. In this way, by introducing a large amount of H ₂ gas, the pressure of the gas atmosphere in the reaction chamber 12 is set to 0.3 Torr.
By so doing, it is possible to eliminate the influence of residual gas at the time of forming the gate insulating layer. Further, the discharge can be stably maintained by setting the electrode interval to a large value of 35 mm.

Then, H ₂ gas was introduced at a flow rate of 500 sccm, and the pressure of the gas atmosphere in the reaction chamber 12 was changed to 1.2 To.
In addition to rr, the electrode interval is set to 28 mm, and 50 W of electric power is supplied from the high frequency power source 19 to stably continue glow discharge. After that, 30 scc of SiH gas is used.
It is introduced at a flow rate of m, the electrode interval is changed to 26 mm, and an a-Si film having a thickness of 0.05 μm is formed. In this case, H ₂
By performing continuous discharge of plasma, it is possible to stably maintain the discharge until the a-Si film and its formation.
Further, by making the pressure before forming the a-Si film smaller than the pressure when forming the a-Si film, the defect density at the interface can be reduced.

Next, the introduction of the above SiH ₄ gas was stopped, H ₂ gas was introduced at a flow rate of 500 sccm, the pressure of the gas atmosphere in the reaction chamber 12 was 0.3 Torr, and the electrode interval was 35 mm. The glow discharge at the time of setting the a-Si film is continued without stopping. It is appropriate that the discharge at this time is 5 seconds or more. Then NH ₃
Gas is introduced at a flow rate of 400 sccm to set the pressure of the gas atmosphere in the reaction chamber 12 to 1.5 Torr, and
The electrode interval is changed to 24 mm, and the high frequency power 19 to 60 W
Power is supplied to continue glow discharge between the electrodes.
In order to stabilize the discharge at this time, it is appropriate to set the discharge time to 3 seconds or more. Then, the introduction of H ₂ gas is stopped, N ₂ gas is introduced at a flow rate of 500 sccm, the electrode interval is set to 20 mm, and the glow discharge is stably continued. After that, SiH ₄ gas is added at 50 sccm
At a flow rate of 0.5 μm to form an n ⁺ a-Si film for forming a semiconductor protective layer.

By the way, when the distance between the high-frequency electrode 13 and the ground electrode 14 is continuously changed (changed in multiple steps) as described above, it depends on the type of gas to be introduced and the pressure of the gas atmosphere in the reaction chamber. The plasma discharge can be stably continued without stopping, and the defect density near the interface between the gate insulating layer 3 and the semiconductor layer 4 and near the interface between the semiconductor layer 4 and the semiconductor protective layer 5 can be reduced.

That is, conventionally, the process condition of each thin film has not been extremely changed as described above, and it is also difficult to change the process condition extremely and to keep the plasma stable. It wasn't. However, as in this embodiment, the electrode interval between the high frequency electrode 13 and the ground electrode 14 is continuously changed (changed in multiple steps).
Then, depending on the type of introduced gas and the pressure of the gas atmosphere in the reaction chamber, for example, the electrode interval is narrowed when the pressure of the gas atmosphere in the reaction chamber is high, and widened when the pressure is low, to control the process conditions. Causes the Si of the gate insulating layer 3 to
The N _x film 3a, the a-Si film 4a of the semiconductor layer 4, and the n ⁺ a-Si film 5a of the semiconductor protective layer 5 are formed under the optimum conditions, and the vicinity of the interface between the gate insulating layer 3 and the semiconductor layer 4 and the semiconductor The defect density near the interface between the layer 4 and the semiconductor protective layer 5 can be reduced.

Thereby, the T produced by the above method is
When an active matrix type liquid crystal display device is assembled and operated by a normal process using a liquid crystal display substrate having FT, a TFT having good switching characteristics is obtained.
I was able to

As described above, the continuous discharge is a means for continuously discharging the gate insulating layer 3 to the semiconductor layer 4 and the semiconductor layer 4 to the semiconductor protective layer 5. However, if this discharge is too long, the surface of the gate insulating layer 3 and the surface of the semiconductor layer 4 are deteriorated due to the chemical action of H ₂ plasma, and in some cases, such problems as film swelling and film peeling occur. Therefore, it is preferable that the discharge is 3 to 20 seconds, which is stable and the influence on the surface can be ignored.

Example 2. FIG. 4 shows a TFT of the active matrix type liquid crystal display device according to the second embodiment. This T
The FT is formed on the insulating substrate 1 so as to cover the gate electrode 2 and a gate electrode 2 made of Mo-Ta formed integrally with a gate line (not shown) on the glass insulating substrate 1 and having a predetermined shape. And a gate insulating layer 3 made of a SiN _x film having a film thickness of 0.3 μm and a film thickness of 0.05 μm formed so as to cover the gate insulating layer 3 corresponding to the gate electrode 2.
Of a predetermined shape, which is made of an a-Si film, a microcrystalline silicon film, or a polycrystalline silicon film, and a film thickness formed by lamination so as to cover the source region and the drain region other than the channel region on the semiconductor layer 4. 0.5 μm n ⁺ a
An n-type semiconductor layer 6 made of a Si film, a source electrode 7 laminated on the n-type semiconductor layer 6 and partly extending to the source region on the gate insulating layer 3, and an n-type semiconductor layer 6, a drain electrode 8 integrated with a signal line (not shown) extending partially to the drain region on the gate insulating layer 3, and a source electrode 7 and a drain electrode 8 thereof.
And Si covering the channel region on the n-type semiconductor layer 6
It is composed of an insulating protective layer 9 made of an N _x film. The source electrode 7 is formed by stacking I on the gate insulating layer 3.
It is connected to the pixel electrode 10 made of TO.

As shown in FIG. 5 (a), the TFT is manufactured by first forming a Mo film on the glass insulating substrate 1 by sputtering.
A metal film made of -Ta is formed, and this metal film is etched by photolithography to form the gate electrode 2 having a predetermined shape together with the gate line.

Next, the glass insulating substrate 1 having the gate electrode 2 formed thereon is heated to 350 ° C. to obtain Si H ₄ , N 2.
Introducing a gas for forming a gate insulating layer composed of H ₃ and N ₂ ,
As shown in FIG. 5B, a gate insulating layer 3 made of a Si N _x film having a film thickness of 0.3 μm is formed by a plasma CVD method using glow discharge described later. Then, while maintaining the glow discharge at the time of forming the gate insulating layer, the introduced gas is switched from the gas for forming the gate insulating layer to the H ₂ gas to continue the glow discharge. Further, Si H ₄ gas is introduced together with H ₂ gas to form an a-Si film 4a for forming a semiconductor layer having a film thickness of 0.05 μm.

Next, the glass insulating substrate 1 on which the a-Si film 4a and the like are formed is heated, an n-type semiconductor layer forming gas composed of PH ₃ and SiH ₄ is introduced, and the plasma CVD method described later is used. Then, an n ⁺ a-Si film having a film thickness of 0.05 μm is formed so as to cover the a-Si film 4a. Then, as shown in FIG. 5C, the n ⁺ a-Si film is etched by photolithography to form an n-shaped film having a predetermined shape.
The type semiconductor layer 6 is formed, and at the same time, the underlying a-Si layer is formed.
The film is etched to form the semiconductor layer 4 having a predetermined shape.

Then, a transparent conductive film of ITO is formed on the glass insulating substrate 1 on which the n-type semiconductor layer 6 is formed by the sputtering method and is etched by the photolithography method, as shown in FIG. 5 (c). As described above, the pixel electrode 10 having a predetermined shape made of a transparent conductive film is formed at a predetermined position on the gate insulating layer 3.
To form.

Further, Cr or Al is sputtered on the glass insulating substrate 1 on which the pixel electrodes 10 are formed.
A metal film made of is formed. Then, the source electrode 7 connecting the n-type semiconductor layer 6 and the pixel electrode 10 and the drain electrode 8 connected to the n-type semiconductor layer 6 are integrally formed together with the signal line by photolithography. And
Using the source electrode 7 and the drain electrode 8 as a mask, etching is performed by photolithography to remove the type semiconductor layer 6 in the channel region. After that, an insulating protective layer made of a SiN _x film is formed on the glass insulating substrate 1 on which the source electrode 7 and the drain electrode 8 are formed by a plasma CVD method (see FIG. 4).

In this TFT, a SiN _x film for forming a gate insulating layer, an a-Si film for forming a semiconductor layer, and n ⁺ a for forming an n-type semiconductor layer.
In forming the -Si film, first, the glass insulating substrate 1 having the gate electrode formed thereon is fixed on the ground electrode 14 of the reaction chamber 12 of the plasma CVD apparatus shown in FIG. 3, and the inside of the reaction chamber 12 is evacuated. Then, the glass insulating substrate 1 is heated to 350 ° C. by the resistance heater 18 provided on the ground electrode 14, and then S is used as a gate insulating layer forming gas in the reaction chamber 12.
iH ₄ gas 10 sccm, NH ₃ gas 60 sccc
m and N ₂ gas are introduced at a flow rate of 400 sccm to set the pressure of the film forming gas atmosphere in the reaction chamber 12 to 0.8 Torr. Then, the electrode distance between the high frequency electrode 13 and the ground electrode 14 is set to 30 mm, 50 W of electric power is supplied from the high frequency power source 19 to generate glow discharge between the electrodes, and the film thickness of 0.
A gate insulating layer made of a 3 μm SiN _x film is formed.

Then, the gas for forming the gate insulating layer is stopped, and at the same time, H ₂ gas is introduced at a flow rate of 500 sccm so that the pressure of the gas atmosphere in the reaction chamber 12 is 0.3 Torr.
In addition, the electrode interval is set to 35 mm, and 35 W of electric power is supplied from the high frequency power source 19 to continue the glow discharge at the time of forming the gate insulating layer on the electrode 14 without stopping. At this time, it is appropriate that the discharge during film formation is 5 seconds or more. By introducing a large amount of H ₂ gas in this way, the reaction chamber 12
By setting the pressure of the gas atmosphere inside to 0.3 Torr, the influence of the residual gas at the time of forming the gate insulating layer can be removed. Further, the discharge can be stably maintained by setting the electrode interval to a large value of 35 mm.

Next, H ₂ gas was introduced at a flow rate of 500 sccm to adjust the pressure of the gas atmosphere in the reaction chamber 12 to 2 To.
In addition to rr, the electrode interval was set to 28 mm, and 50 W of power was supplied from the high frequency power supply 19 to continue glow discharge. Then, SiH ₄ gas was introduced at a flow rate of 30 sccm, the electrode interval was changed to 26 mm, and the film thickness was 0.0
A 5 μm a-Si film is formed. In this case, the continuous discharge of H ₂ plasma makes it possible to stably maintain the discharge until the a-Si film and the film formation.

By the way, in this way, the interval between the high-frequency electrode 13 and the ground electrode 14 is continuously changed (changed in multiple steps).
Then, as in Example 1, depending on the type of gas to be introduced and the pressure of the gas atmosphere in the reaction chamber, the plasma discharge can be stably continued without stopping, and the gate insulating layer 3 and the semiconductor layer 4 The defect density near the interface and near the interface between the semiconductor layer 4 and the semiconductor protective layer 5 can be reduced.

That is, the high frequency electrode 13 and the ground electrode 14
By continuously changing (in multiple steps) the distance between and, the electrode spacing can be changed depending on the type of gas to be introduced and the pressure of the gas atmosphere in the reaction chamber, for example when the pressure of the gas atmosphere in the reaction chamber is high. Is narrowed and widened when it is low to control the process condition, so that the S of the gate insulating layer 3 is reduced.
The defect density near the interface between the gate insulating layer 3 and the semiconductor layer 4 can be reduced by forming the iN _x film and the a-Si film 4a of the semiconductor layer 4 under optimum conditions.

Thereby, the T produced by the above method is
When an active matrix type liquid crystal display device is assembled and operated by a normal process using a liquid crystal display substrate having FT, a TFT having good switching characteristics is obtained.
I was able to

As described above, the continuous discharge is a means for continuously discharging the gate insulating layer 3 to the semiconductor layer 4. However, if this discharge is too long, the surface of the gate insulating layer 3 and the surface of the semiconductor layer 4 are deteriorated due to the chemical action of H ₂ plasma, and in some cases, such problems as film swelling and film peeling occur. Therefore, it is preferable that the discharge is 3 to 20 seconds, which is stable and the influence on the surface can be ignored.

Example 3. FIG. 6 shows a TFT having a positive staggered structure according to the third embodiment. This TFT has three insulating substrates 1 made of glass (for example, Corning 7059).
Plasma CVD by glow discharge by heating to 50 ° C. and introducing a gas consisting of SiH ₄ and nitrous oxide (N ₂ O).
By the method, an undercoat film 21 made of SiO ₂ and having a film thickness of 0.5 μm is formed.

Next, an ITO film having a film thickness of 0.1 μm for forming the pixel electrode 10 and a metal film made of Mo—W are formed by a sputtering method and etched by a photolithography method to form a source having a predetermined shape. The electrode 7 and the drain electrode 8 are formed.

Next, the insulating substrate 1 is heated to 350 ° C., a semiconductor layer forming gas composed of SiH ₄ and H ₂ is introduced, and a 0.1 μm-thick a-Si film is formed by plasma CVD.
The film 22 is formed. After the film formation, while maintaining the glow discharge at the time of forming the a-Si film 22, the introduction of SiH ₄ gas is stopped, and the introduction gas is changed from the a-Si film forming gas to H ₂ or H.
Switch to e or N ₂ gas to sustain the discharge and
H ₄ gas is introduced to form a gate insulating layer 3 made of a SiN _x film having a thickness of 0.02 μm. Then, the introduction of SiH ₄ gas was stopped, and SiH ₄ and N ₂ O gas were introduced while continuing the discharge by N ₂ gas to obtain a film thickness of 0.02 μm.
The SiON film of is formed. Then, the introduction of SiH ₄ and N ₂ O gas is stopped, and the SiH ₄ and NH ₃ guys are introduced while continuing the discharge with only N ₂ gas to obtain a film thickness of 0.4 μm.
A mN SiN _x film is formed.

Next, the insulating substrate 1 was sputtered on the insulating substrate 1 with a thickness of 0.3 μm of aluminum (Al) and 0.1.
A metal film made of a Mo film of 2 μm is formed, and the metal film and the gate insulating layer 3 are chemically dry etched by a photolithography method to form a gate electrode 2 having a predetermined shape together with the gate line. A-
The Si / SiN _x / SiON structure portion is exposed. At this time, using a fluorine-based gas, only the upper SiN _x film was etched to expose the SiON film. By leaving the a-Si / SiN _x / SiON structure in this way, laser annealing becomes easy.

Further, using the gate electrode 2 as a mask,
Doping the a-Si film with P ions. In this ion doping, PH ₃ gas diluted to 5% with H ₂ is decomposed by plasma, and the generated ion species are collectively accelerated by an electric field without mass separation and implanted into an a-Si film. It is done by The doping amount at this time is 3 ×
The acceleration voltage was 60 kV at 10 ¹⁵ cm ^-2 .

Next, from the top of the insulating substrate 1, a wavelength of 30
Irradiation with a XeCl excimer laser with 8 nm and energy density of 70 mJ. Other examples of this irradiation laser include Ar
Excimer laser such as F, KrF, XeF, and YA
A G laser, an Ar laser, or the like can also be used. In this case, the gate electrode 2 serves as a mask, and only the a-Si film in the P-ion-doped portion is crystallized. In this way, a low resistance N-type polycrystalline silicon film is formed.
Then, this N-type polycrystalline silicon film is etched by a photolithography method to form a source region 23 and a drain region 24.

After that, plasma CV is formed on the insulating substrate 1.
An insulating protective layer 9 made of a SiN _x film is formed by the D method,
Etching is performed by a photolithography method to remove the insulating protective layer on the peripheral electrodes and the pixel electrodes 10. Further, the metal film made of Mo-W on the pixel electrode 10 is removed.

When an active matrix liquid crystal display device was assembled by a known method using the liquid crystal display substrate having the TFT manufactured as described above, a liquid crystal display device having good switching characteristics could be obtained.

Example 4. FIG. 7 shows the configuration of a liquid crystal display device (LCD) using the above-mentioned TFT as a switch element. This liquid crystal display device includes an active element substrate 26 and a counter substrate 27 that faces the active element substrate 26 with a predetermined distance.
And a liquid crystal 28 filled between the substrates 26 and 27.

The active element substrate 26 is formed on the main surface of the transparent insulating substrate 1 made of glass, which faces the counter substrate 27, as shown in FIG.
The gate electrode 2, the gate insulating layer 3, the semiconductor layer 4,
A TFT 30 including a semiconductor protective layer 5, an n-type semiconductor layer 6, a source electrode 7, a drain electrode 8 and an insulating protective layer 9, a pixel electrode 10 and the like are formed. Further, an alignment film 31 made of, for example, a low temperature cure type polyimide resin is provided on the TFT 30 and the pixel electrode 10. Further, the outer main surface of the transparent insulating substrate 1 (opposite main surface)
A polarizing plate 32 is attached to the. On the other hand, the counter substrate 27 is
A common electrode 34 made of ITO is formed on the main surface of the transparent insulating substrate 33 made of glass, which faces the active element substrate 26. On the common electrode 34, similar to the active element substrate 26, for example, a low temperature cure type polyimide resin is used. An alignment film 35 is provided. Furthermore, on this counter substrate 27,
A polarizing plate 36 is attached to the outer principal surface (opposite principal surface) of the transparent insulating substrate 33. The alignment films 31 and 35 of the substrates 26 and 27 are respectively rubbed in a predetermined direction with a cloth or the like to be subjected to a rubbing treatment in which the alignment axes are approximately 90 °.

The alignment film 3 of each of the substrates 26 and 27 is
The rubbing directions of 1 and 35 are set such that the good viewing angle direction is the front direction. In addition, this liquid crystal display element,
Illumination is performed from the outside of the main surface of either one of the active element substrate 26 and the counter substrate 27.

With this structure, it is possible to manufacture a liquid crystal display element having excellent TFT characteristics, stability, insulation and the like with a good yield.

[0057]

As described above, according to the present invention, the defect density in the vicinity of the interface between the gate insulating layer and the semiconductor layer or in the vicinity of the interface between the semiconductor layer and the semiconductor protective layer can be reduced, and further film swelling or film peeling can be achieved. Can be prevented, and a TFT having better characteristics than a conventional TFT can be obtained.

The TFT manufactured by this method can be applied to a liquid crystal display device to form a highly reliable liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a thin film transistor according to a first embodiment of the present invention.

2A to 2E are views for explaining the manufacturing method thereof.

FIG. 3 is a diagram showing a main configuration of a plasma CVD apparatus used for manufacturing the thin film transistor.

FIG. 4 is a diagram showing a configuration of a thin film transistor according to a second embodiment of the present invention.

5A to 5D are views for explaining the manufacturing method thereof.

FIG. 6 is a diagram showing a configuration of a thin film transistor according to Example 3 of the present invention.

FIG. 7 is a diagram showing a structure of a liquid crystal display device using the thin film transistor according to the first embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Glass insulating substrate 2 ... Gate electrode 3 ... Gate insulating layer 4 ... Semiconductor layer 5 ... Semiconductor protective layer 6 ... N-type semiconductor layer 7 ... Source electrode 8 ... Drain electrode 9 ... Insulating protective layer 10 ... Pixel electrode 12 ... Reaction chamber 13 ... High-frequency electrode 14 ... Ground electrode 16 ... Vacuum exhaust device 17 ... Gas introduction device 26 ... Active element substrate 27 ... Counter substrate 22 28 ... Liquid crystal 30 ... TFT 31 ... Alignment film 32 ... Polarizing plate 33 ... Glass insulating substrate 34 ... Common Electrode 35 ... Alignment film 36 ... Polarizing plate

Claims (17)

[Claims] 1. A method of manufacturing a thin film transistor, wherein the gate insulating layer and the semiconductor layer of a thin film transistor having at least a gate insulating layer and a semiconductor layer laminated on the gate insulating layer are laminated by plasma CVD. When the semiconductor layer is laminated on the gate insulating layer, the gate insulating layer is formed, the interval between discharge electrodes is changed while maintaining plasma discharge, and then the semiconductor layer is formed. And a method for manufacturing a thin film transistor. 2. The method of manufacturing a thin film transistor according to claim 1, wherein when the semiconductor layer is laminated on the gate insulating layer, the gate insulating layer is formed and then H ₂ gas plasma discharge is maintained. By changing the distance between the discharge electrodes,
Then, a method of manufacturing a thin film transistor, characterized in that the semiconductor layer is formed. 3. The method of manufacturing a thin film transistor according to claim 1, wherein when a semiconductor layer is laminated and formed on a gate insulating layer, a plasma containing a non-film forming gas as a main component is formed after forming the gate insulating layer. A method of manufacturing a thin film transistor, characterized in that a gap between discharge electrodes is changed while maintaining discharge, and then the semiconductor layer is formed. 4. The method of manufacturing a thin film transistor according to claim 1, wherein when the semiconductor layer is laminated on the gate insulating layer, the gate insulating layer is formed and then H ₂ , He,
Manufacture of a thin film transistor, characterized in that the distance between discharge electrodes is changed while maintaining plasma discharge containing at least one of Ar, N ₂ and NH ₃ gases as a main component, and then the semiconductor layer is formed. Method. 5. The method of manufacturing a thin film transistor according to claim 1, wherein when the semiconductor layer is laminated and formed on the gate insulating layer, the gate insulating layer is formed and then the pressure is applied when the gate insulating layer is formed. Also, a method for manufacturing a thin film transistor, characterized in that the interval between the discharge electrodes is changed while a low-voltage discharge period is provided and the plasma discharge is maintained, and then the semiconductor layer is formed. 6. A plasma CV is applied to the semiconductor layer and the semiconductor protective layer of a thin film transistor having at least a semiconductor layer and a semiconductor protective layer formed on the semiconductor layer.
In the method for manufacturing a thin film transistor in which the semiconductor protective layer is laminated on the semiconductor layer in the method of manufacturing a thin film transistor by the method D, the distance between the discharge electrodes is changed while maintaining plasma discharge after forming the semiconductor layer. And then forming the semiconductor protective layer. 7. The method of manufacturing a thin film transistor according to claim 6, wherein when the semiconductor protective layer is laminated on the semiconductor layer, the semiconductor layer is formed and then discharged while maintaining plasma discharge of H ₂ gas. A method of manufacturing a thin film transistor, which comprises changing the distance between electrodes and then forming the semiconductor protective layer. 8. The method of manufacturing a thin film transistor according to claim 6, wherein when the semiconductor protective layer is laminated on the semiconductor layer, the semiconductor layer is formed, and then plasma discharge containing a non-film forming gas as a main component. A method of manufacturing a thin film transistor, characterized in that the distance between the discharge electrodes is changed while maintaining the above, and then the semiconductor protective layer is formed. 9. The method of manufacturing a thin film transistor according to claim 6, wherein when the semiconductor protective layer is laminated on the semiconductor layer, the semiconductor layer is formed and then H ₂ , He, A is formed.
A thin film transistor, characterized in that the interval between the discharge electrodes is changed while maintaining plasma discharge containing at least one of r, N ₂ and NH ₃ gas as a main component, and then the semiconductor protective layer is formed. Production method. 10. The method of manufacturing a thin film transistor according to claim 6, wherein when the semiconductor protective layer is laminated and formed on the semiconductor layer, the pressure after forming the semiconductor layer is lower than the pressure at the time of forming the semiconductor layer. The method for manufacturing a thin film transistor, characterized in that the interval between the discharge electrodes is changed while maintaining the discharge period and the plasma discharge is maintained, and then the semiconductor protective layer is formed. 11. Plasma C is applied to the semiconductor layer and the gate insulating layer of a thin film transistor having at least a semiconductor layer and a gate insulating layer formed on the semiconductor layer.
In a method of manufacturing a thin film transistor in which a stacked film is formed by a VD method, when the gate insulating layer is stacked and formed on the semiconductor layer, a gap between discharge electrodes is changed while maintaining plasma discharge after forming the semiconductor layer. And then forming the gate insulating layer. 12. The method of manufacturing a thin film transistor according to claim 11, wherein when the gate insulating layer is laminated on the semiconductor layer, the semiconductor layer is formed and then discharged while maintaining a plasma discharge of H ₂ gas. Change the electrode spacing,
Then, a method for manufacturing a thin film transistor, characterized in that the gate insulating layer is formed. 13. The method of manufacturing a thin film transistor according to claim 11, wherein when the gate insulating layer is laminated on the semiconductor layer, the semiconductor layer is formed and then a plasma discharge containing a non-film forming gas as a main component. A method for manufacturing a thin film transistor, characterized in that the distance between the discharge electrodes is changed while maintaining the above condition, and then the gate insulating layer is formed. 14. The method of manufacturing a thin film transistor according to claim 11, wherein when the gate insulating layer is laminated on the semiconductor layer, the semiconductor layer is formed and then H ₂ , He,
A thin film transistor, characterized in that an interval between discharge electrodes is changed while maintaining a plasma discharge containing at least one of Ar, N ₂ and NH ₃ gases as a main component, and then the gate insulating layer is formed. Production method. 15. The method of manufacturing a thin film transistor according to claim 11, wherein when the gate insulating layer is laminated and formed on the semiconductor layer, the pressure after forming the semiconductor layer is lower than the pressure at the time of forming the semiconductor layer. Of the discharge electrode and changing the interval between the discharge electrodes while maintaining the plasma discharge, and thereafter forming the gate insulating layer. 16. A thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1. Description: 17. A liquid crystal display device using the thin film transistor according to claim 16 as a switch element.