JPH0818032A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable a large amount of current to flow by reducing leakage current with a high withstand voltage, improving breaking capacity, achieving fine machining with a high yield, and reducing ON voltage. CONSTITUTION:P<+> layer 12 is formed on the lower surface of N-substrate 10. A recessed part 40 is provided on the upper surface of the N-substrate 10. Then, P<+> side-part gate region 32 and a bottom part gate region 34 are formed at a side part 42 and a bottom part 44 of the recessed part 40, respectively. The impurities of N<-> substrates 10 and 20 are eliminated by washing RCA and the substrates are washed in pure water and are subjected to spinner drying. Then, while a projecting part 14 of the N<-> substrate 10 and a lower surface 24 of N<-> substrate 20 are in contact, the N<-> substrate 10 and the N<-> substrate 20 are joined by heating at 800 deg.C in hydrogen atmosphere.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to an electrostatic induction (SI) thyristor and its manufacturing method.

[0002]

26 and 27 are perspective sectional views for explaining a conventional static induction thyristor devised by the present inventor and a method for manufacturing the same.

A conventional static induction thyristor 100 of this type.
Was manufactured as follows.

That is, first,
Each surface is mirror-polished N ^-Substrates 10 and 2
Prepare 0.

[0005] Next, as shown in FIG. 26, N ^- substrate 10
A P ⁺ layer 12 is formed on the lower surface of the P by an impurity diffusion method. Next, the recess 40 capable of accommodating the gate electrode 90 is provided on the upper surface of the N ⁻ substrate 10 by photolithography. Next, the P ⁺ gate region 130 is selectively formed in the bottom portion 44 of the recess 40 by selectively diffusing the P-type impurity. Next, a gate electrode 90 made of tungsten is selectively formed in the recess 40 on the P ⁺ gate region 130 by photolithography.

On the other hand, the N ⁺ layer 22 is formed on the upper surface of the N ⁻ substrate 20 by the impurity diffusion method.

Next, with a sulfuric acid + hydrogen peroxide aqueous solution,
The N ⁻ substrates 10 and 20 are ultrasonically cleaned to remove organic substances and metals.

Next, the N ^- substrates 10 and 20 are washed with pure water and spinner dried at room temperature.

Next, as shown in FIG. 27, the convex portion 14 of the N ⁻ substrate 10 and the lower surface 24 of the N ⁻ substrate 20 between the concave portions 40 are brought into contact with each other and heated at 800 ° C. in a hydrogen atmosphere. Thus, the N ⁻ substrate 10 and the N ⁻ substrate 20 are bonded.

Next, the P formed on the lower surface of the N ⁻ substrate 10 is formed.
^An anode electrode 60 and a cathode electrode 70 are formed on the lower surface of the ⁺ layer 12 and the upper surface of the N ⁺ layer 22 formed on the upper surface of the N ⁻ substrate 20, respectively.

In the electrostatic induction thyristor 100 thus formed, the P ⁺ layer 12 functions as the anode, the N ⁺ layer 22 functions as the cathode, and the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as the N base 50. P ⁺ gate region 13
The 0 and the gate electrode 90 function as a gate that controls the anode current flowing between the anode electrode 60 and the cathode electrode 70.

In this conventional electrostatic induction thyristor 100, the N base 50 in which the P ⁺ gate region 130 is embedded is formed by the joining of the N ⁻ substrate 10 and the N ⁻ substrate 20, so that a uniform and high quality crystal is formed. It is possible to obtain the N base 50 having the property. Further, N after forming the gate region 130 of the P ^{+ -} as in the case of a layer is epitaxially grown, the control of anode current conductivity type N base 50 between the gate region 130 of P ⁺ is will change the P-type non There is no such thing as possible.

Further, P⁺On the gate area 130 of
Since the gate electrode 90 made of gustene is provided,
The maximum lateral breaking current is increased by reducing the lateral resistance
I can do it. The gate electrode 90 is N^-Substrate 10 and
And N^-Before joining the substrates 20, N^-In the recess 40 of the substrate 10
Since it is already housed in the gate electrode 9
Even if 0 is set, N⁺Layers 22 and N^-substrate
A groove with a large aspect ratio is provided in 20, and the game is placed in this groove.
It is not necessary to form the contact electrode 90, and N ⁺Layer 22
And N^-The substrate 20 is finely divided by the groove
High resistance will not occur.

Further, since the recess 40 provided on the upper surface of the N ⁻ substrate 10 can accommodate the gate electrode 90,
It does not take too long to form.

Further, the gate electrode 90 is composed of the N ⁻ substrate 10
Since it is accommodated in the recess 40 provided on the upper surface of the
^- substrate 20 ^- N that is joined to the convex portion 14 of the upper surface of the substrate 10
It is not necessary to provide a recess in the lower surface 24 of the
May be planar. Therefore, when the convex portion 14 on the upper surface of the N ⁻ substrate 10 and the lower surface 24 of the N ⁻ substrate 20 are joined together, it is not necessary to perform special alignment, and the manufacturing is facilitated.

The following publicly known documents are listed below as examples of conventional semiconductor device technology. <Patent-related literature> -Patent No. 1131903-Japanese Patent Publication No. 1-26187 <General literature> -Junichi Nishizawa "Development of high-power electrostatic induction transistor" Research report by the Ministry of International Trade and Industry, Agency of Industrial Science and Technology Research Grant 196
9 years ・ Junichi Nishizawa “High power vertical junction FE with triode characteristics”
T ”Nikkei Electronics September 27, 1971 P.
P. 50-61 ・ J. Nishizawa, T. Terasaki and J. Shibata "Field
-Effect Transistorversus Analog Transistor (Static
Inductial Transistor) "IEEE Transon Electron Devi
ces, Vel.ED-22 (4), 185 (1975) ・ J. Nishizawa and K. Nakamura, Rev. de Physiquee
Appliquee, T13,725 (1978) ・ J. Nishizawa and Y. Otsubo, Tech. Dig. 1980 IED
M, 658 (1980) ・ Junichi Nishizawa, Tadahiro Ohmi, Ken Shigeru, Kaoru Motoya, IEICE Technical Report, ED81-84 (1981)

[0017]

As described above, the electrostatic induction thyristor devised by the present inventor and the manufacturing method thereof have very excellent characteristics. However, in this conventional electrostatic induction thyristor 100, the P ⁺ gate region 130 was only provided at the bottom portion 44 of the recess 40.

Therefore, when turned off, the P ⁺ gate region 130 is formed.
The thickness of the depletion layer extending from the anode current direction is small,
As a result, there were problems in terms of breakdown voltage and leakage current.

Further, since the thickness of the depletion layer extending from the P ⁺ gate region 130 in the anode current direction is small at the time of OFF, the interval between the gate regions 130 is narrowed in order to obtain a predetermined OFF characteristic. It was necessary, and for that purpose, the space between the recesses 40 had to be narrowed.
As a result, there is a problem that the yield is low when the recess 40 is finely processed on the upper surface of the N ⁻ substrate 10.

When the distance between the recesses 40 is narrowed in this manner, the cross-sectional area of the N ⁻ substrate 10 between the recesses 40 is reduced and the resistance of the portion is increased, resulting in a higher on-voltage. There was also the problem that a large current could not flow.

A general object of the present invention is to provide a semiconductor device such as an electrostatic induction thyristor having a high breakdown voltage, a small leakage current, and an excellent breaking ability, and a method of manufacturing the same.

A main object of the present invention is to provide a semiconductor device such as an electrostatic induction thyristor which can improve the yield in microfabrication and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device such as an electrostatic induction thyristor capable of lowering an on-voltage and allowing a large current to flow, and a method of manufacturing the same.

[0024]

According to the present invention, a gate for controlling a current flowing between the anode electrode and the cathode electrode is provided in a semiconductor substrate provided between the anode electrode and the cathode electrode. In the semiconductor device, a cavity is provided in the semiconductor substrate, and a gate region is provided in a region of the semiconductor substrate exposed on a side portion of the cavity.

Preferably, the side portion of the cavity is provided substantially parallel to the direction of the current flowing between the anode electrode and the cathode electrode.

Further, it is preferable that a gate region is provided in a region exposed at the bottom of the cavity of the semiconductor substrate.

Furthermore, a gate region may be provided in a region exposed to the ceiling of the cavity of the semiconductor substrate.

It is preferable that an insulating film is provided in the cavity so as to cover the pn junction exposed in the cavity among the pn junctions formed between the gate region and the semiconductor substrate.

It is also preferable that an insulating film is provided in the cavity so as to cover the entire surface of the region exposed in the cavity of the semiconductor substrate.

Preferably, a gate electrode made of a good conductor electrically connected to the gate region is further provided in the cavity of the semiconductor substrate.

It is more preferable to provide an insulating film in the cavity so as to cover the gate electrode.

Further, preferably, the semiconductor substrate has a first semiconductor layer of one conductivity type, a second semiconductor layer of another conductivity type provided on the first semiconductor layer, and the second semiconductor layer. And a third semiconductor layer of the other conductivity type having a higher impurity concentration than that of the second semiconductor layer, wherein one of the anode electrode and the cathode electrode is the first semiconductor. Is provided in electrical connection with a layer, the other of the anode electrode and the cathode electrode is provided in electrical connection with the third semiconductor layer, and the gate region is the one conductivity type semiconductor, The cavity and the gate region are provided in the second semiconductor layer.

Furthermore, according to the present invention, the semiconductor substrate includes a first semiconductor layer of one conductivity type and a second semiconductor layer of another conductivity type provided on the first semiconductor layer. A third semiconductor layer provided between the first and second semiconductor layers and having a high impurity concentration, wherein one of the anode electrode and the cathode electrode is electrically connected to the first semiconductor layer. The other one of the anode electrode and the cathode electrode is provided so as to be electrically connected to the second semiconductor layer, and a plurality of the cavities are provided in correspondence with the number of the third semiconductors. A high impurity concentration region is provided between the cavities.

Furthermore, the present invention provides a step of preparing first and second semiconductor substrates of one conductivity type, and the first semiconductor substrate.
A step of forming a recess on one main surface of the semiconductor substrate, and
An impurity-doped gate region of another conductivity type in a region exposed at least on the side of the recess of the semiconductor substrate, exposing the one main surface of the first semiconductor substrate between the gate regions, A step of selectively providing, and the one main surface of the first semiconductor substrate exposed between the gate regions,
And a step of joining the one main surface of the second semiconductor substrate.

In this method, preferably, the side portion of the recess is provided substantially perpendicular to the one main surface of the first semiconductor substrate.

Preferably, another conductive type gate region doped with an impurity is formed in a region exposed at least on the side of the recess of the first semiconductor substrate, and the first semiconductor is provided between the gate regions. In the step of exposing the one main surface of the substrate and selectively providing it, the gate region of another conductivity type in which impurities are doped in the regions exposed on the side and bottom of the recess of the first semiconductor substrate. Is a step of exposing and selectively providing the one main surface of the first semiconductor substrate between the gate regions.

Furthermore, according to the present invention, the steps of preparing first and second semiconductor substrates of one conductivity type are respectively provided, and a recess is formed on one main surface of the first semiconductor substrate, and the one main space is provided between the recesses. Exposing a surface and selectively providing the surface; joining the one main surface of the first semiconductor substrate exposed between the recesses and the one main surface of the second semiconductor substrate; After bonding, the region exposed on the side and the bottom of the recess of the first semiconductor substrate and the region of the one main surface of the second semiconductor substrate exposed on the recess are doped with impurities. And a step of providing a conductive type gate region.

In this method, preferably, after providing the gate region, an insulating film is provided in the recess so as to cover the gate region, and then the first semiconductor substrate of the first semiconductor substrate exposed between the gate regions. The one main surface and the one main surface of the second semiconductor substrate are bonded.

Furthermore, preferably, after joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate, side and bottom portions of the recess and the second semiconductor are formed. An oxide film is provided on the one main surface of the substrate and in the region exposed to the recess.

Further, before joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate, preferably, the gate region is electrically connected to the gate region. A gate electrode made of a good conductor is provided.

More preferably, before joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate, an insulating film is formed in the recess to cover the gate electrode. Set up.

Further, preferably, after joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate, a side portion of the recess is the first semiconductor substrate. An oxide film is provided so as to cover the region exposed to the bottom, the region exposed to the recess on the one main surface of the second semiconductor substrate, and the gate electrode.

One of the other main surface of the first semiconductor substrate opposite to the one main surface and the other main surface of the second semiconductor substrate opposite to the one main surface. And a step of providing the other conductive type first semiconductor layer, and one of the anode electrode and the cathode electrode is electrically connected to the other main surface of the first semiconductor substrate or the first semiconductor layer. And a step of electrically connecting the other of the anode electrode and the cathode electrode to the other main surface of the second semiconductor substrate or the second semiconductor layer. Have.

[0044]

In the semiconductor device of the present invention, the cavity is provided in the semiconductor substrate, and the gate region is provided in the region exposed to the side of the cavity of the semiconductor substrate. Since the anode current flows along the side portion of the cavity of the semiconductor substrate, by providing the gate region along the side portion of the cavity as described above, the length of the depletion layer extending from the gate region in the anode current direction when the gate region is off is increased. Can be large. Therefore, the breakdown voltage at the time of off can be increased, the leakage current can be reduced, and a semiconductor device having an excellent breaking capability can be obtained.

Further, as described above, since the thickness of the depletion layer extending from the gate region in the anode current direction can be increased at the time of turning off, a predetermined off characteristic can be obtained without narrowing the interval between the gate regions. Therefore, it is not necessary to narrow the space between the cavities of the semiconductor substrate. As a result, the yield at the time of finely processing the cavities in the semiconductor substrate can be improved.

Further, since it is not necessary to narrow the space between the cavities in this way, it is also suppressed that the cross-sectional area of the semiconductor substrate between the cavities is reduced, and the resistance of the semiconductor substrate between the cavities is lowered, and as a result, the ON-state is turned on. The voltage drops and a large current can be achieved.

Furthermore, by providing the side portions of the cavity substantially parallel to the direction of the current flowing between the anode electrode and the cathode electrode, the depletion layer can be uniformly extended over the entire channel length between the gate regions at the time of off. it can.
Therefore, the breakdown voltage at the time of off can be further increased, the leakage current can be further reduced, and a semiconductor device having an excellent breaking capability can be obtained.

Further, by providing the side portions of the cavity substantially parallel to the direction of the current flowing between the anode electrode and the cathode electrode in this way, more excellent off characteristics can be obtained, so that the semiconductor substrate of the semiconductor substrate can be obtained. The spacing between the cavities can be wider. As a result, the yield at the time of finely processing the cavities in the semiconductor substrate can be further improved.

Further, since the space between the cavities can be made wider in this way, the cross-sectional area of the semiconductor substrate between the cavities can be made wider, and the resistance of the semiconductor substrate between the cavities can be made smaller. The voltage further decreases, and a larger current can be achieved.

Further, by providing the gate region in the region exposed at the bottom of the cavity of the semiconductor substrate and / or providing the gate region in the region exposed at the ceiling of the cavity of the semiconductor substrate, the lateral resistance of the gate is increased. The maximum breaking current can be increased by decreasing the frequency, and the frequency can be increased. Thus, the gate resistance can be reduced by providing the gate region in the region exposed on the side of the cavity and the region exposed on the bottom and / or the ceiling of the cavity. as a result,
The gate volume can be reduced to increase the controlled current, and the capacity can be increased.

By providing an insulating film in the cavity so as to cover the pn junction exposed in the cavity of the pn junction formed between the gate region and the semiconductor substrate, the breakdown voltage between the gate and the cathode can be improved. it can. Further, by providing the insulating film in the cavity so as to cover the entire surface of the region exposed in the cavity of the semiconductor substrate, the breakdown voltage between the gate and the cathode can be more reliably improved.

Further, by further providing the gate electrode made of a good conductor electrically connected to the gate region in the cavity of the semiconductor substrate, the lateral resistance of the gate can be reduced and the maximum breaking current can be increased. Carrier extraction current can be increased, and faster switching becomes possible.

Further, in the method for manufacturing a semiconductor device of the present invention, first conductivity type first and second semiconductor substrates are prepared respectively, and a concave portion is provided on one main surface of the first semiconductor substrate.
Impurity-doped gate regions of another conductivity type are exposed in at least a region of the first semiconductor substrate exposed to the side of the recess to expose the one main surface of the first semiconductor substrate between the gate regions. The one main surface of the first semiconductor substrate exposed between the gate regions and the one main surface of the second semiconductor substrate are bonded to each other.

As described above, by providing the gate region in the region of the first semiconductor substrate which is exposed at the side of the recess provided in the one main surface of the first semiconductor substrate, the depletion layer extending from the gate region when off is formed. The length of the anode current direction can be increased. Therefore, the breakdown voltage at the time of off can be increased, the leakage current can be reduced, and a semiconductor device having an excellent breaking capability can be manufactured.

Further, since the thickness of the depletion layer extending from the gate region in the anode current direction can be increased when the gate region is off, a predetermined off characteristic can be obtained without narrowing the interval between the gate regions. Therefore, it is not necessary to narrow the interval between the concave portions provided on the one main surface of the first semiconductor substrate. As a result, the yield at the time of finely processing the concave portion on the one main surface of the first semiconductor substrate can be improved.

Further, since it is not necessary to narrow the interval between the recesses in this way, it is possible to suppress the reduction in the cross-sectional area of the first semiconductor substrate between the recesses, and the resistance of the first semiconductor substrate between the recesses is reduced. As a result, the on-voltage is lowered and a large current can be achieved.

Further, in the method of the present invention, the base on which the gate region is provided is formed by joining the first semiconductor substrate and the second semiconductor substrate without performing epitaxial growth, so that a uniform and high-quality crystal is formed. It is possible to obtain a base having good properties. Further, for example, P ⁺ N after forming the gate region of ^- as in the case of a layer of epitaxially grown, for example, P ⁺ N between the gate regions of the
There is no possibility that the conductivity type of the base is changed to the P type and the control of the anode current becomes impossible. Further, high-concentration doping of the gate region is possible.

Epitaxial growth requires a high temperature of 1100 ° C. or higher, and impurities are very easily diffused.
If it is heated to 00 ° C. or higher, bonding is possible and impurities hardly diffuse. Although this joining can be performed without applying pressure, joining can be performed at a lower temperature by joining under pressure.

Furthermore, by providing the side portion of the recess substantially perpendicular to the one main surface of the first semiconductor substrate, the side portion of the recess is substantially parallel to the direction of the current flowing between the anode electrode and the cathode electrode. Therefore, the depletion layer can be uniformly extended over the entire length of the channel between the gate regions when turned off. Therefore, the breakdown voltage at the time of off can be further increased, the leakage current can be further reduced, and a semiconductor device having an excellent breaking capability can be manufactured.

Further, by providing the side portion of the concave portion substantially perpendicular to the one main surface of the first semiconductor substrate in this manner, more excellent off characteristics can be obtained, so that the concave portion of the first semiconductor substrate can be obtained. The distance between them can be made wider. As a result, the yield at the time of finely processing the concave portion on the one main surface of the first semiconductor substrate can be further improved.

Further, since the distance between the recesses can be made wider as described above, the cross-sectional area of the first semiconductor substrate between the recesses can be made wider and the resistance of the first semiconductor substrate between the recesses can be made smaller. As a result, the on-voltage of the semiconductor device manufactured by this manufacturing method is further lowered, and a larger current can be achieved.

By providing the gate region in the region exposed at the bottom of the cavity of the semiconductor substrate, the lateral resistance of the gate is reduced, the maximum breaking current can be increased, and the frequency can be increased. In this way, the gate resistance can be reduced by providing the gate region in the regions exposed at the side and bottom of the cavity of the first semiconductor substrate. As a result, the gate volume can be reduced and the controlled current can be increased, and the capacity can be increased.

Further, first conductivity type first and second semiconductor substrates are prepared respectively, and recesses are formed in one main surface of the first semiconductor substrate, and one main surface is exposed between the recesses to selectively expose the main surfaces. Provided,
The one main surface of the first semiconductor substrate exposed between the recesses and the one main surface of the second semiconductor substrate are joined together, and after joining, the regions exposed on the side and bottom of the recess of the first semiconductor substrate, and By providing a gate region of another conductivity type doped with an impurity in a region which is one main surface of the second semiconductor substrate and is exposed in the recess, the gate region is formed on the side, bottom and ceiling of the recess. , The lateral resistance of the gate becomes smaller, the maximum breaking current can be further increased, and the frequency can be further increased.

Further, after the gate region is provided, an insulating film is provided in the recess so as to cover the gate region, and thereafter, the one main surface of the first semiconductor substrate exposed between the gate regions and the second semiconductor. Impurities can be prevented from diffusing from the gate region to the bonding surface when bonding to the main surface of the substrate. As a result, the on-voltage is reduced and the breakdown voltage between the gate and the cathode is improved.

Further, one main surface of the first semiconductor substrate and the second main surface
After bonding the main surface of the semiconductor substrate with the first main surface of the semiconductor substrate, an oxide film is provided on the side and bottom portions of the recess and in the area of the main surface of the second semiconductor substrate that is exposed in the recess. The pn junction formed between the semiconductor substrate and the second semiconductor substrate can be passivated, and as a result, the breakdown voltage between the gate and the cathode is improved.

Before the main surface of the first semiconductor substrate and the main surface of the second semiconductor substrate are bonded together, a gate region and a gate region are formed in a recess provided in the main surface of the first semiconductor substrate. By providing a gate electrode made of a good conductor that is electrically connected, the lateral resistance of the gate can be reduced and the maximum breaking current can be increased, and the carrier extraction current can be increased, resulting in faster switching. It will be possible.

Further, since the gate electrode is already provided in the concave portion of the first semiconductor substrate before joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate,
Even when the gate electrode is provided in the semiconductor substrate as described above, it is not necessary to form a groove having a large aspect ratio in the semiconductor substrate from the outside and form the gate electrode in the groove. As a result, the semiconductor substrate above the gate electrode is not finely divided by the groove to have a high resistance.

Further, since the recess provided on the one main surface of the first semiconductor substrate only needs to be able to accommodate the gate electrode, for example, even if the recess is formed by a dry etching method having a low etching rate, the formation thereof is possible. Never takes too long.

Further, since the gate electrode is provided in the recess provided in the one main surface of the first semiconductor substrate, the gate electrode of the second semiconductor substrate joined to the one main surface of the first semiconductor substrate is formed. It is not necessary to provide the concave portion on the one main surface, and the one main surface may be flat. Therefore, when the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate are bonded to each other, it is not necessary to perform special alignment, which facilitates manufacturing.

As the gate electrode, polycrystalline silicon doped with impurities, aluminum, and refractory metal such as tungsten are preferably used. If polycrystalline silicon or refractory metal is used for the gate electrode,
The thermal diffusion bonding of the first semiconductor substrate and the second semiconductor substrate can be performed at a higher temperature. As a result, the disorder of the crystal lattice at the bonding interface can be further reduced, and a good bonding interface can be obtained.

Before joining the main surface of the first semiconductor substrate and the main surface of the second semiconductor substrate, a gate electrode is formed in the recess provided in the main surface of the first semiconductor substrate. By providing the insulating film so as to cover, the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate can be kept clean at the time of bonding, and the one main surface of the first semiconductor substrate and the first main substrate can be kept clean. It is possible to obtain a better bond between the two main surfaces of the semiconductor substrate.

The insulating film covering the gate electrode is preferably formed by depositing an oxide film or the like by a chemical vapor deposition method (CVD method) when aluminum or refractory metal is used for the gate electrode. When polycrystalline silicon doped with impurities is used as the electrode, it may be formed by oxidizing polycrystalline silicon or may be formed by depositing an oxide film or the like by a CVD method.

In addition, after joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate, a region of the first semiconductor substrate exposed on the side and bottom of the recess, By providing an oxide film on the main surface of the semiconductor substrate and covering the region exposed in the recess and the gate electrode,
The pn junction between the gate region and the semiconductor substrate is passivated, and the breakdown voltage between the gate and the cathode is improved.

The oxide film is preferably formed by thermal oxidation. In that case, the gate electrode is
Polycrystalline silicon doped with impurities is preferably used.

When the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate are bonded to each other, the bonding surface has one conductivity type and is provided on the first semiconductor substrate. Is the first
The impurity concentration of the semiconductor substrate is higher than that of the second semiconductor substrate, and when provided in the second semiconductor substrate, a high-concentration semiconductor region having a higher impurity concentration than that of the second semiconductor substrate is formed to improve electrical connection. . The thickness of this high-concentration semiconductor region is several 1
It is preferably 0Å to several 100Å.

Further, after the step of preparing each of the first and second semiconductor substrates, there is a step of providing a plurality of high impurity concentration regions on one main surface of the first semiconductor substrate at predetermined intervals. Alternatively, a recess may be provided between the plurality of high impurity concentration regions that are separated from each other by a predetermined distance. Further, after the step of preparing each of the first and second semiconductor substrates, there may be a step of providing a plurality of high impurity concentration regions on one main surface of the second semiconductor substrate at a predetermined distance. . In this case, the plurality of high-impurity concentration regions are provided corresponding to one main surface exposed except the concave portion defined in the first semiconductor substrate.

With such a configuration or method, power consumption and heat generation are reduced.

Although only an electrostatic induction thyristor is described here as an example, the basic structure is an electrostatic induction transistor except the anode P emitter of the electrostatic induction thyristor. Therefore, those skilled in the art can easily replace the static induction thyristor in the following embodiments with the static induction transistor.

[0079]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

(First Embodiment) FIGS. 1 and 2 are perspective sectional views for explaining an electrostatic induction thyristor according to a first embodiment of the present invention and a method for manufacturing the same.

First, N ⁻ substrates 10 and 20 in which at least the surfaces to be bonded to each other are mirror-polished are prepared.

Next, as shown in FIG.^-Board 10
P on the bottom surface by the impurity diffusion method⁺Form the layer 12. Next
To N^-On the top surface of the substrate 10 by the photolithography method,
The recess 40 having a width of 30 μm and a depth of 20 μm by 50 μm.
Set up with a switch. The side portion 42 of the recess 40 is N^-Board 10
Is provided almost vertically on the upper surface of. Next, P-type impurities
By selectively diffusing boron, which is⁺Ge of
The cover area 30 is aligned with the sides 42 and bottom 44 of the recess 40.
Each exposed N^-Selectively formed in the region of the substrate 10.
It P formed in this way⁺Gate area 30
From the side gate region 32 and the bottom gate region 34
Be composed. In addition, the diffusion of boron is BBr₃+ O ₂Atmosphere
It was carried out in air at a temperature of 1050 to 1200 ° C. Also, this
When boron is diffused, the side portion 42 and the bottom portion of the recess 40 are
An oxide film is formed on 44, but it is not shown.

On the other hand, the N ⁺ layer 22 is formed on the upper surface of the N ⁻ substrate 20 by the impurity diffusion method.

Next, with an aqueous solution of sulfuric acid and hydrogen peroxide,
The N ⁻ substrates 10 and 20 are ultrasonically cleaned to remove organic substances and metals.

Next, the N ⁻ substrates 10 and 20 are washed with pure water, and spinner dried at room temperature.

Next, as shown in FIG.
^- kept in contact with the lower surface 24 of the substrate 20, in a hydrogen atmosphere by heating at 800 ° C., N ^{- -} protrusion 14 and the N substrate 10 to bond the substrate 20 ^- substrate 10 and N.

Next, P formed on the lower surface of the N ⁻ substrate 10
^An anode electrode 60 and a cathode electrode 70 are formed on the lower surface of the ⁺ layer 12 and the upper surface of the N ⁺ layer 22 formed on the upper surface of the N ⁻ substrate 20, respectively.

In the electrostatic induction thyristor 100 thus formed, the P ⁺ layer 12 functions as the anode, the N ⁺ layer 22 functions as the cathode, and the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as the N base 50. P ⁺ gate region 30
Functions as a gate that controls the anode current flowing between the anode electrode 60 and the cathode electrode 70. In the present embodiment, the concave portion 40 is provided on the upper surface of the N ⁻ substrate 10, and the concave portion 40 and the lower surface 24 of the N ⁻ substrate 20 make the N ⁻
A cavity is formed in the base 50. Further, in this embodiment, the side gate region 32 is provided in the region exposed to the side portion 42 of the recess 40 of the N ⁻ substrate 10. Since the anode current flows along the side portion 42 of the recess 40, by providing the side gate region 32 along the side portion 42 of the recess 40 in this manner, the anode current of the depletion layer extending from the gate region 30 at the time of OFF is formed. The length in the direction can be increased. Therefore, the breakdown voltage at the time of off can be increased, the leakage current can be reduced, and the electrostatic induction thyristor 100 excellent in the breaking ability can be obtained.

As described above, the gate region 3 is turned off when it is turned off.
Since the thickness of the depletion layer extending from 0 in the anode current direction can be increased, a predetermined off characteristic can be obtained without reducing the distance between the gate regions 30. Therefore, between the recesses 40 of the N ⁻ substrate 10. There is no need to reduce the distance.
As a result, the yield at the time of finely processing the recess 40 on the upper surface of the N ⁻ substrate 10 can be improved.

Since it is not necessary to reduce the distance between the recesses 40 as described above, the N ⁻ substrate 10 between the recesses 40 is reduced.
It is also suppressed that the cross-sectional area of the
^- resistance of the substrate 10 is reduced, as a result, the ON voltage attained is to large current decrease.

Further, as in this embodiment, the side portion 42 of the recess 40 is provided substantially parallel to the direction of the anode current flowing between the anode electrode 60 and the cathode electrode 70, so that the side gate region 32 is also formed. The depletion layer can be formed substantially parallel to the direction of the anode current, and as a result, the depletion layer can be uniformly extended over the entire channel length between the gate regions 30 at the time of off. Therefore, the breakdown voltage at the time of off can be further increased, the leakage current can be further reduced, and the electrostatic induction thyristor 100 excellent in the breaking capability can be obtained.

Further, as described above, by providing the side portion 42 of the recess 40 substantially parallel to the direction of the anode current,
Since more excellent off characteristics can be obtained, the distance between the recesses 40 of the N ⁻ substrate 10 can be increased. As a result, the yield at the time of finely processing the recess 40 in the N ⁻ substrate 10 can be further improved.

Further, since the distance between the recesses 40 can be made larger in this way, the N ⁻ substrate 1 between the recesses 40 is increased.
The cross-sectional area of 0 can be made wider, and the N ⁻ substrate 10 between the recesses 40 can be
Can be made smaller, and as a result, the on-state voltage can be further lowered and a larger current can be achieved.

The bottom 44 of the recess 40 of the N ⁻ substrate 10 is also used.
Since the bottom gate region 34 is also provided in the region exposed to, the lateral resistance of the gate can be made smaller, the maximum breaking current can be increased, and high frequency can be achieved.

As described above, in this embodiment, the region exposed on the side portion 42 of the recess 40 of the N ⁻ substrate 10 and the recess 4 are formed.
The gate resistance can be reduced because the side gate region 32 and the bottom gate region 34 are provided in the regions exposed to the bottom portion 44 of 0, respectively. As a result, the gate volume can be reduced and the controlled current can be increased, and the capacity can be increased.

In this static induction thyristor 100
Is P⁺The N base 50 provided with the gate region 30 of
N^-Substrate 10 and N^-Formed by joining the substrates 20
Therefore, the N base 50 has uniform and high quality crystallinity.
Can be obtained. Also, P ⁺The gate area 30 of
After completing N^-For epitaxial growth of layers
Sea urchin P⁺Conductivity type of the N base 50 between the gate regions 30 of the
Changes to P-type and it is impossible to control the anode current.
It won't happen. Also, P⁺Of the gate area 30
High-concentration doping is also possible.

FIG. 3 shows an electrostatic induction thyristor 1 of this embodiment.
4 is a plan view for explaining the entire structure of 00 of FIG.
FIG. 5 is a plan view of the electrostatic induction thyristor 100 of the present embodiment when the cathode electrode 70, the N ⁺ layer 22 and the N ⁻ substrate 20 are removed, and FIG. 5 is a sectional view taken along line XX of FIG. Is.

A guard ring 1 is provided on the outer peripheral portion of the N ⁻ substrate 10.
As well as relax the electric field concentration 71 by placement into a double, N ^-
An N ⁺ channel stopper 173 is provided on the outermost periphery of the substrate 10.
Is provided to prevent the depletion layer from spreading to the outer edge of the N ⁻ substrate 10. The distance between the outer guard ring 171 and the channel stopper 173 is not less than the thickness of the N ⁻ substrate 10.

The outer peripheral portion of the N ⁻ substrate 10 is covered with an insulating layer 175 made of SiO ₂ . The insulating layer 175 is N
^- also provided on the side surface of the substrate 20 and the N ⁺ layer 22, N ⁺
It is provided so as to extend to the peripheral portion on the upper surface of the layer 22. The cathode electrode 70 is provided on the N ⁺ layer 22, and the peripheral portion thereof is the insulating layer 1 provided on the peripheral portion of the N ⁺ layer 22.
It extends over 75.

N ⁻ substrate 10 inside guard ring 171
An annular gate electrode extraction portion 170 is provided on the upper surface of the. The N ⁻ substrate 10 under the gate electrode extraction portion 170
An annular P ⁺ layer 172 is provided on the upper surface of the. P ⁺
The depth of layer 172 is the same as the depth of guard ring 171. The gate electrode extraction part 170 is connected to an external lead part (not shown). The gate electrode extraction part 170 is N
^-After bonding the substrate 10 and the N ^- substrate 20, the N ^- substrate 20
The peripheral portion of the N ⁻ substrate 10 is removed by etching to expose the surface of the peripheral portion of the N ⁻ substrate 10 and the insulating layer 175 is formed, and then formed.

On the upper surface of the N ⁻ substrate 10 inside the gate electrode extraction portion 170, a recess (cavity) 140 having a width of 100 μm and a side portion 142 of the recess 140 of the N ⁻ substrate 10 and a region exposed to the recess 140 are formed. Wide gate area 1
30 are provided concentrically. Although only two of these are shown in FIG.
There are about a few books.

Between the wide concave portion 140 and the wide concave portion 140, 730, and between the wide concave portion 140 and the gate electrode extraction portion 1
70 to 732 of N ^{− on} the upper surface of the substrate 10 is 30 μm
Recesses 40 having a narrow width are provided concentrically. Although only a few lines are shown in FIG. 4, in actuality, 50 to 10 are provided between 730 and 732, respectively.
About 0 are provided. Sides 42 of each narrow recess 40
And P ^{+ in} the region of the N ⁻ substrate 10 exposed at the bottom 44.
Gate regions 30 are provided concentrically.

The concentric gate region 30, the gate region 130, and the gate electrode lead-out portion 170 are connected by a wide gate region 230 extending in the radial direction. Wide gate regions 230, N ^- providing a P ⁺ region in a region of the substrate 10 ^- the providing wide recess 240 extending radially on the upper surface of the substrate 10, N exposed to the side and bottom of the recess 240 It is formed by By thus providing the wide concentric gate region 130 and the gate region 230 extending in the radial direction, the narrow gate region 30 and the gate electrode lead-out portion 170 can be connected with low resistance.

The wide gate region 130, the wide gate region 230, and the wide concave portion 14 provided in this embodiment are provided.
0, the wide recess 240, the gate electrode extraction portion 170, the P ⁺ layer 172 under the gate electrode extraction portion 170, the guard ring 171, the channel stopper 173, the insulating layer 175, the cathode electrode 70, etc. The present invention is not limited to the embodiments, but can be applied to semiconductor devices of other embodiments described later.

In this embodiment, the joining was performed at 800 ° C., but the joining can be performed at 400 ° C. or higher. However, if the temperature is higher than 1100 ° C., the impurity of the P ⁺ gate region 30 diffuses into the N ⁻ substrates 10 and 20 and adversely affects the characteristics of the thyristor, which is not preferable. The joining is more preferably 700 to 700 at normal pressure.
Perform in the range of 1100 ° C. Less thermal diffusion of impurities,
Moreover, the strain of the junction crystal lattice can be reduced.

Further, in the present embodiment, the joining was performed without applying pressure from both sides of the N ⁻ substrates 10 and 20, but the joining can be performed while applying pressure from both sides of the N ⁻ substrates 10 and 20. preferable. This is because the bonding temperature decreases, heat diffusion is suppressed, and the number of non-contact parts decreases. The pressure is preferably added in the range of ^{0.1kg / cm 2 ~100kg / cm 2} . This is because if it is 0.1 kg / cm ² or less, the contact becomes insufficient, and if it is 100 kg / cm ² or more, a positional shift due to deformation occurs. At this time, the bonding temperature is preferably 400 to 1100 ° C. It is preferably 500 to 1000 ° C. This is because the joining temperature can be lowered by applying pressure.

(Second Embodiment) FIGS. 6 and 7 are perspective sectional views for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a second embodiment of the present invention.

In the present embodiment, after the gate region 30 is provided, the oxide film 80 is provided in the recess 40 so as to cover the gate region 30, and then the N ⁻ between the recesses 40 and the protrusions 14 and N ^{− of the} substrate 10. It differs from the first embodiment in that it is joined to the lower surface 24 of the substrate 20, but other configurations and manufacturing methods are the same as in the first embodiment. As in the present embodiment, the oxide film 80 is provided in the recess 40 so as to cover the gate region 30, and then the recess 40 is formed.
Between the convex portion 14 of the N ⁻ substrate 10 and the lower surface 24 of the N ⁻ substrate 20 between
By joining with the convex portion 14 of the N ⁻ substrate 10 and the lower surface 24 of the N ⁻ substrate 20, it is possible to prevent impurities from diffusing from the gate region 30 to the joint surface. The voltage is reduced and the breakdown voltage between the gate and the cathode is also improved. In this embodiment, after the gate region 30 is provided, the N ⁻ substrate 10 is thermally oxidized to form an oxide film, and then the upper surface of the N ⁻ substrate 10 is polished to form the oxide film shown in FIG.
An oxide film 80 in the state shown in was formed.

(Third Embodiment) FIGS. 8 to 11 are perspective sectional views for explaining an electrostatic induction thyristor according to a third embodiment of the present invention and a method for manufacturing the same.

First, N ⁻ substrates 10 and 20 in which at least the surfaces to be bonded to each other are mirror-polished are prepared.

Next, as shown in FIG. 8, recesses 40 having a width of 40 μm and a depth of 20 μm are provided at a pitch of 60 μm on the upper surface of the N ⁻ substrate 10 by photolithography.

Next, with an aqueous solution of sulfuric acid and hydrogen peroxide,
The N ⁻ substrates 10 and 20 are ultrasonically cleaned to remove organic substances and metals.

Next, the N ⁻ substrates 10 and 20 are washed with pure water and spinner dried at room temperature.

Next, as shown in FIG.
^- kept in contact with the lower surface 24 of the substrate 20, in a hydrogen atmosphere by heating at 800 ° C., N ^{- -} protrusion 14 and the N substrate 10 N base by bonding a substrate 20 ^- substrate 10 and the N A semiconductor substrate bonded body 200 composed of 50 is formed. The recess 40 and the lower surface 24 of the N ⁻ substrate 20 form a recess 140 in the N base 50.

Next, as shown in FIG. 10, by selectively diffusing boron, which is a P-type impurity, the P ⁺ gate region 30 is exposed to the side portion 42 and the bottom portion 44 of the recess 40, respectively. ^{-Region of} substrate 10 and N ^- substrate 20
Is selectively formed in a region of the lower surface 24 exposed to the recess 140. The P ⁺ gate region 30 thus formed
Is composed of a side gate region 32, a bottom gate region 34 and a ceiling gate region 36. The diffusion of boron was performed at a temperature of 1050 to 1200 ° C. in a BBr ₃ + O ₂ atmosphere. Further, when the boron is diffused, the recess 4
N exposed to the side portion 42, the bottom portion 44, and the recess 140 of 0
^- the lower surface 24 of the substrate 20 an oxide film is formed, but not shown.

Next, as shown in FIG. 11, the impurity diffusion method is used.
By N^-The bottom surface of the substrate 10 is P ⁺Layer 12, N^-Base
The upper surface of the plate 20 has N⁺Layers 22 are each formed.

Next, the P formed on the lower surface of the N ⁻ substrate 10 is formed.
^An anode electrode 60 and a cathode electrode 70 are formed on the lower surface of the ⁺ layer 12 and the upper surface of the N ⁺ layer 22 formed on the upper surface of the N ⁻ substrate 20, respectively.

In the electrostatic induction thyristor 100 thus formed, the P ⁺ layer 12 functions as the anode, the N ⁺ layer 22 functions as the cathode, and the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as the N base 50. The side gate region 32,
The P ⁺ gate region 30 composed of the bottom gate region 34 and the ceiling gate region 36 functions as a gate that controls the anode current flowing between the anode electrode 60 and the cathode electrode 70.

In this embodiment, the P ⁺ gate region 3
Since 0 is constituted not only by the side gate region 32 and the bottom gate region 34 but also by the ceiling gate region 36, the first gate region 30 of P ⁺ is constituted by the side gate region 32 and the bottom gate region 34. As compared with the case of the second embodiment, the lateral resistance of the gate becomes smaller, the maximum breaking current can be further increased, and the frequency can be further increased.

(Fourth Embodiment) FIG. 12 shows the fourth embodiment of the present invention.
3 is a perspective cross-sectional view for explaining the electrostatic induction thyristor of the embodiment of FIG.

In this embodiment, the N ⁻ substrate 10 and the N ⁻ substrate 20 are bonded and then thermally oxidized to form the side gate region 32, the bottom gate region 34 and the recess 40 of the lower surface 24 of the N ⁻ substrate 20. The exposed region is covered with an oxide film 80, and then the anode electrode 60 is formed on the lower surface of the P ⁺ layer 12 formed on the lower surface of the N ⁻ substrate 10 and the upper surface of the N ⁺ layer 22 formed on the upper surface of the N ⁻ substrate 20. The cathode electrode 70 is different from that of the first embodiment in that the cathode electrode 70 and the cathode electrode 70 are respectively formed, but other configurations and manufacturing methods are the same.

In the present embodiment, since the pn junction is passivated by the oxide film 80, the breakdown voltage between the gate and the cathode can be improved.

(Fifth Embodiment) FIG. 13 shows the fifth embodiment of the present invention.
3 is a perspective cross-sectional view for explaining the electrostatic induction thyristor of the embodiment of FIG.

In this embodiment, the N ⁻ substrate 10 and the N ⁻ substrate 20 are bonded to form a semiconductor substrate bonded body composed of the N base 50, and then the side gate region 32, the bottom gate region 34, and the ceiling. The gate region 30 of P ⁺ composed of the partial gate region 36 is formed and then thermally oxidized to cover the side gate region 32, the bottom gate region 34 and the ceiling gate region 36 with an oxide film, and then N ^- P ⁺ layer 12, N on the lower surface of the substrate 10 ^- on the upper surface of the substrate 20 N ⁺ layer 22 are respectively formed, but that the anode electrode 60 and cathode electrode 70 are formed respectively different from the third embodiment The other configurations and manufacturing methods are the same.

Also in this embodiment, since the pn junction is passivated by the oxide film 80, the breakdown voltage between the gate and the cathode can be improved.

(Sixth Embodiment) FIGS. 14 and 15 show
It is a perspective sectional view for explaining the static induction thyristor of the 6th example of the present invention, and a manufacturing method for the same.

First, N ⁻ substrates 10 and 20 in which at least the surfaces to be bonded to each other are mirror-polished are prepared.

Next, as shown in FIG. 14, the N ⁻ substrate 10
A P ⁺ layer 12 is formed on the lower surface of the P by an impurity diffusion method. Next, a width of 40 μm and a depth of 25 which can accommodate the gate electrode 90 are formed on the upper surface of the N ⁻ substrate 10 by photolithography.
The μm recesses 40 are provided at a pitch of 60 μm.

Next, by selectively diffusing boron which is a P-type impurity, the P ⁺ gate region 30 is recessed 40.
Are selectively formed in the regions of the N ⁻ substrate 10 exposed on the side portion 42 and the bottom portion 44, respectively. The P ⁺ gate region 30 thus formed is composed of a side gate region 32 and a bottom gate region 34. The boron diffusion is 1050 to 1200 ° C. in a BBr ₃ + O ₂ atmosphere.
Temperature. An oxide film is formed on the side portion 42 and the bottom portion 44 of the recess 40 when the boron is diffused, but it is not shown.

Next, by photolithography, a width of 20 μm is formed on the bottom gate region 34 and in the recess 40.
Gate electrode 90 made of tungsten having a film thickness of 0.5 μm
Are selectively formed.

On the other hand, the N ⁺ layer 22 is formed on the upper surface of the N ⁻ substrate 20 by the impurity diffusion method.

Next, with an aqueous solution of sulfuric acid and hydrogen peroxide,
The N ⁻ substrates 10 and 20 are ultrasonically cleaned to remove organic substances and metals.

Next, the N ⁻ substrates 10 and 20 are washed with pure water and spinner dried at room temperature.

Next, as shown in FIG. 15, heating is performed at 800 ° C. in a hydrogen atmosphere in a state where the convex portion 14 of the N ⁻ substrate 10 and the lower surface 24 of the N ⁻ substrate 20 between the concave portions 40 are in contact with each other. Thus, the N ⁻ substrate 10 and the N ⁻ substrate 20 are bonded. In addition, when aluminum is used for the gate electrode 90, the bonding is performed at 400 ° C.

Next, the P formed on the lower surface of the N ⁻ substrate 10 is formed.
^An anode electrode 60 and a cathode electrode 70 are formed on the lower surface of the ⁺ layer 12 and the upper surface of the N ⁺ layer 22 formed on the upper surface of the N ⁻ substrate 20, respectively.

In the electrostatic induction thyristor 100 thus formed, the P ⁺ layer 12 functions as the anode, the N ⁺ layer 22 functions as the cathode, and the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as the N base 50. P ⁺ gate region 30
The gate electrode 90 also functions as a gate that controls the anode current flowing between the anode electrode 60 and the cathode electrode 70.

In the present embodiment, the bottom gate region 34
Since the gate electrode 90 made of tungsten is provided on the upper side, the resistance in the lateral direction of the gate is reduced to increase the maximum breaking current, and the extraction current of carriers can be increased to enable faster switching. Become.

The gate electrode 90 is formed in the recess 40 of the N ⁻ substrate 10 before joining the N ⁻ substrate 10 and the N ⁻ substrate 20.
Since the gate electrode 90 is already housed in the inside, a groove having a large aspect ratio is externally provided in the N ⁺ layer 22 and the N ⁻ substrate 20, and the gate electrode 90 is provided in the groove. Is not necessary, and the N ⁺ layer 22 and the N ⁻ substrate 20 are not finely divided by the groove to have a high resistance.

Further, since the recess 40 provided on the upper surface of the N ⁻ substrate 10 can accommodate the gate electrode 90,
For example, even if the recess 40 is formed by a dry etching method having a low etching rate, it does not take too long to form the recess 40.

Further, the gate electrode 90 is the N ⁻ substrate 10
Since it is accommodated in the recess 40 provided on the upper surface of the
^- substrate 20 ^- N that is joined to the convex portion 14 of the upper surface of the substrate 10
It is not necessary to provide a recess in the lower surface 24 of the
May be planar. Therefore, when the convex portion 14 on the upper surface of the N ⁻ substrate 10 and the lower surface 24 of the N ⁻ substrate 20 are joined together, it is not necessary to perform special alignment, and the manufacturing is facilitated.

FIG. 16 is a plan view for explaining the overall structure of the electrostatic induction thyristor 100 of this embodiment,
From the electrostatic induction thyristor 100 to the cathode electrode 70, N ⁺
FIG. 17 is a plan view when the layer 22 and the N ⁻ substrate 20 are removed, and FIG. 17 is a sectional view taken along line YY of FIG. 16.

A guard ring 1 is provided on the outer peripheral portion of the N ⁻ substrate 10.
As well as relax the electric field concentration 71 by placement into a double, N ^-
An N ⁺ channel stopper 173 is provided on the outermost periphery of the substrate 10.
Is provided to prevent the depletion layer from spreading to the outer edge of the N ⁻ substrate 10. The distance between the outer guard ring 171 and the channel stopper 173 is not less than the thickness of the N ⁻ substrate 10.

The outer peripheral portion of the N ⁻ substrate 10 is covered with an insulating layer 175 made of SiO ₂ . The insulating layer 175 is N
^- also provided on the side surface of the substrate 20 and the N ⁺ layer 22, N ⁺
It is provided so as to extend to the peripheral portion on the upper surface of the layer 22. The cathode electrode 70 is provided on the N ⁺ layer 22, and the peripheral portion thereof is the insulating layer 1 provided on the peripheral portion of the N ⁺ layer 22.
It extends over 75.

N ⁻ substrate 10 inside guard ring 171
An annular gate electrode extraction portion 170 is provided on the upper surface of the. The N ⁻ substrate 10 under the gate electrode extraction portion 170
An annular P ⁺ layer 172 is provided on the upper surface of the. P ⁺
The depth of layer 172 is the same as the depth of guard ring 171. The gate electrode extraction part 170 is connected to an external lead part (not shown). The gate electrode extraction part 170 is N
^-After bonding the substrate 10 and the N ^- substrate 20, the N ^- substrate 20
The peripheral portion of the N ⁻ substrate 10 is removed by etching to expose the surface of the peripheral portion of the N ⁻ substrate 10 and the insulating layer 175 is formed, and then formed.

On the upper surface of the N ⁻ substrate 10 inside the gate electrode lead-out portion 170, a wide concave portion 140 having a width of 100 μm and a wide area formed in a region exposed to the side portion 142 and the bottom portion 144 of the concave portion 140 of the N ⁻ substrate 10 are formed. The gate region 130 and a wide gate electrode 190 made of tungsten on the gate region 130 are concentrically provided. Although only two of these are shown in FIG.
About 30 are provided.

Between the wide concave portion 140 and the wide concave portion 140 730, and between the wide concave portion 140 and the gate electrode lead-out portion 1
70 to 732 of N ^{− on} the upper surface of the substrate 10 is 30 μm
Recesses 40 having a narrow width are provided concentrically. Although only a few lines are shown in FIG. 4, in actuality, 50 to 10 are provided between 730 and 732, respectively.
About 0 are provided. Sides 42 of each narrow recess 40
And P ^{+ in} the region of the N ⁻ substrate 10 exposed at the bottom 44.
The gate regions 30 are provided concentrically, and the gate electrodes 90 are provided concentrically on each gate region 30.

Concentric gate region 30 and gate region 1
30, the gate electrode 90, the gate electrode 190, and the gate electrode extraction portion 170 are connected by a wide gate region 230 and a wide gate electrode 290 that extend in the radial direction. Wide gate regions 230, N ^- providing a P ⁺ region in a region of the substrate 10 ^- the providing wide recess 240 extending radially on the upper surface of the substrate 10, N exposed to the side and bottom of the recess 240 It is formed by The wide gate electrode 290 is used for the wide gate region 2
It is formed on 30. Thus, the wide concentric gate region 130 and the gate electrode 190, and the radially extending gate region 230 and the gate electrode 290.
By providing, the narrow gate region 30 and the gate electrode 90 can be connected to the gate electrode extraction portion 170 with low resistance.

The wide gate region 130, the wide gate region 230, the wide gate electrode 190, the wide gate electrode 290, the wide recess 140, which are provided in this embodiment,
The wide recess 240, the gate electrode lead-out portion 170, the P ⁺ layer 172 below the gate electrode lead-out portion 170, the guard ring 17
The specific structures of 1, the channel stopper 173, the insulating layer 175, the cathode electrode 70, etc. are not limited to the present embodiment, but can be applied to semiconductor devices of other embodiments described later.

(Seventh Embodiment) FIGS. 18 and 19 are perspective sectional views for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a seventh embodiment of the present invention.

In this embodiment, after the gate region 30 and the gate electrode 90 are provided, the oxide film 80 is provided in the recess 40 so as to cover the gate electrode 90 and the gate region 30, and then the N ⁻ substrate between the recesses 40 is provided. 10 convex portions 14 and N
^- Although point joining the lower surface 24 of the substrate 20 is different from the sixth embodiment, the other configuration and manufacturing method is the same as the sixth embodiment. As in the present embodiment, the oxide film 80 is provided in the recess 40 so as to cover the gate electrode 90 and the gate region 30, and then the protrusion 14 of the N ⁻ substrate 10 and the N ⁻ substrate 2 between the recesses 40.
N ⁻ substrate 10 by bonding to the bottom surface 24 of
The convex portion 14 and the N ^- When bonding the bottom surface 24 of substrate 20, N ^- protrusion 14 and the N substrate 10 ^- the lower surface of the substrate 20 24
Can be kept clean at the time of bonding, and the N ⁻ substrate 1
It is possible to obtain a better joint between the convex portion 14 of 0 and the lower surface 24 of the N ⁻ substrate 20.

In the present embodiment, the oxide film 80 is formed by depositing the oxide film 80 by the chemical vapor deposition method when a refractory metal such as tungsten or a metal such as aluminum is used as the gate electrode 90. Preferably, when polycrystalline silicon doped with impurities is used as the gate electrode 90, the polycrystalline silicon may be oxidized to form the oxide film 80, and the oxide film 8 may be formed by the CVD method.
0 may be deposited.

In this embodiment, thermal oxidation or CVD is used.
Then, an oxide film 80 is formed by the method, and then the upper surface of the N ⁻ substrate 10 is polished to form the oxide film 80 in the state shown in FIG.

Instead of the oxide film 80, another insulating film such as a silicon nitride film or a silicon oxynitride film can be used.

(Eighth Embodiment) FIGS. 20 and 21 are perspective sectional views for explaining an electrostatic induction thyristor and a method for manufacturing the same according to an eighth embodiment of the present invention.

In this embodiment, polycrystalline silicon doped with boron is used for the gate electrode 90, and the N ⁻ substrate 10 and the N ⁻ substrate 20 are joined to each other to form the semiconductor substrate joined body 300 made of the N base 50. , Thermal oxidation is performed to cover the gate electrode 90, the side gate region 32, the bottom gate region 34 and the lower surface 24 of the N ⁻ substrate 20 with the oxide film 80, and then the anode electrode 60 and the cathode electrode 7 are formed.
Although 0 is formed respectively, it is different from the sixth embodiment, but other configurations and manufacturing methods are the same.

Also in this embodiment, since the pn junction is passivated by the oxide film 80, the breakdown voltage between the gate and the cathode can be improved.

In the above embodiments, the case where the present invention is applied to the electrostatic induction thyristor has been described, but the present invention is the first embodiment described with reference to FIGS. 1 to 21.
To the static induction thyristor according to the eighth embodiment, P ⁺
The same applies to the static induction transistor in which the layer 12 is replaced with the N ⁺ drain.

(Ninth Embodiment) FIGS. 22 and 23 show
It is a perspective sectional view for explaining the static induction thyristor of the 9th example of the present invention, and a manufacturing method for the same. This embodiment is similar to the sixth embodiment, but there is a difference in that a high impurity concentration region is formed in a portion corresponding to the joint surface between the convex portion 14 of the N ⁻ substrate 10 and the N ⁻ substrate 20. .

Here, N ⁻ substrates 10 and 20 in which at least the surfaces to be bonded to each other are mirror-polished are prepared.

Next, as shown in FIG. 22, N ⁻ substrate 10
A P ⁺ layer 12 is formed on the lower surface of the P by an impurity diffusion method. Next, the N ⁺ layer 16 is selectively formed on the upper surface of the N ⁻ substrate 10 by a photolithography method with a predetermined width and approximately 50 Å to 500 Å
It is preferably formed to a depth of 100Å. The impurity concentration in this case is at least about 10 ^{19 -20} cm ^-3 . Next, a recess 4 having a width of 40 μm and a depth of 25 μm, which is between the N ⁺ layers 16 and can accommodate the gate electrode 90 in the N ⁻ substrate 10.
0s are provided at a pitch of 60 μm.

[0161] Next, N respectively exposed to the side 42 and the bottom 44 of the recess 40 of the gate region 30 of P ⁺ by selectively diffusing boron is a P-type impurity ^- substrate 1
It is selectively formed in the region of 0. The P ⁺ gate region 30 thus formed is composed of a side gate region 32 and a bottom gate region 34.

Next, by photolithography, a width of 20 μm is formed on the bottom gate region 34 and in the recess 40.
Gate electrode 90 made of tungsten having a film thickness of 0.5 μm
Are selectively formed.

On the other hand, the N ⁺ layer 22 is formed on the upper surface of the N ⁻ substrate 20 by the impurity diffusion method.

Next, the sulfuric acid + hydrogen peroxide solution was used to remove N.
^- removing organic substances and metals subjected to ultrasonic cleaning of the substrate 10 and 20.

Next, the N ⁻ substrates 10 and 20 are washed with pure water and spinner dried at room temperature.

Then, as shown in FIG. 23, the convex portions 14 of the N ⁻ substrate 10 between the concave portions 40 and the lower surface 24 of the N ⁻ substrate 20 are brought into contact with each other and heated at 800 ° C. in a hydrogen atmosphere. Thus, the N ⁻ substrate 10 and the N ⁻ substrate 20 are bonded. In addition, when aluminum is used for the gate electrode 90, the bonding is performed at 400 ° C.

Next, the P formed on the lower surface of the N ⁻ substrate 10 is formed.
^An anode electrode 60 and a cathode electrode 70 are formed on the lower surface of the ⁺ layer 12 and the upper surface of the N ⁺ layer 22 formed on the upper surface of the N ⁻ substrate 20, respectively.

In the electrostatic induction thyristor 100 thus formed, the N ⁺ layer 12 functions as the anode, the N ⁺ layer 22 functions as the cathode, and the N ⁻ substrate 10 and the N ⁻ substrate 20 both function as the N base 50. P ⁺ gate region 30
The gate electrode 90 also functions as a gate that controls the anode current flowing between the anode electrode 60 and the cathode electrode 70.

(Tenth Embodiment) FIG. 24 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a tenth embodiment of the present invention.

In the ninth embodiment, N^-On the substrate 10 side
High impurity concentration region, that is, N ⁺Layer 16 selectively
Although provided, in the tenth embodiment, rather, N^-substrate
N to face 10^-A region of high impurity concentration on the substrate 20 side
It is provided.

That is, on the N ⁻ substrate 10 side, after the mirror-polished N ⁻ substrates 10 and 20 are prepared, the width 20 is provided on the bottom region 34 and in the recess 40 as in the sixth embodiment.
Processing steps are performed until the gate electrode 90 made of tungsten having a thickness of 0.5 μm and a thickness of 0.5 μm is selectively formed (see FIG. 14).

On the other hand, the N ⁺ layer 22 is formed on the upper surface of the N ⁻ substrate 20 by the impurity diffusion method. Then, the N ^- substrate 1
The N ⁺ layers 17 are formed as regions of high impurity concentration in a region facing the 0 side with a gap of 60 μm and a width of 15 μm and a depth of 50 to 50 μm.
It is selectively formed with a thickness of 500Å, preferably 100Å.
At this time, the impurity concentration for forming the N ⁺ layer 17 is at least 10 19 ^-20 cm ^-3 .

Next, the sulfuric acid + hydrogen peroxide solution was used to remove N
^- the organic substances and metal is removed by ultrasonic cleaning of the substrate 10 and 20, below, perform the same steps as the sixth embodiment (see FIG. 25).

The ninth and tenth embodiments described above have the following specific effects.

Generally, when substrates having a low impurity concentration are bonded together, the electrical resistance of the bonded portion becomes relatively high. Therefore, there is an inconvenience that power consumption and heat generation amount increase. In order to eliminate this inconvenience, this embodiment forms a high impurity concentration region on at least one surface of two semiconductor substrates which are bonded to each other. That is, a high impurity concentration region (N ⁺ layer 16 or 1 or more) is formed on at least one surface.
By bonding the semiconductor substrates formed with 7) to each other and heating them, impurities are diffused into the other substrate, and an electrically favorable ohmic contact is obtained.

Here, in the high impurity concentration region (N ⁺ layer 16 or 17) at the junction between the semiconductor substrates, the gate breakdown voltage in contact with the gate layer may be lowered, and main current control may not be performed sufficiently. In this embodiment, the high-concentration region of the junction is formed at a position separated from the gate region by about several μm, so there is no possibility of that.

[0177]

In the semiconductor device of the present invention, since the cavity is provided in the semiconductor substrate and the gate region is provided in the region exposed to the side of the cavity of the semiconductor substrate, the breakdown voltage at the time of off is increased. In addition, the leakage current can be reduced, and a semiconductor device having an excellent breaking capability can be obtained. Further, it is possible to obtain a predetermined off characteristic without reducing the distance between the gate regions, and it is not necessary to reduce the distance between the cavities of the semiconductor substrate. As a result, the yield at the time of finely processing the cavities in the semiconductor substrate can be improved. Further, since it is not necessary to narrow the space between the cavities, it is possible to suppress the reduction of the cross-sectional area of the semiconductor substrate between the cavities, and the resistance of the semiconductor substrate between the cavities is reduced. Can be converted to current.

Further, by providing the side portions of the cavity substantially parallel to the direction of the current flowing between the anode electrode and the cathode electrode, the breakdown voltage at the off time can be further increased, and the leakage current is also smaller. It is possible to obtain a semiconductor device having an excellent breaking ability. In addition, the space between the cavities of the semiconductor substrate can be made wider, and as a result, the yield in microfabrication of the cavities in the semiconductor substrate can be further improved. Further, the cross-sectional area of the semiconductor substrate between the cavities can be made wider, and the resistance of the semiconductor substrate between the cavities can be made smaller. As a result, the on-voltage can be further lowered and a larger current can be achieved.

Further, by providing the gate region also in the region exposed at the bottom of the cavity of the semiconductor substrate and / or by providing the gate region also in the region exposed at the ceiling of the cavity of the semiconductor substrate, the gate lateral direction can be improved. The resistance is reduced, the maximum breaking current can be increased, and high frequency can be achieved.

Moreover, by providing an insulating film in the cavity so as to cover the pn junction exposed in the cavity of the pn junction formed between the gate region and the semiconductor substrate, the gate-
The breakdown voltage between the cathodes can be improved. Further, by providing the insulating film in the cavity so as to cover the entire surface of the region exposed in the cavity of the semiconductor substrate, the breakdown voltage between the gate and the cathode can be more reliably improved.

Further, by further providing the gate electrode made of a good conductor electrically connected to the gate region in the cavity of the semiconductor substrate, the maximum breaking current can be increased and high-speed switching can be performed.

In the method of manufacturing a semiconductor device of the present invention, the gate region is provided in the region of the first semiconductor substrate exposed on the side of the recess provided in the one main surface of the first semiconductor substrate. In addition, it is possible to increase the breakdown voltage at the time of off, reduce the leakage current, and manufacture a semiconductor device having an excellent breaking capability. Further, it is possible to obtain a predetermined off characteristic without reducing the distance between the gate regions, and it is not necessary to reduce the distance between the concave portions provided on the one main surface of the first semiconductor substrate. As a result, the yield at the time of finely processing the concave portion on the one main surface of the first semiconductor substrate can be improved. Further, since it is not necessary to narrow the space between the recesses, it is also possible to suppress the reduction in the cross-sectional area of the first semiconductor substrate between the recesses, and the resistance of the first semiconductor substrate between the recesses is lowered, and as a result, the ON The voltage drops and a large current can be achieved.

Further, in the present invention, the base on which the gate region is provided is formed by joining the first semiconductor substrate and the second semiconductor substrate without performing epitaxial growth, so that the crystallinity is uniform and of high quality. It is possible to obtain a base having Moreover, the conductivity type of the base between the gate regions is not changed, and the control of the anode current does not become impossible. High concentration doping of the gate region is also possible.

Further, by providing the side portion of the recess substantially perpendicularly to the one main surface of the first semiconductor substrate, the breakdown voltage at the off time can be further increased and the leakage current can be further reduced. It is possible to manufacture a semiconductor device having an excellent breaking ability. Further, the distance between the recesses of the first semiconductor substrate can be made wider, and as a result, the yield at the time of finely processing the recesses on the one main surface of the first semiconductor substrate can be further improved. Further, the first between the recesses
Of the semiconductor substrate can be made wider, and the resistance of the first semiconductor substrate between the recesses can be made smaller. As a result, the on-voltage of the semiconductor device manufactured by this manufacturing method can be further reduced to further increase the large current. Can be realized.

Further, by providing the gate region also in the region exposed at the bottom of the cavity of the semiconductor substrate, the lateral resistance of the gate is reduced, the maximum breaking current can be increased, and the frequency can be increased.

Further, the first and second semiconductor substrates of one conductivity type are prepared respectively, and recesses are formed in one main surface of the first semiconductor substrate, and one main surface is exposed between the recesses to selectively. Provided,
The one main surface of the first semiconductor substrate exposed between the recesses and the one main surface of the second semiconductor substrate are joined together, and after joining, the regions exposed on the side and bottom of the recess of the first semiconductor substrate, and By providing a gate region of another conductivity type doped with an impurity in a region which is one main surface of the second semiconductor substrate and is exposed in the recess, the gate region is formed on the side, bottom and ceiling of the recess. , The lateral resistance of the gate becomes smaller, the maximum breaking current can be further increased, and the frequency can be further increased.

By providing the insulating film in the recess after covering the gate region after providing the gate region, the on-voltage is reduced and the breakdown voltage between the gate and the cathode is improved.

In addition, the first main surface of the first semiconductor substrate and the second
After bonding the main surface of the semiconductor substrate with the first main surface of the semiconductor substrate, an oxide film is provided on the side and bottom portions of the recess and in the area of the main surface of the second semiconductor substrate that is exposed in the recess. The pn junction formed between the semiconductor substrate and the second semiconductor substrate can be passivated, and as a result, the breakdown voltage between the gate and the cathode is improved. Also, the first
Prior to joining the one main surface of the semiconductor substrate and the one main surface of the second semiconductor substrate, a good conductor electrically connected to the gate region in the recess provided in the one main surface of the first semiconductor substrate. By providing the gate electrode made of, the maximum breaking current can be increased and high-speed switching can be performed.

Since the gate electrode is already provided in the concave portion of the first semiconductor substrate before the main surface of the first semiconductor substrate and the main surface of the second semiconductor substrate are joined,
Even when the gate electrode is provided in the semiconductor substrate as described above, it is not necessary to form a groove having a large aspect ratio in the semiconductor substrate from the outside and form the gate electrode in the groove. As a result, the semiconductor substrate above the gate electrode is not finely divided by the groove to have a high resistance.

Further, the recess provided on the one main surface of the first semiconductor substrate need only be capable of accommodating the gate electrode. Therefore, even if the recess is formed by a dry etching method with a low etching rate, the formation thereof is possible. Never takes too long.

Furthermore, since the gate electrode is provided in the recess provided in the one main surface of the first semiconductor substrate, the second semiconductor substrate of the second semiconductor substrate joined to the one main surface of the first semiconductor substrate is formed. It is not necessary to provide the concave portion on the one main surface, and the one main surface may be flat. Therefore, when the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate are bonded to each other, it is not necessary to perform special alignment, which facilitates manufacturing.

Before joining the main surface of the first semiconductor substrate and the main surface of the second semiconductor substrate, a gate electrode is formed in the recess provided in the main surface of the first semiconductor substrate. By providing the insulating film so as to cover, the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate can be kept clean at the time of bonding, and the one main surface of the first semiconductor substrate and the first main substrate can be kept clean. It is possible to obtain a better bond between the two main surfaces of the semiconductor substrate.

After joining the first main surface of the first semiconductor substrate and the first main surface of the second semiconductor substrate, the first semiconductor substrate is exposed in the side and bottom portions of the recess, and By providing an oxide film on the main surface of the semiconductor substrate and covering the region exposed in the recess and the gate electrode,
The pn junction between the gate region and the semiconductor substrate is passivated, and the breakdown voltage between the gate and the cathode is improved.

Further, a plurality of high impurity concentration regions are provided on the main surface of either one of the first and second semiconductor substrates at a predetermined interval. Therefore, even if substrates having low impurity concentrations are bonded to each other, there is an advantage that the power consumption and the heat generation can be suppressed as a result of ohmic bonding.

[Brief description of drawings]

FIG. 1 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a first embodiment of the present invention.

FIG. 2 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the first embodiment of the present invention.

FIG. 3 is a plan view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the first embodiment of the present invention.

FIG. 4 is a plan view for explaining the electrostatic induction thyristor and the manufacturing method thereof according to the first embodiment of the present invention.

5 is a sectional view taken along line XX of FIG.

FIG. 6 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the second embodiment of the present invention.

FIG. 7 is a perspective cross-sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the second embodiment of the present invention.

FIG. 8 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the third embodiment of the present invention.

FIG. 9 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a third embodiment of the present invention.

FIG. 10 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a third embodiment of the present invention.

FIG. 11 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the third embodiment of the present invention.

FIG. 12 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a fourth embodiment of the present invention.

FIG. 13 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the fifth embodiment of the present invention.

FIG. 14 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the sixth embodiment of the present invention.

FIG. 15 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the sixth embodiment of the present invention.

FIG. 16 is a plan view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the sixth embodiment of the present invention.

17 is a cross-sectional view taken along the line YY of FIG.

FIG. 18 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the seventh embodiment of the present invention.

FIG. 19 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a seventh embodiment of the present invention.

FIG. 20 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the eighth embodiment of the present invention.

FIG. 21 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to an eighth embodiment of the present invention.

FIG. 22 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the ninth embodiment of the present invention.

FIG. 23 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a ninth embodiment of the present invention.

FIG. 24 is a perspective sectional view for explaining an electrostatic induction thyristor and a method for manufacturing the same according to a tenth embodiment of the present invention.

FIG. 25 is a perspective sectional view for explaining the electrostatic induction thyristor and the method for manufacturing the same according to the tenth embodiment of the present invention.

FIG. 26 is a perspective sectional view for explaining a conventional junction type electrostatic induction thyristor and a method for manufacturing the same.

FIG. 27 is a perspective sectional view for explaining a conventional junction type electrostatic induction thyristor and a method for manufacturing the same.

[Explanation of symbols]

10 ... N ^- substrate, 12 ... P ⁺ layer, 14 ... Convex portion, 20 ... N
^- substrate, 22 ... N ⁺ layer, 24 ... bottom surface, 30 ... gate region, 32 ... side gate regions, 34 ... bottom gate region, 3
6 ... Ceiling gate region, 40 ... Recessed portion, 42 ... Side portion, 44
... bottom part, 50 ... N base, 60 ... anode electrode, 70 ...
Cathode electrode, 80 ... Oxide film, 90 ... Gate electrode, 10
0 ... Electrostatic induction thyristor, 130 ... Gate region, 140
... Recesses, 200 ... Semiconductor substrate bonded body, 300 ... Semiconductor substrate bonded body

Claims (24)

[Claims] 1. A semiconductor device in which a gate for controlling a current flowing between the anode electrode and the cathode electrode is provided in the semiconductor substrate provided between the anode electrode and the cathode electrode. A cavity inside,
A semiconductor device, wherein a gate region is provided in a region exposed on a side portion of the cavity of the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein a side portion of the cavity is provided substantially parallel to a direction of the current flowing between the anode electrode and the cathode electrode. 3. A gate region is provided in a region exposed at the bottom of the cavity of the semiconductor substrate.
Alternatively, the semiconductor device according to item 2. 4. The semiconductor device according to claim 1, wherein a gate region is provided in a region exposed on the ceiling of the cavity of the semiconductor substrate. 5. A pn junction is formed between the gate region and the semiconductor substrate, and an insulating film is provided in the cavity to cover the pn junction of the pn junction exposed in the cavity. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 6. The semiconductor device according to claim 5, wherein an insulating film is provided in the cavity so as to cover the entire surface of the region of the semiconductor substrate exposed in the cavity. 7. The semiconductor according to claim 1, further comprising a gate electrode made of a good conductor electrically connected to the gate region in the cavity of the semiconductor substrate. apparatus. 8. The semiconductor device according to claim 7, wherein an insulating film is provided in the cavity so as to cover the gate electrode. 9. The semiconductor substrate comprises: a first semiconductor layer of one conductivity type, a second semiconductor layer of another conductivity type provided on the first semiconductor layer, and the second semiconductor layer. A third semiconductor layer provided above and having a higher impurity concentration than the second semiconductor layer and having a conductivity type other than the second semiconductor layer, wherein one of the anode electrode and the cathode electrode is electrically connected to the first semiconductor layer. And the other of the anode electrode and the cathode electrode is electrically connected to the third semiconductor layer, the gate region is the semiconductor of one conductivity type, and the cavity and 2. The gate region is provided in the second semiconductor layer.
9. The semiconductor device according to any one of 8 to 8. 10. The semiconductor substrate includes a first semiconductor layer of one conductivity type, a second semiconductor layer of another conductivity type provided on the first semiconductor layer, the first and second semiconductor layers. And a third semiconductor layer having a high impurity concentration, the one of the anode electrode and the cathode electrode being electrically connected to the first semiconductor layer. The other of the cathode electrodes is provided to be electrically connected to the second semiconductor layer, and the cavity is provided to the third semiconductor layer.
9. The semiconductor device according to claim 1, wherein a plurality of semiconductors are provided corresponding to the number of semiconductors, and a high impurity concentration region is provided between the adjacent cavities. 11. A step of preparing first and second semiconductor substrates of one conductivity type, a step of providing a recess in one main surface of the first semiconductor substrate, and at least the first semiconductor substrate. A step of selectively providing an impurity-doped gate region of another conductivity type in a region exposed on the side of the recess, exposing the one main surface of the first semiconductor substrate between the gate regions; And a step of joining the one main surface of the first semiconductor substrate exposed between the gate regions and the one main surface of the second semiconductor substrate to each other. . 12. The method of manufacturing a semiconductor device according to claim 11, wherein the side portion of the recess is provided substantially perpendicular to the one main surface of the first semiconductor substrate. 13. A gate region of another conductivity type doped with an impurity is provided in a region exposed at least at a side of the recess of the first semiconductor substrate, and the gate region of the first semiconductor substrate is provided between the gate regions. The step of exposing and selectively providing one main surface may include forming a gate region of another conductivity type, which is doped with impurities, in a region exposed on a side portion and a bottom portion of the recess of the first semiconductor substrate. 13. The method of manufacturing a semiconductor device according to claim 11, further comprising the step of exposing and selectively providing the one main surface of the first semiconductor substrate between the gate regions. 14. A step of preparing first and second semiconductor substrates of one conductivity type, respectively, and a step of exposing a concave portion on one main surface of the first semiconductor substrate and exposing the one main surface between the concave portions. A step of selectively providing, a step of joining the one main surface of the first semiconductor substrate exposed between the recesses and a one main surface of the second semiconductor substrate, and the step of: Gate regions of another conductivity type in which impurities are doped in the regions exposed at the side and bottom of the recess of the first semiconductor substrate and in the region of the one main surface of the second semiconductor substrate exposed in the recess. A method of manufacturing a semiconductor device, comprising: 15. After providing the gate region, an insulating film is provided in the recess so as to cover the gate region, and then, the one main surface of the first semiconductor substrate exposed between the gate regions, 14. The method of manufacturing a semiconductor device according to claim 11, wherein the main surface of the second semiconductor substrate is bonded. 16. After joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate, side and bottom portions of the recess and the one of the second semiconductor substrate. 16. The method of manufacturing a semiconductor device according to claim 11, further comprising the step of providing an oxide film in a region which is the main surface and is exposed in the recess. 17. A good conductor that is electrically connected to the gate region in the recess before joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate. 16. The method of manufacturing a semiconductor device according to claim 11, further comprising the step of providing a gate electrode made of. 18. A step of providing an insulating film in the recess to cover the gate electrode before joining the one main surface of the first semiconductor substrate and the one main surface of the second semiconductor substrate. 18. The method for manufacturing a semiconductor device according to claim 17, further comprising: 19. The first principal surface of the first semiconductor substrate and the first principal surface of the second semiconductor substrate are bonded together, and then the first principal surface is bonded.
Of the semiconductor substrate, the oxide film is provided so as to cover the regions exposed to the side and bottom of the recess, the region of the one main surface of the second semiconductor substrate exposed to the recess, and the gate electrode. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising a step. 20. One of another main surface of the first semiconductor substrate opposite to the one main surface and another main surface of the second semiconductor substrate opposite to the one main surface. A step of providing the other conductive type first semiconductor layer, and electrically connecting one of the anode electrode and the cathode electrode to the other main surface of the first semiconductor substrate or the first semiconductor layer. And a step of electrically connecting the other of the anode electrode and the cathode electrode to the other main surface of the second semiconductor substrate or the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 11, further comprising: 21. After the step of preparing each of the first and second semiconductor substrates, there is a step of providing a plurality of high impurity concentration regions on one main surface of the first semiconductor substrate at predetermined intervals. 21. The method of manufacturing a semiconductor device according to claim 11, further comprising: 22. A recess is provided between the plurality of high impurity concentration regions which are separated from each other by a predetermined distance.
The manufacturing method of the semiconductor device described in the above. 23. After the step of preparing each of the first and second semiconductor substrates, there is a step of providing a plurality of high impurity concentration regions on one main surface of the second semiconductor substrate at predetermined intervals. 21. The method of manufacturing a semiconductor device according to claim 11, further comprising: 24. The plurality of high impurity concentration regions are the first
24. The method of manufacturing a semiconductor device according to claim 23, wherein the method is provided corresponding to one main surface that is exposed except for a concave portion defined in the semiconductor substrate.