CN205564760U - Carborundum power semiconductor - Google Patents
Carborundum power semiconductor Download PDFInfo
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- CN205564760U CN205564760U CN201620074515.0U CN201620074515U CN205564760U CN 205564760 U CN205564760 U CN 205564760U CN 201620074515 U CN201620074515 U CN 201620074515U CN 205564760 U CN205564760 U CN 205564760U
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Abstract
The utility model provides a carborundum power semiconductor is through contacting the layer and form silica gate oxide layer on silicon contacting the layer at silicon on the carborundum epitaxial layer for the silicon on silicon contact layer and silica gate oxide layer's silica's crystalline grain phase -match can reduce silica gate oxide layer and the interface trapped charge's on silicon contact layer quantity greatly, improves the mobility of channel carrier, possesses that carborundum power semiconductor is high pressure resistant, the characteristic of high temperature simultaneously again.
Description
Technical field
This utility model belongs to essential electronic element field, relates to semiconductor device, particularly to a kind of silicon carbide power semiconductor devices.
Background technology
Carborundum is as third generation semi-conducting material, there is the superior functions such as broad-band gap, high heat conductance, high breakdown field strength, high saturated velocity, it is suitable for making high temperature high power, high-temperature high-frequency and radioprotective device, it is widely used on various power semiconductor, such as mos field effect transistor (MOSFET) etc..
Fig. 1 is existing SiC semiconductor power device, specifically includes that drain electrode 1, silicon carbide substrates 2, cushion 3, silicon carbide epitaxial layers 4, pwell district 5, contact porose area 6, source area 7, silicon dioxide grid oxide layer 8, polysilicon gate 9, dielectric layer 10, source electrode 11.When silicon dioxide grid oxide layer is formed, generally by forming silicon dioxide grid oxide layer on silicon carbide epitaxial layers in the method that silicon carbide epitaxial layers is thermally grown.But, owing in growth course, silicon dioxide does not mates with the lattice of carbofrax material, the defect electric charges such as substantial amounts of dangling bonds, carbon bunch and Lacking oxygen can be produced in the interface of silicon dioxide grid oxide layer and silicon carbide epitaxial layers and silicon dioxide grid oxide layer, cause SiC semiconductor power devices inversion channel carrier mobility extremely low, influence whether the unlatching of device, pressure etc., reduce device performance.
Utility model content
This utility model is intended at least to solve one of technical problem present in prior art, propose a kind of silicon carbide power semiconductor devices, this silicon carbide power semiconductor devices can reduce the quantity of silicon dioxide grid oxide layer and the interface trapped charge of silicon contact layer, improves the mobility of channel carrier.
In order to realize above-mentioned purpose of the present utility model, embodiment of the present utility model provides a kind of silicon carbide power semiconductor devices, including: silicon carbide substrates；Being formed at the cushion in described silicon carbide substrates front, the conduction type of described cushion is identical with the conduction type of described silicon carbide substrates；Being formed at the silicon carbide epitaxial layers on described cushion and the first well region being formed in described silicon carbide epitaxial layers, the conduction type of described silicon carbide epitaxial layers is identical with the conduction type of described cushion, contrary with the conduction type of described first well region；Being formed at the silicon contact layer on described silicon carbide epitaxial layers and be formed at the second well region of described silicon contact layer both sides, described second well region contacts with described first well region, and the conduction type of described first well region is identical with the conduction type of described second well region；The source area being formed in described second well region of every side with contact porose area, the conduction type of described source area is contrary with the described conduction type contacting porose area；It is sequentially formed at silicon dioxide grid oxide layer, polycrystalline silicon grid layer and the source electrode on described silicon contact layer;It is formed at the drain electrode at the described silicon carbide substrates back side.
According to embodiment of the present utility model, by silicon contact layer on silicon carbide epitaxial layers and on silicon contact layer formed silicon dioxide grid oxide layer, the silicon of silicon contact layer is matched with the lattice of the silicon dioxide of silicon dioxide grid oxide layer, the quantity of silicon dioxide grid oxide layer and the interface trapped charge of silicon contact layer can be greatly reduced, improve the mobility of channel carrier, possess again that silicon carbide power semiconductor devices is high pressure resistant, the characteristic of high temperature simultaneously.
Preferably, described silicon carbide power semiconductor devices also includes dielectric layer, and described dielectric layer is between described polycrystalline silicon grid layer and described source electrode.
Preferably, the material of described dielectric layer is boron-phosphorosilicate glass or polyimides.
Preferably, the doping content of described silicon carbide substrates is 1 × 1018cm-3-2.0×1018cm-3, the doping content of described cushion is 0.5 × 1018cm-3-1.0×1018cm-3, the doping content of described silicon carbide epitaxial layers is 4.6 × 1015cm-3-5.5×1015cm-3。
Preferably, doping type is linear distribution or class Gauss distribution.
Preferably, described contact porose area forms Ohmic contact with described source electrode.
Preferably, the doping content of described source area is 7.6 × 1015cm-3-8.5×1015cm-3。
Preferably, the upper surface of described contact porose area is etched away part, and the thickness being etched away part is 3500A 4500A.
Preferably, the doping content of described silicon contact layer is 1.5 × 1014cm-3-2.5×1014cm-3。
Additional aspect of the present utility model and advantage will part be given in the following description, and part will become apparent from the description below, or is recognized by practice of the present utility model.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present utility model and advantage will be apparent from easy to understand, wherein from combining the accompanying drawings below description to embodiment:
Fig. 1 is the generalized section of existing N-type silicon carbide power semiconductor devices；
Fig. 2 is the generalized section of the N-type silicon carbide power semiconductor devices of this utility model embodiment.
Detailed description of the invention
Of the present utility model embodiment is described below in detail, and the example of described embodiment is shown in the drawings, and the most same or similar label represents same or similar element or has the element of same or like function.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining this utility model, and it is not intended that to restriction of the present utility model.
In description of the present utility model, it will be appreciated that, term " longitudinally ", " laterally ", on " ", D score, " front ", " afterwards ", " left ", " right ", " vertically ", " level ", " push up ", " end " " interior ", " outward ", " just ", orientation or the position relationship of the instruction such as " carrying on the back " are based on orientation shown in the drawings or position relationship, it is for only for ease of description this utility model and simplifies description, rather than indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that to restriction of the present utility model.
In description of the present utility model, unless otherwise prescribed and limit, it should be noted that term " is installed ", " being connected ", " connection " should be interpreted broadly, such as, can be to be mechanically connected or electrical connection, can also be the connection of two element internals, can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, for the ordinary skill in the art, the concrete meaning of above-mentioned term can be understood as the case may be.
It should be noted that, the following embodiment of this utility model all illustrates as a example by N-type silicon carbide power semiconductor devices, for p-type silicon carbide power semiconductor devices, is referred to this utility model embodiment, corresponding change doping type, does not repeats them here.
Fig. 2 is the generalized section of N-type silicon carbide power semiconductor devices in one embodiment of this utility model, is only the size giving each region of signal in figure, and concrete size can be designed according to the requirement of device parameters.N-type silicon carbide power semiconductor devices in Fig. 2 can be implemented as N-type MOSFET.
It can be seen that N-type silicon carbide power semiconductor devices includes in the present embodiment: silicon carbide substrates 102, in the present embodiment, the doping content of silicon carbide substrates 102 is 1 × 1018cm-3-2.0×1018cm-3It is preferably 1.5 × 1018cm-3 。
The front of silicon carbide substrates is formed with cushion 103, and the conduction type of cushion 103 be N-type identical with the conduction type of described silicon carbide substrates 102, the doping content of cushion 103 is 0.5 × 1018cm-3 -1.0×1018cm-3, it is therefore preferable to 0.6 × 1018cm-3, doping type can be linear distribution or class Gauss distribution.
Being formed with silicon carbide epitaxial layers 104 on cushion 103, the doping content of silicon carbide epitaxial layers 104 is 4.6 × 1015cm-3-5.5×1015cm-3, it is therefore preferable to 5 × 1015cm-3；And in silicon carbide epitaxial layers 104, it being formed with the first well region 105, the conduction type of silicon carbide epitaxial layers 104 is N-type with the conduction type of cushion 103, and the conduction type of the first well region 105 is p-type.Wherein, the first well region 105 has two, is symmetrically dispersed in the region near upper surface, the both sides of silicon carbide epitaxial layers 104.
Being formed with silicon contact layer 106 on silicon carbide epitaxial layers 104, the doping content of silicon contact layer 106 is 1.5 × 1014cm-3-2.5×1014cm-3, it is therefore preferable to 2 × 1014cm-3；And it is formed at the second well region 107 of silicon contact layer 106 both sides, the bottom of the second well region 107 and the upper surface of the first well region 105, wherein, second well region 107 of both sides is symmetrically distributed the top of the first well region 105, the conduction type of the first well region 105 and the conduction type of the second well region 107 centered by silicon contact layer 106 and is p-type；
The source area 108 being formed in second well region 107 of every side with contact porose area 109, source area 108 is disposed adjacent side by side with contacting porose area 109, and the conduction type of source area 108 is N-type, and the second well region 107 is p-type, and source area 108 doping content is 7.6 × 1015cm-3-8.5×1015cm-3, it is therefore preferable to 8 × 1015cm-3, contact porose area 109 is p-type, and doping content is 1 × 1014cm-3。
It is sequentially formed at the silicon dioxide grid oxide layer 110 on silicon contact layer 106, polycrystalline silicon grid layer 111 and source electrode 113, specifically, silicon dioxide grid oxide layer 110 covers silicon contact layer the 106, second well region 107 and part contact porose area 109, source electrode 113 covering part source area 108 with contact porose area 109.Preferably.Contact porose area 109 forms Ohmic contact with source electrode 113, and Ohmic contact can reduce surface contacted resistance;Further, it is also possible to by contact porose area 109 upper surface be etched away part, be etched away part thickness be 3500A 4500A, contact hole district 109 so can be made preferably to contact with source electrode 113.And
It is formed at the drain electrode 101 at silicon carbide substrates 102 back side.
According to embodiment of the present utility model, by silicon contact layer on silicon carbide epitaxial layers and on silicon contact layer formed silicon dioxide grid oxide layer, the silicon of silicon contact layer is matched with the lattice of the silicon dioxide of silicon dioxide grid oxide layer, the quantity of silicon dioxide grid oxide layer and the interface trapped charge of silicon contact layer can be greatly reduced, improve the mobility of channel carrier, possess again that silicon carbide power semiconductor devices is high pressure resistant, the characteristic of high temperature simultaneously.
As a preferred implementation of the present utility model, silicon carbide power semiconductor devices also includes 112 layers of medium, dielectric layer 112 is between polycrystalline silicon grid layer 111 and source electrode 113, specifically, dielectric layer 112 covers polycrystalline silicon grid layer 111 and part source area 108, dielectric layer 112 1 aspect affects the performance of silicon carbide power semiconductor devices for preventing foreign matter from entering, still further aspect has certain porefilling capability makes silicon chip surface planarize, and the material of dielectric layer 112 is boron-phosphorosilicate glass or polyimides.
This utility model additionally provides the manufacture method of a kind of N-type silicon carbide power semiconductor devices, wherein N-type silicon carbide power semiconductor devices refers to that silicon carbide substrates 102 is for N-type, in an embodiment of the present utility model, the processing step of N-type silicon carbide power semiconductor devices is as follows:
S11: provide and there is heavily doped N-type silicon carbide substrates 102.
S12: being formed in the front of N-type silicon carbide substrates 102 and have heavily doped cushion 103, this utility model indication front refers to the upper surface of N-type silicon carbide substrates 102, and the back side refers to the lower surface of N-type silicon carbide substrates 102.
S13: form lightly doped silicon carbide epitaxial layers 104 by ion implanting or solid-state source diffusion method on cushion 103；And form the first well region 105 in being engraved in silicon carbide epitaxial layers 104 by light.
S14: form N-type silicon contact layer 106 by deposit on silicon carbide epitaxial layers 104, N-type silicon contact layer 106 is heavy doping, and in N-type silicon contact layer 106, forming p-type the second well region 107 by photoetching, the method for ion implanting, p-type the second well region 107 is for gently to mix；
S15: form N-type source region 108 in p-type the second well region 107 by the method for photoetching, ion implanting and contact porose area 109.
S16: on N-type silicon contact layer 106, forms silicon dioxide grid oxide layer 110 by thermally grown, etching, then forms polysilicon layer 111 on silicon dioxide grid oxide layer 110 by deposit, ion implanting, and by being deposited on polysilicon layer 111 formation dielectric layer 112.
S17: deposit metal is to form source electrode 113 on dielectric layer 112, and source electrode 113 forms Ohmic contact with contacting porose area 109.
S18: thinning N-type silicon carbide substrates 102, forms drain electrode 101 at the back side of N-type silicon carbide substrates 102.The method forming drain electrode 101 is preferably: evaporation.Thinning method can be any substrate thinning technique, specifically can be but not limited to grinding, chemically mechanical polishing, dry etching, electrochemical corrosion or wet etching method, it is preferred to use Ginding process.
Manufacture method according to embodiment of the present utility model, by silicon contact layer on silicon carbide epitaxial layers and on silicon contact layer formed silicon dioxide grid oxide layer, the silicon of silicon contact layer is matched with the lattice of the silicon dioxide of silicon dioxide grid oxide layer, the quantity of silicon dioxide grid oxide layer and the interface trapped charge of silicon contact layer can be greatly reduced, improve the mobility of channel carrier, possess again that silicon carbide power semiconductor devices is high pressure resistant, the characteristic of high temperature simultaneously.
In the description of this specification, the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means that the specific features, structure, material or the feature that combine this embodiment or example description are contained at least one embodiment of the present utility model or example.In this manual, the schematic representation to above-mentioned term is not necessarily referring to identical embodiment or example.And, the specific features of description, structure, material or feature can combine in any one or more embodiments or example in an appropriate manner.
Embodiment the most of the present utility model, it will be understood by those skilled in the art that: these embodiments can carry out in the case of without departing from principle of the present utility model and objective multiple change, revise, replace and modification, scope of the present utility model is limited by claim and equivalent thereof.
Claims (6)
1. a silicon carbide power semiconductor devices, it is characterised in that including:
Silicon carbide substrates；
Being formed at the cushion in described silicon carbide substrates front, the conduction type of described cushion is identical with the conduction type of described silicon carbide substrates；
Being formed at the silicon carbide epitaxial layers on described cushion and the first well region being formed in described silicon carbide epitaxial layers, the conduction type of described silicon carbide epitaxial layers is identical with the conduction type of described cushion, contrary with the conduction type of described first well region；
Being formed at the silicon contact layer on described silicon carbide epitaxial layers and be formed at the second well region of described silicon contact layer both sides, described second well region contacts with described first well region, and the conduction type of described first well region is identical with the conduction type of described second well region；
The source area being formed in described second well region of every side with contact porose area, the conduction type of described source area is contrary with the described conduction type contacting porose area；
It is sequentially formed at silicon dioxide grid oxide layer, polycrystalline silicon grid layer and the source electrode on described silicon contact layer;And
It is formed at the drain electrode at the described silicon carbide substrates back side.
2. silicon carbide power semiconductor devices as claimed in claim 1, it is characterised in that also including dielectric layer, described dielectric layer is between described polycrystalline silicon grid layer and described source electrode.
3. silicon carbide power semiconductor devices as claimed in claim 2, it is characterised in that the material of described dielectric layer is boron-phosphorosilicate glass or polyimides.
4. silicon carbide power semiconductor devices as claimed in claim 1, it is characterised in that the doping type of described cushion is linear distribution or class Gauss distribution.
5. silicon carbide power semiconductor devices as claimed in claim 1, it is characterised in that described contact porose area forms Ohmic contact with described source electrode.
6. silicon carbide power semiconductor devices as claimed in claim 5, it is characterised in that the upper surface of described contact porose area is etched away part, and the thickness being etched away part is 3500A 4500A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620074515.0U CN205564760U (en) | 2016-01-26 | 2016-01-26 | Carborundum power semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620074515.0U CN205564760U (en) | 2016-01-26 | 2016-01-26 | Carborundum power semiconductor |
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| CN205564760U true CN205564760U (en) | 2016-09-07 |
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| CN201620074515.0U Active CN205564760U (en) | 2016-01-26 | 2016-01-26 | Carborundum power semiconductor |
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Effective date of registration: 20191203 Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Patentee after: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address before: BYD 518118 Shenzhen Road, Guangdong province Pingshan New District No. 3009 Patentee before: BYD Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. |
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kwai Chung street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. |