JPH08179999A - Dma transfer data guarantee system - Google Patents

Abstract

PURPOSE: To guarantee transfer data before an error occurs by showing a part where the error occurs when data transfer of DMA system is performed. CONSTITUTION: When a device control module 1 is started up by an instruction from a high-order program, a DMA transfer control part 11 starts the data transfer by DMA transfer, and checks whether or not an overrun error occurs during the DMA transfer, and starts up an error line control part 12 when the overrun error occurs, and after that, completes processing by performing DMA transfer completion processing. The error line control part 12 performs the DMA transfer completion processing, and starts up an error line informing part 13, and after that, completes the processing after writing a data transfer address and data transfer length when the error occurs in a data transfer address/length area 14. The error line informing part 13 informs the occurrence of the error to a device control module 2 by turning on an error line 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer data guarantee system, and more particularly to a general-purpose parallel interface bus (GP).
The present invention relates to a DMA transfer data guarantee method for guaranteeing the transfer data before the error occurs when a data error occurs during the data transfer in the system for performing the data transfer by the DMA method between the device control modules through IB).

[0002]

2. Description of the Related Art Conventionally, when an error occurs during data transfer in a system in which data is transferred by a DMA method between device control modules via GPIB, the device control module on the transmission side detects only the occurrence of an overrun error. Was there.

Therefore, when a data error occurs in an instruction during data transmission / reception, all the data in the instruction are invalid.

[0004]

When a data error occurs in a data transmission / reception command during data transfer in this conventional system, all the data in this command, that is, the data transferred before the occurrence of this error are invalidated. There was a problem that

An object of the present invention is to provide a DMA transfer data guarantee system capable of guaranteeing the transfer data before the error occurrence by indicating the error occurrence point during the data transfer of the DMA system.

[0006]

According to the present invention, a GPI
In a system for transferring data by a DMA method between device control modules through B, an error line is provided between the device control modules, each device control module controls a data transfer of the GPIB, and a DMA transfer control unit, A storage area for storing the transfer data address and the transfer data length generated during the transfer, an error line control unit for writing the transfer data address and the transfer data length in this storage area, and an error for controlling the ON / OFF of the error line A DMA transfer data guarantee system characterized by including a line notification unit is obtained.

When the device control module on the transmission side is activated by an instruction from a higher-order program, the DMA transfer control unit starts data transfer by the DMA method, and an overrun error occurs during this DMA transfer. If so, the error line control unit is activated, and the error line control unit activated by the DMA transfer control unit activates the error line notifying unit and the data transfer address and data transfer length at the time of occurrence of this error. Is written in the storage area, and the error line notification unit activated by the error line control unit turns on the error line, thereby obtaining a DMA transfer data guarantee system.

Further, when the device control module on the receiving side is activated by an instruction from the upper program,
The DMA transfer control unit starts the data transfer by the DMA method, and when the occurrence of an overrun error is notified from the error line during the DMA transfer, activates the error line control unit, and the DMA transfer control unit The activated error line control unit activates the error line notification unit and writes the data transfer address and the data transfer length at the time of this error in the storage area, and the error line activated by the error line control unit The notifying unit turns off the error line to obtain the DMA transfer data guarantee system.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a system block diagram showing an embodiment of a DMA transfer data guarantee system of the present invention, FIG. 2 is a flow chart for explaining the operation of a device control module on the transmission side in this embodiment, and FIG. 7 is a flowchart for explaining the operation of the device control module on the receiving side in the embodiment.

2 (a) and 3 (a) show the operations of the DMA transfer control units 11 and 21 in FIG. 1, respectively, and FIGS. 2 (b) and 3 (b) respectively show FIG.
2 shows the operation of the error line control units 12 and 22, and FIGS. 2 (c) and 3 (c) show the operation of the error line notification units 13 and 23 in FIG. 1, respectively.

Referring to FIG. 1, the system of this embodiment comprises a device control module 1 on the transmission side and a device control module 2 on the reception side, which are connected by a general-purpose parallel interface bus (GPIB) 4. The data transfer by the DMA method is performed between the device control modules 1 and 2 through GPIB4.

An error line 3 is provided between the device control modules 1 and 2, and each device control module 1 and 2 controls the data transfer of GPIB 4 by D.
MA transfer control units 11 and 21, data transfer address / length areas 14 and 24 for storing transfer data addresses and transfer data lengths generated during data transfer, and data transfer to these data transfer address / length areas 14 and 24. Error line control unit 12, 22 for writing the transfer data address and the transfer data length generated in
And error line notification units 13 and 23 for performing on / off control of the error line 3.

Next, the operation of this embodiment will be described.

First, referring also to FIGS. 1 and 2, when the device control module 1 transmits data, when the device control module 1 is activated by an instruction from a higher-order program (application program), D
The MA transfer control unit 11 starts data transfer by DMA transfer (step S111).

Whether or not an overrun error has occurred during this DMA transfer is checked by a generally known method (S112), and if no overrun error has occurred (N in S112), DMA transfer is performed. It is checked whether or not it has ended (S113).

If the DMA transfer is not completed (N in S113), the process returns to S112 to recheck whether an overrun error has occurred. If Y in S113, that is, if the DMA transfer is completed, a DMA transfer end process is performed (S115).

Further, if Y in S112, that is, if an overrun error has occurred, the error line control unit 12
Is started (S114), DMA transfer end processing is then performed (S115), and the process ends.

The error line control unit 12 activated by the DMA transfer control unit 11 in S114 performs DMA transfer end processing (S121), and an error for controlling the error line 3 of the dedicated line for notifying the device control module 2 of the error occurrence. The line notification unit 13 is activated (S122), and then the data transfer address and the data transfer length at the time of the error occurrence are written in the data transfer address / length area 14 (S123), and the process ends.

The error line notification unit 13 activated by the error line control unit 12 in S122 turns on the error line 3 (S131) and ends.

As described above, in this embodiment, when the transmission error occurs, the data transfer address and the data transfer length information up to that point can be acquired, and the data transferred before the error occurrence time is guaranteed to be invalid. To be done.

Referring also to FIGS. 1 and 3, when the device control module 2 receives data, when the device control module 2 is activated by an instruction from a higher-order program (application program), D
The MA transfer control unit 21 starts data transfer by DMA transfer (step S211).

The error line 3 is checked to see if an overrun error has occurred during this DMA transfer (S21
2) If the error occurrence is not notified by the error line 3 (N in S212), it is checked whether the DMA transfer is completed (S213).

If the DMA transfer is not completed (N in S113), the process returns to S212 to recheck the error line 3 to see if an error has been notified. S213
If Y, that is, when the DMA transfer is completed, the DMA transfer end process is performed (S215).

When Y is determined in S212, that is, when the error occurrence is notified by the error line 3, the error line control unit 22 is activated (S214), and then the DMA transfer end process is performed (S215), and the process ends.

The error line control unit 22 activated by the DMA transfer control unit 21 in S214 performs DMA transfer end processing (S221), and an error for controlling the error line 3 of the dedicated line for notifying the device control module 1 of the error occurrence. The line notification unit 23 is activated (S222), and then the data transfer address and the data transfer length at the time of error occurrence are set in the data transfer address / length area 24 (S223), and the process ends.

The error line notification unit 23 activated by the error line control unit 22 in S222 turns off the error line 3 (S231) and ends.

As described above, in this embodiment, when the reception error occurs, the data transfer address and the data transfer length information up to that point can be obtained, and the data transferred before the error occurrence time is guaranteed to be invalid. To be done.

Next, the data resending operation by an instruction from the upper program when an error occurs will be described with reference to FIGS.

FIG. 4 is a flow chart for explaining the data resending operation by the instruction from the upper program when an error occurs in the embodiment shown in FIG.

When an error occurs (S311), DMA
The transfer control unit 11 acquires the data transfer address and the data transfer length at the time of the error from the data transfer address / length area 14 through the error line control unit 12 and the error line notification unit 13 according to the instruction from the upper program (S312), The data transfer address and the data transfer length to be transferred next are calculated based on the values of the data transfer address and the data transfer length (S
313), and thereafter, the data is retransferred through GPIB4 (S314).

[0032]

As described above, the present invention is based on GPIB.
In a system in which data is transferred between device control modules via the DMA system, an error line is provided between the device control modules, and each device control module has a DMA transfer control unit for controlling the data transfer of GPIB, and an error line occurs during the data transfer. A storage area for storing the transfer data address and the transfer data length, an error line control unit for writing the transfer data address and the transfer data length in this storage area, and an error line ON,
Since the transfer data address and the transfer data length when an error occurs in the transmission / reception side during the DMA transfer can be acquired by providing the error line notification unit for performing the off control, the data before the time of the error occurrence is acquired. Has the effect that can be guaranteed.

[Brief description of drawings]

FIG. 1 is a system block diagram showing an embodiment of a DMA transfer data guarantee system of the present invention.

FIG. 2 is a flowchart for explaining the operation of the device control module on the transmission side in this embodiment.

FIG. 3 is a flowchart for explaining the operation of the device control module on the receiving side in the present embodiment.

FIG. 4 is a flowchart for explaining a data resend operation by an instruction from a higher-order program when an error occurs in the embodiment shown in FIG.

[Explanation of symbols]

 1, 2 Device control module 3 Error line 4 General-purpose parallel interface bus (GPIB) 11, 21 DMA transfer control unit 12, 22 Error line control unit 13, 23 Error line notification unit 14, 24 Data transfer address / length area

Claims (3)

[Claims] 1. A system for performing a DMA-based data transfer between device control modules through a general-purpose parallel interface bus, wherein an error line is provided between the device control modules, and each device control module transfers data through the general-purpose parallel interface bus. A DMA transfer control unit that controls the transfer data address, a storage area that stores a transfer data address and a transfer data length generated during the data transfer, and an error line control unit that writes the transfer data address and the transfer data length in the storage area, An error line notifying unit for performing on / off control of the error line.
MA transfer data guarantee method. 2. When the device control module on the transmission side is activated by an instruction from a higher-level program, the D
The MA transfer control unit starts the data transfer by the DMA method, and if an overrun error occurs during the DMA transfer, activates the error line control unit,
The error line control unit activated by the A transfer control unit activates the error line notification unit, writes the data transfer address and the data transfer length at the time of this error in the storage area, and activates from the error line control unit. 2. The DMA transfer data guarantee system according to claim 1, wherein the error line notification unit that has turned on turns on the error line. 3. When the device control module on the receiving side is activated by an instruction from a higher-level program, the D
The MA transfer control unit starts the data transfer by the DMA method, and when the occurrence of an overrun error is notified from the error line during the DMA transfer, activates the error line control unit and activates from the DMA transfer control unit. The error line control unit starts the error line notification unit and writes the data transfer address and the data transfer length at the time of occurrence of the error in the storage area,
3. The DMA transfer data guarantee system according to claim 1, wherein the error line notification unit activated by the error line control unit turns off the error line.