JPH08179802A - Actuator controller - Google Patents

Abstract

PURPOSE: To prevent a control system from becoming unstable by the high-order resonance of an actuator without generating any initial inverse response in the control system and without increasing a sampling frequency even in the case of digital control. CONSTITUTION: A displace deviation detecting part 2 detects deviation between a displace position P1 of an actuator 1 and a disk focal point position P2 and outputs a signal S1 showing the value of the deviation. An A/D converting part 3 digitizes the signal S1 and outputs it deviation value data D1. Based on the deviation value data D1, a digital arithmetic part 4 generates control value data D2 with digital arithmetic. A timing control part 5 applies delay time Td satisfying the condition of 0<Td<1/fs to the control value data D2 for controlling the actuator, for which a high-order resonance frequency is fs, and outputs the result as control value data D4. The control value data D4 are supplied through a D/A converting part 6, gain control part 7 and driving amplifier 8 to the actuator 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an actuator control device, and more particularly to an actuator control device capable of stabilizing a mechanical higher-order resonance generated at the time of controlling an actuator of an optical head.

[0002]

2. Description of the Related Art An optical head of an optical disk recording / reproducing apparatus is provided with a focus actuator and a track actuator for adjusting the focus of a focused beam and for tracking, respectively. Controlling.

However, since the actuator has mechanical resonance characteristics, the operation of the control system becomes unstable. As means for preventing the instability of the control system due to such higher-order resonance of the actuator, JP-A-61-234403 describes
As disclosed in the publication, an all-pass filter for delaying only the open loop phase by a predetermined amount without changing the open loop gain of the control system is inserted into the control system loop.

For example, it is assumed that an open-loop characteristic diagram and a Nyquist diagram of a control system are as shown in FIGS. 13 and 14 when an all-pass filter is not inserted. Here, the higher-order resonance point of the actuator is 12 kHz, and the control system open-loop phase is inverted near this resonance frequency. Further, as shown in the Nyquist diagram of FIG. 14, the gain margin of the control system is about 1 dB. In general, when the gain margin is about 1 dB, it is not practical to cope with a change in performance of the actuator over time or disturbance, and the control system may oscillate. Therefore, it is desirable to secure about 10 dB as the gain margin of the control system.

If an all-pass filter having the circuit shown in FIG. 11 and having the characteristics shown in FIG. 12 is inserted into the control system, for example, the open-loop characteristics and the Nyquist diagram of the control system are as shown in FIG. 16 and FIG. That is, by inserting the all-pass filter, the open-loop gain does not change, but only the open-loop phase is delayed. Therefore, as shown in the Nyquist diagram shown in FIG. 16, a gain margin of the control system can be secured about 10 dB. The control system can be stabilized against the higher-order resonance of the actuator.

[0006]

As described above, when stabilizing the high-order resonance of the actuator by using the all-pass filter, there are the following problems.

1. Since the initial response of the control system occurs in the opposite direction, good control performance cannot be obtained.

For example, if the all-pass filter has the circuit configuration shown in FIG. 11, the transfer function is (-s + p ₀ ) / (s + p ₀ ) ... (1). However, p ₀ = 1 / CR> 0, s: Laplace operator Now, if the step response of the equation (1) is obtained with p ₀ = 2π × 14400, as shown in FIG. It occurs in the opposite direction. This is because the initial motion of the system is strongly influenced by the differential term s in the numerator polynomial of the transfer function of the all-pass filter, and the response of the system settles in the opposite direction to the coefficient sign of s in the steady state. The initial reverse response of the control system output excites the initial reverse response of the actuator output. As described above, in the control system including the conventional all-pass filter, good control performance cannot be expected in the initial response of the system.

2. It is difficult to realize a digital control system by digital calculation.

Consider realizing the all-pass filter of the equation (1) in a digital control system on the premise of digital operation.

Now, using the zero-order hold in equation (1), z
When converted, the formula (2) is obtained.

[0012]

However, T: sampling period The gain of the equation (2) can be obtained as the following equation (3) by using the relation of z = exp (sT).

[0014]

Ω = 2πf, f: frequency The condition that the gain of equation (3) becomes 0 dB is p ₀ = 0 o
r T = 0 or ω × T = 2πn (n = 0, 1, 2,
…) Therefore, in order not to change the open loop gain of the control system for arbitrary p ₀ and ω,
In order to set the gain of Expression (3) to 0 dB, it is necessary to set the sampling period T to be sufficiently short.

FIG. 18 shows the sampling frequency (1 / T).
(3) when is set to 60, 240, 960 kHz
(Where p ₀ = 2π × 1)
4400). As shown in FIG. 18, in order to make the all-pass filter discretized so that the gain variation is within negligible 1 dB, the sampling frequency is about 1 MHz, and it is necessary to increase the sampling frequency to about 70 times the pole of the filter. There is.

Generally, the higher-order resonance point of the actuator is
It exists at a frequency higher than the control frequency band of the control system.
A practical sampling frequency is a frequency that is 5 to 20 times the control frequency band. Therefore, in order to realize the all-pass filter for stabilizing the high-order resonance in the digital control system, a sampling frequency higher than the sampling frequency required for the desired control frequency band is required. Further, if the sampling frequency becomes higher, higher performance of the digital arithmetic circuit is required, so that the cost of the control system increases significantly, which is difficult to realize in practice.

An object of the present invention is to prevent the control system from becoming unstable due to the higher-order resonance of the actuator without causing an initial reverse response in the control system and increasing the sampling frequency in digital control. It is an object of the present invention to provide an actuator control device which can be realized without performing.

[0019]

An actuator control device of the present invention detects a deviation between a displacement position and a set position of an actuator and outputs a deviation value signal, and a displacement deviation detecting means according to a pulse of a sampling cycle. A / D conversion means for digitizing the deviation value signal and outputting it as deviation value data, and digital operation means for generating control value data for controlling the actuator from the deviation value data,
Timing adjusting means for providing a delay time Td satisfying 0 <Td <1 / fs to the control value data when a higher-order resonance frequency of the actuator is fs, and the actuator based on output data of the timing adjusting means And driving means for driving.

In the above configuration, the timing adjusting means may divide the input clock and output a pulse of the sampling period, and may reset the input clock in response to an output pulse of the frequency divider. A counter that counts, a comparator that compares a count value of the counter with a set value set from the outside and outputs a pulse when they match, and a plurality of cascade-connected flip-flops; A first delay circuit that operates in response to an output pulse and delays the control value data output by the digital operation means for a predetermined time; and a flip-flop that operates in response to a pulse output by the comparator. A second delay circuit for delaying the control value data output from the one delay circuit for a predetermined time.

[0021]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a focus or tracking actuator of an optical head is controlled and a sampling frequency 60
It shows a device that digitizes at kHz and controls by digital operation.

The displacement deviation detecting section 2 detects a deviation between the displacement position P1 of the actuator 1 and the disk focus position P2, and generates an electric signal S1 indicating the deviation value. A-D
The conversion unit 3 outputs a clock pulse CLK having a sampling period.
According to 2, the signal S1 indicating the deviation value is digitized and converted into deviation value data D1.

The digital operation section 4 has a well-known digital filter such as a discretized lead-lag filter, lag-lead filter, low-pass filter, etc., and inputs the deviation value data D1 and past values of the deviation value data D1. Based on the past value of the control value data D2 to be output, the product operation with a preset filter constant is executed to generate the control value data D2 so that the desired control system open loop gain frequency characteristic is obtained.

The timing adjustment section 5 is provided for the same purpose as the conventional all-pass filter, and delays the control value data D2 by a predetermined time without changing the gain, and outputs the control value data D4. I do. Details will be described later.

The DA converter 6 converts the control value data D4 into an analog signal. The gain adjusting unit 7 is composed of, for example, a variable resistor, and adjusts the control system open loop DC gain. The drive amplifier 8 power-amplifies the output of the gain adjustment unit 7 and drives the actuator 1 of the optical head.

FIG. 2 is a block diagram showing an example of the timing adjusting section 5. FIG. 3 is a timing chart showing the operation.

The frequency divider 51 divides the operation clock of the digital operation section 4 as an input clock CLK1 and outputs a clock pulse CLK2 having the same period T as the sampling frequency (60 kHz). In the present embodiment, as shown in FIG. 3, the input clock CLK1 having the period h is divided into 1/8 and the clock pulse CL having the sampling period (T = 8h) is obtained.
K2. This clock pulse CLK2 is applied to the counter 52 and the plurality of flip-flop circuits FF0-F0.
Fn. Further, it is also supplied to the A / D converter 3 and used as a sampling pulse.

The counter 52 has a clock pulse CLK2
To count the input clock CLK1 and output the count value CN (“0” to “7”) to the comparator 53. The comparator 53 compares the count value CN with a setting value k supplied from the outside, and outputs a clock pulse CLK3 when they match. For example, when the set value k supplied from the outside is "4", the clock pulse CLK3 is output when the count value CN of the counter 52 becomes "4" as shown in FIG.

A delay circuit 54 composed of n + 1 stages of flip-flop circuits FF0 to FFn connected in cascade.
Updates the input data according to the clock pulse CLK2, delays the control value data D2 by n cycles (n · 8h) of the clock pulse CLK2, and outputs the control value data D3.

The delay circuit 55 is a flip-flop circuit, and the control value data D3 is generated according to the clock pulse CLK3.
Is updated, and the control value data D3 is delayed by a predetermined time (4h) and output as control value data D4. Therefore, the total delay time is (n · 8h + 4h).

Generally, it is assumed that the period of the input clock CLK1 is h, the frequency is divided by m (m is an integer of 1 or more) in the frequency dividing section 51, and the set value in the comparator 53 is k (k = k).
0, 1, 2,..., M−1) and n + 1 flip-flop circuits in the delay unit 54, the delay time Td given to the control value data D1 by the timing adjustment unit 5 is Td = (n · m · h) + (k · h) (5)

FIG. 4 shows the gain and phase characteristics of the timing adjusting section 5 when Td = 18 μs.
FIG. 5 shows a step response in this case.
If the actuator higher-order resonance frequency is fs (Hz), the delay time Td may be set to 0 <Td <1 / fs. With this configuration, the same function as that of the all-pass filter in the conventional example can be realized without increasing the sampling frequency and without generating an initial reverse response.

Now, the control system open loop gain and open loop phase when the timing adjusting section 5 is not inserted in the control system are as shown in FIG. 6, and the Nyquist diagram is shown in FIG. It is supposed to be like this.
That is, a higher-order resonance point (fs = 12 kHz) of the actuator exists near the frequency at which the open-loop phase is inverted,
It is assumed that the gain margin of the control system is only about 1 dB.

When the timing adjusting section 5 is inserted in such a control system, the open loop gain and open loop phase of the control system are as shown in FIG. 8, and the Nyquist diagram is as shown in FIG. become. That is, since the open loop phase of the control system at the actuator higher-order resonance point is delayed,
As shown in (1), the gain margin of the control system can be secured about 10 dB, and the control system can be stabilized against the higher-order resonance of the actuator.

In this embodiment, the operation clock of the digital operation section 4 is used as the input clock CLK1, but a clock having an arbitrary cycle Tc satisfying 0 <Tc <1 / fs can be used. .

FIG. 10 is a block diagram showing another embodiment of the timing adjustment unit.

The timing adjustment section 9 has a shift register composed of n + 1 stages of register circuits, and has a cycle H
By shifting the control value data D2 according to the clock pulse CLK4, the control value data D2 can be output as the control value data D3 with a delay of n cycles of the clock pulse CLK4.

That is, the delay time Td given to the control value data D1 by the timing adjustment section 9 is as follows: Td = n · H (6)

Here, if the actuator higher-order resonance frequency is fs (Hz), 0 <Td is set as the delay time Td.
It may be set to <1 / fs.

[0041]

As described above, according to the present invention, in order to prevent instability of the control system due to higher-order resonance of the actuator, control value data for controlling the actuator whose higher-order resonance frequency is fs is used. And 0 <Td <1 / f
By providing the timing adjustment unit that provides the delay time Td that satisfies s, no initial reverse response occurs, and there is no need to increase the sampling frequency.
The control system can be easily stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a timing adjustment unit illustrated in FIG. 1;

FIG. 3 is a timing chart showing an operation of a timing adjustment unit 5;

FIG. 4 is a diagram illustrating an example of gain and phase characteristics of a timing adjustment unit 5;

FIG. 5 is a diagram showing a step response of the timing adjustment unit 5;

FIG. 6 is a diagram illustrating an open-loop gain and an open-loop phase of a control system when the timing adjustment unit 5 is removed.

FIG. 7 is a Nyquist diagram of a control system when the timing adjustment unit 5 is removed.

FIG. 8 is a diagram showing an open-loop gain and an open-loop phase of a control system when a timing adjusting unit 5 is inserted.

FIG. 9 is a Nyquist diagram of the control system when the timing adjustment unit 5 is inserted.

FIG. 10 is a block diagram showing another embodiment of the timing adjustment unit shown in FIG. 1;

FIG. 11 is a circuit diagram illustrating an example of a conventional all-pass filter.

FIG. 12 is a diagram showing characteristics of the all-pass filter shown in FIG.

FIG. 13 is a diagram illustrating an open-loop gain and an open-loop phase of a control system when an all-pass filter is not inserted.

FIG. 14 is a Nyquist diagram of a control system when an all-pass filter is not inserted.

FIG. 15 is a diagram showing an open-loop gain and an open-loop phase of a control system when an all-pass filter is inserted.

FIG. 16 is a Nyquist diagram of a control system when an all-pass filter is inserted.

FIG. 17 is a diagram showing a step response of the all-pass filter shown in FIG.

FIG. 18 is a diagram illustrating gain and phase characteristics with respect to a sampling frequency when an all-pass filter is realized by discretization.

[Explanation of symbols]

 1 Actuator 2 Displacement deviation detection unit 3 A-D conversion unit 4 Digital operation unit 5, 9 Timing adjustment unit 8 Drive amplifier 51 Frequency divider 52 Counter 53 Comparator 55, 54 Delay circuit CLK1 Input clock (cycle h) CLK2 Clock pulse (Sampling cycle T) CN output value of the counter 52 D1 deviation value data D2-D4 control value data S1 signal indicating deviation value

Claims (2)

[Claims] 1. A displacement deviation detecting means for detecting a deviation between a displacement position of an actuator and a set position and outputting a deviation value signal, and the deviation value signal digitized in accordance with a pulse of a sampling cycle to obtain deviation value data. Output A-D
Conversion means, digital operation means for generating control value data for controlling the actuator from the deviation value data, and 0 <Td <1/0 for the control value data when the higher-order resonance frequency of the actuator is fs. An actuator control device comprising: a timing adjusting unit that provides a delay time Td that satisfies fs; and a driving unit that drives the actuator based on output data of the timing adjusting unit. 2. The frequency adjusting device according to claim 1, wherein the timing adjusting unit divides an input clock and outputs a pulse having the sampling period, and counts the input clock by resetting according to an output pulse of the frequency divider. A counter, a comparator for comparing the count value of the counter with a set value set from outside and outputting a pulse when they match, and a plurality of cascade-connected flip-flops, the output pulse of the frequency divider; A first delay circuit that operates in response to the control signal data and delays the control value data output by the digital operation means for a predetermined time, and a flip-flop that operates in response to a pulse output by the comparator. 2. The actuator control device according to claim 1, further comprising a second delay circuit that delays the control value data output from the delay circuit for a predetermined time.