JPH07121932A - Light-pulse-width correction circuit in magneto-optical disk drive apparatus - Google Patents

Abstract

PURPOSE:To effect a fine adjustment of a light-pulse width arbitrarily and simply without increasing the cost of a light-pulse-width correction circuit in a magneto-optical disk drive apparatus. CONSTITUTION:A reference clock (a) is input to a phase comparator 51 for a PLL circuit 50, and a phase-adjusted reference clock (b) whose phase is delayed by DELTAt from the reference clock (a) is output by a VCO 56. An encoder 42 generates a fundamental light pulse (c) on the basis of the reference clock (a). By an exclusive OR circuit 61, an inverter 62, a D-flip-flop 63 and a logical sum circuit 64, a corrected light pulse (f) whose pulse width is by DELTAt wider than the fundamental light pulse (c) is generated on the basis of the reference clock (a), the phase-adjusted reference clock (b) and the fundamental light pulse (c). The offset voltage of the VCO 56 is adjusted by an offset-voltage-adjustment preset resistance 55, and the pulse width of the corrected light pulse (f) is fine adjusted arbitrarily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write pulse width correction circuit for a magneto-optical disk drive device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of the structure of a magneto-optical disk drive device. In FIG. 3, 1 is a SCSI controller connected to a SCSI interface, 2 is a buffer RAM, 3 is a CPU, 4 is a ROM, and 5
Is a RAM, 6 is an encoder / decoder, 7 is a write pulse width correction circuit, 8 is a laser control circuit, 9 is a laser diode, 10 is a photodetector, 11 is a read circuit, 12 is a servo control circuit, 13 is a body detector,
14 is a driver circuit, 15 is a focus actuator, 16 is a tracking actuator, 17 is a linear motor, 18 is a mechanism sensor, 19 is a loading motor, 20 is a spindle motor drive circuit, 2
Reference numeral 1 is a magneto-optical disk.

The write pulse of the magneto-optical disk drive device is generated in synchronization with the reference clock of the system, but the width of the write pulse needs to be corrected according to the characteristics of the medium, the number of revolutions and the like. . The circuit for that purpose is the write pulse width correction circuit 7.

The write pulse width is basically about several tens to 60 ns, and the correction value is about 5 ns to 15 n.
It is usual to widen the s pulse width, but this correction value is an extremely small value.

FIG. 4 shows the configuration of a write pulse width correction circuit 7 in a conventional magneto-optical disk drive device. Figure 4
, 31 is the signal line of the basic write pulse A, 3
Reference numeral 2 is a 15 ns delay line, and 33 is an OR circuit.

For example, as shown in FIG. 5, the pulse width is 54
When the basic write pulse A of ns is supplied, the write pulse B delayed by 15 ns is generated by the 15 ns delay line 32. The basic write pulse A and the delayed write pulse B are supplied to the logical sum circuit 33, and the logical sum is taken to obtain the corrected write pulse C having a pulse width of 69 ns.

[0007]

In the conventional case, there is a problem that the delay line is expensive. There is also a problem that the delay time width is fixed and cannot be adjusted arbitrarily. In order to be able to make fine adjustments, a large number of delay lines are required, which leads to a significant increase in cost, and there is a problem in that adjustments are troublesome.

The present invention was devised in view of such circumstances, and a magneto-optical disk drive device capable of arbitrarily and easily fine-adjusting a write pulse width without causing a significant increase in cost. It is an object of the present invention to provide a write pulse width correction circuit.

[0009]

A write pulse width correction circuit of a magneto-optical disk drive device according to the present invention receives a reference clock and generates a basic write pulse having a cycle of an integral multiple of the reference clock. The phase-adjusted reference clock having the same frequency as the reference clock and delayed from the reference clock by a predetermined time
A PLL circuit for outputting from the CO, and means for generating a corrected write pulse having a pulse width wider than the basic write pulse by the delay time based on the reference clock, the basic write pulse, and the phase-adjusted reference clock, PL
Means for varying the offset voltage applied to the VCO in the L circuit.

[0010]

The delay time Δt of the phase-adjusted reference clock output from the VCO with respect to the reference clock can be changed by changing the offset voltage applied to the VCO in the PLL circuit. Therefore, the pulse width of the corrected write pulse whose pulse width is wider than the basic write pulse by the delay time Δt can be changed by adjusting the offset voltage.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a write pulse width correction circuit of a magneto-optical disk drive device according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block circuit diagram showing the configuration of a write pulse width correction circuit. In FIG. 1, 41 is a system reference clock generation circuit that generates a system reference clock a, 42 is an encoder for generating a basic write pulse c based on the system reference clock a, 51 is a phase comparator, 52 is a charge pump, 53 is a low pass filter, 54 is an offset voltage adder, 55 is a phase offset voltage adjustment semi-fixed resistor (variable resistor), and 56 is a VCO.
(Voltage Controlled Oscillator), 50 is a PLL (Phase Locked Loop) circuit including the above elements 51 to 56. Also,
61 is an exclusive OR circuit, 62 is an inverting circuit, 63 is a D flip-flop, and 64 is an OR circuit.

FIG. 2 is a timing chart for explaining the operation. The system reference clock a output from the reference clock generation circuit 41 is the phase comparator 5 in the encoder 42, the exclusive OR circuit 61 and the PLL circuit 50.
Input to 1. Phase comparator 51, charge pump 5
2, in the PLL circuit 50 including the low-pass filter 53 and the VCO 56, the offset voltage adjustment semi-fixed resistor 55 is adjusted to adjust the offset voltage applied to the VCO 56 via the offset voltage adder 54. The phase-adjusted reference clock b is shifted in phase from the system reference clock a by Δt. This delay time Δt can be finely adjusted steplessly by the offset voltage adjusting semi-fixed resistor 55.

The phase-adjusted reference clock b has the same frequency as the system reference clock a. The encoder 42 generates a basic write pulse c based on the input system reference clock a. The basic write pulse c is usually called a "3T signal" having a cycle three times as long as the system reference clock a, and is an example of the write pulse.

System reference clock a and Δ from this
The phase-adjusted reference clock b delayed by t is passed through the exclusive OR circuit 61 and the inverting circuit 62 to generate the latch signal d, and the latch signal d is input to the clock input terminal of the D flip-flop 63. Further, the basic write pulse c from the encoder 42 is input to the data input terminal of the D flip-flop 63. Then, the Q output terminal of the D flip-flop 63 outputs the phase-adjusted write pulse e delayed by Δt from the basic write pulse c. The phase-adjusted write pulse e and the basic write pulse c from the encoder 42 are combined with the logical sum circuit 64.
By passing the light source through the
Therefore, the corrected write pulse f having a wide pulse width can be obtained.

Data is written to the magneto-optical disk by the corrected write pulse f. The pulse width of the post-correction write pulse f can be finely adjusted steplessly by the offset voltage adjusting semi-fixed resistor 55 in the PLL circuit 50.

[0017]

As described above, according to the present invention, the write pulse width with respect to the magneto-optical disk can be arbitrarily and easily finely adjusted with a relatively simple circuit structure without increasing the cost. .

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of a write pulse width correction circuit of a magneto-optical disk drive device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing an example of a configuration of a magneto-optical disk drive device.

FIG. 4 is a circuit diagram showing a configuration of a write pulse width correction circuit of a conventional magneto-optical disk drive device.

FIG. 5 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 41 ... System reference clock generation circuit 42 ... Encoder 50 ... PLL circuit 51 ... Phase comparator 52 ... Charge pump 53 ... Low-pass filter 54 ... Offset voltage adder 55 ... Offset voltage adjustment semi-fixed resistor 56 ...... VCO (voltage controlled oscillator) 61 …… Exclusive OR circuit 62 …… Inversion circuit 63 …… D flip-flop 64 …… OR circuit a …… System reference clock b …… Reference clock after phase adjustment c …… Basic write pulse d …… Latch signal e …… Phase adjusted write pulse f …… Corrected write pulse Δt …… Delay time

Claims (1)

[Claims] 1. A means for inputting a reference clock to generate a basic write pulse having a cycle that is an integral multiple of the reference clock, and inputting the reference clock, having the same frequency as the reference clock, and for a predetermined time from the reference clock. A PLL circuit that outputs a delayed phase-adjusted reference clock from the VCO, and a pulse circuit that is wider in pulse width by the delay time than the basic write pulse based on the reference clock, the basic write pulse, and the phase-adjusted reference clock A write pulse width correction circuit for a magneto-optical disk drive device, comprising: a means for generating a write pulse; and a means for varying an offset voltage applied to a VCO in the PLL circuit.