JPH0734539Y2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is an audio system capable of switching between reproduction at a prescribed reproduction (normal reproduction) speed and reproduction at twice the normal reproduction (double speed reproduction) speed. The present invention relates to a PLL circuit that generates a read clock signal for a disc reproducing device.

(Prior Art) In a conventional PLL circuit for generating a clock for reading information from a disc of a CD player compatible with 2 × speed, a separate voltage control oscillator (VCO) is provided for normal reproduction and 2 × speed reproduction, The VCO was switched according to the switching of each playback mode. In the CD player shown in FIG. 4, 10a and 10b are these voltage controlled oscillators, which are switched by the switch 13. The switching signal for the switch 13 is given by the system controller 8.

Reference numeral 5 is a signal processing circuit including a phase comparison means (PC) _5-1 .

(Problems to be Solved by the Invention) As described above, according to the prior art, since an audio disc reproducing apparatus capable of reproducing at double speed must have two voltage-controlled oscillators, the free-run frequencies of the voltage-controlled oscillators are different from each other. There is a problem in that the voltage-controlled oscillator must be adjusted and the stability of the oscillation frequency and the like with respect to temperature must be ensured for each voltage-controlled oscillator.

Further, since there are two voltage controlled oscillators, there is a problem in that it is necessary to perform processing such as stopping the oscillation of the voltage controlled oscillator that is not selected because it easily causes a beat.

It is an object of the present invention to provide a PLL circuit which solves the above problems by providing only one voltage controlled oscillator in a double speed audio disc reproducing apparatus.

(Means for Solving the Problem) A PLL circuit of the present invention is a switching instruction means for switching between reproduction of information recorded on an audio disc at a specified reproduction speed and reproduction at a reproduction speed twice the specified reproduction speed. In the audio disc reproducing apparatus that is configured to be selectable in accordance with the instruction by, the PLL circuit that generates the clock signal for reading the information detected from the audio disc, when the oscillation frequency is the reproduction at the specified reproduction speed. A voltage controlled oscillator set to the oscillation frequency of
In response to the output from the switching instructing means, the oscillation frequency of the voltage controlled oscillator is multiplied by 2 in the case of a reproduction instruction at the double reproduction speed, and is output, and in the case of a reproduction instruction at the prescribed reproduction speed. It is characterized in that it is provided with a multiplication means for outputting without multiplying by two, and outputs the output of the multiplication means for phase comparison.

Furthermore, the gain of the low-pass filter at the time of reproduction at the specified reproduction speed may be made higher than the gain at the time of reproduction at twice the reproduction speed.

(Operation) In the PLL circuit of the present invention constructed as described above, the oscillation frequency of the voltage-controlled oscillator is set to the frequency at the time of reproduction at the specified reproduction speed, and by the multiplication means, at the time of reproduction at the double reproduction speed. The oscillation frequency of the voltage controlled oscillator is doubled and output, and when the playback is performed at the specified playback speed, the oscillation frequency of the voltage controlled oscillator is output without being doubled, so only one voltage controlled oscillator is required. . As a result, the problem when two voltage controlled oscillators are required is solved.

Further, the oscillation frequency of the voltage controlled oscillator is not doubled at the time of reproduction at the specified reproduction speed, but is doubled at the time of reproduction at the doubled reproduction speed. Since the gain of the low-pass filter is reduced when multiplied, the loop gain of the PLL circuit, which increases by multiplying by 2, is compensated.

(Embodiment) Hereinafter, the present invention will be described with reference to an embodiment.

FIG. 1 is a block diagram of an audio disc reproducing apparatus capable of reproducing at double speed using one embodiment of the present invention.

Information 1 is recorded on an audio disc 1. Reference numeral 2 denotes a disk motor, which rotationally drives the clamped audio disk 1. An optical pickup 3 irradiates the audio disc 1 with laser light and reads information from the audio disc 1 according to a change in the amount of reflected light from the audio disc 1. A pickup servo circuit 4 controls the irradiation position of the laser light of the optical pickup 3 based on the change of the reflected light from the audio disc 1 so that the laser light of the optical pickup 3 can always read the information from the audio disc 1.

Reference numeral 5 denotes a signal processing circuit including a phase comparison means 5 _-1 , which receives an information signal read from the audio disc 1 by the optical pickup 3 and compares the information signal with a clock for reading the information signal. The error signal is sent to the low pass filter 9. Also optical pickup 3
The information signal from is decoded in the signal processing circuit 5 and is subjected to error correction and interpolation processing to reproduce the recorded information. 6 is a disk motor drive circuit,
The rotation of the disk motor 2 is controlled so that the audio disk 1 rotates at a speed suitable for the signal processing circuit 5 to process and output the information signal read from the audio disk 1. Reference numeral 7 denotes a DA conversion circuit, which converts the information reproduced by the signal processing of the signal processing circuit 5 from a digital signal to an analog signal and outputs it to the output terminal 12.

A system controller 8 controls the operation of the entire circuit. The low-pass filter 9 integrates and compensates the error signal output from the phase comparison means _5-1 to generate an oscillation control voltage of the voltage controlled oscillator 10. Voltage controlled oscillator
Reference numeral 10 generates a clock signal for reading a signal from the audio disc 1 read by the optical pickup 3. Reference numeral 11 denotes a doubling circuit, which selectively outputs the oscillation output of the voltage controlled oscillator 10, that is, the clock signal, by doubling it according to an instruction from the system controller 8 in response to normal reproduction and double speed reproduction. Or output directly without multiplication.

The operation of the embodiment constructed as above will be described.

An instruction signal is output to the signal processing circuit 5, the low-pass filter 9, the multiplication circuit 11 and the disk motor drive circuit 6 as to whether the system controller 8 performs normal reproduction or double speed reproduction. Since the voltage controlled oscillator 10 always oscillates at the frequency corresponding to the normal reproduction, when the normal reproduction is instructed by the system controller 8, the doubling circuit 11 stops the doubling operation and the oscillation of the voltage controlled oscillator 10 occurs. The output is sent to the signal processing circuit 5. Therefore, the clock signal frequency is adjusted to the frequency for normal reproduction. The low-pass filter 9 selects the compensation characteristic during normal reproduction.

The disc motor drive circuit 6 selects the compensation characteristic during normal reproduction. In this way, the PLL circuit for generating the read clock signal from the audio disc 1 during the normal reproduction is configured, and the read clock signal for the normal reproduction of the audio disc 1 is generated by the PLL circuit. Playback is performed.

Next, when the system controller 8 instructs the double speed reproduction, the signal processing circuit 5 starts the processing of the signal by a clock signal which is double the speed of the normal reproduction. Doubler circuit 11
Then, the oscillation frequency of the voltage controlled oscillator 10 is doubled and sent to the signal processing circuit 5 as a clock signal. The low-pass filter 9 can reduce the gain with respect to the gain during normal reproduction. This is because doubling the oscillation frequency of the voltage controlled oscillator 10 doubles the amount of phase change with respect to the output voltage of the voltage controlled oscillator. The output of the low pass filter 9 is sent to the voltage controlled oscillator 10 as an oscillation control voltage. In this way, the PLL circuit for generating the read clock signal from the audio disc 1 at the time of the double speed reproduction is constructed, and the reading of the audio disc 1 at the time of the double speed reproduction is performed. Further, the disc motor drive circuit 6 selects a compensation characteristic suitable for the double speed reproduction, and controls the rotation of the disc motor 2 to the rotation for the double speed reproduction.

Next, examples of the doubler circuit 11 and the low-pass filter 9 will be shown.

As shown in FIG. 2A, the doubling circuit 11 includes an inverter 9 ₁
To 9 _5, the NAND gate 9 ₆ to 9 ₉ consists of transistors 9 _10, resistor and the integrating circuit 9 ₁₁ to 9 ₁₂ comprising a capacitor. The NAND gates 9 _{6 to} 9 _{9 form} an exclusive OR circuit 9 ₁₃ . The inverter 9 ₁ is an input buffer, and the inverter 9 ₂ is used as an amplifier. The inverter 9 ₃ inverts the output of the inverter 9 ₂ and sends it to the exclusive OR circuit 9 ₁₃ . The output of the inverter 9 ₃ delays through the integrating circuit 9 _11, the output of the integrating circuit 9 ₁₁ inverts and sends to the inverter 9 _5, are sent to the exclusive OR circuit 9 _13. Here, the delay time by the integrating circuit 9 ₁₁ is set to a time shorter than 1/2 cycle of the oscillation output of the voltage controlled oscillator 10.

On the other hand, the output of the inverter 9 ₃ integrates the integrating circuit 9 _12, the output of the integrating circuit 9 ₁₂ is inverted by the inverter 9 _4, the inverter 9
_It is fed back to the input / output of ₂ and integrated circuit 9 ₁₂ and inverter
9 _3, 9 ₅ by return circuit, inversion potential of the inverter 9 ₂ are added DC voltage to the input of the inverter 9 ₂ so that the duty ratio of 50%.

The system controller 8 is normal reproduction to the base of the transistor 9 ₁₀ a voltage of the high potential, when the double-speed reproduction and a voltage of low potential. The collector of the transistor 9 ₁₀ connected to the input terminal of the inverter 9 _5, are to be selectively grounded input terminal of the inverter 9 ₅ by a signal from the system controller 8.

Now, when normal playback is instructed, transistor 9
₁₀ is controlled to the ON state. Therefore, the output of the inverter 9 ₅ is fixed to a high potential (logic "1"). As a result, the NAND gate 9 ₉ output shown in FIG. 2 that controls an oscillation output from the voltage controlled oscillator 10 to a duty ratio 50% (b) is sent to the phase comparator 5 _-1. When double speed reproduction is instructed, 9 ₁₀ is controlled to be in the off state. Therefore, the inverter 9 ₅ outputs a signal obtained by delaying the oscillation output of the voltage controlled oscillator 10 whose duty ratio is controlled to 50% by delaying the delay time of the integrating circuit 9 ₁₁ . As a result, Nand Gate
As shown in FIG. 2 (c), an output obtained by doubling the oscillation frequency of the voltage controlled oscillator 10 is sent from the 9 ₉ to the phase comparison means 5 _-1 .

As shown in FIG. 3, the low-pass filter 9 applies the normal reproduction instruction from the system controller 8 to the voltage applied to the inverting input terminal of the resistor 9, the capacitor 9 ₂ , the operational amplifier 9 ₃ and the operational amplifier 9 ₃ and the double speed reproduction. Switch to switch with instructions
It has 9 ₃ and the gain can be switched between normal playback and double speed playback.

(Effect of the Invention) As described above, according to the present invention, the output of the voltage controlled oscillator is selectively reproduced at the specified reproduction speed and at the reproduction speed twice the specified reproduction speed. Since the frequency is doubled, the voltage controlled oscillator is commonly used in the case of the specified reproduction speed and the case of the doubled reproduction speed.
It can be constructed at low cost. The adjustment of the free-run frequency is also effective if it is performed for one voltage controlled oscillator.

Furthermore, since only one voltage-controlled oscillator is required, the beat that occurs when there are two voltage-controlled oscillators does not occur, and there is also the effect that the design study of the oscillation frequency and the like with respect to temperature can be performed for one voltage-controlled oscillator. .

Furthermore, the gain of the low-pass filter in the case of reproduction at the double speed is reduced compared to the gain of the low-pass filter in case of reproduction at the specified reproduction speed.
This has the effect of compensating for the loop gain of the PLL circuit, which increases due to multiplication.

[Brief description of drawings]

FIG. 1 is a block diagram of an audio disc reproducing apparatus capable of reproducing at double speed using one embodiment of the present invention. FIG. 2 is a circuit diagram and a waveform diagram showing an example of a doubler circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a low pass filter according to an embodiment of the present invention. FIG. 4 is a block diagram of a conventional example. DESCRIPTION OF _SYMBOLS 1 ... Audio disk, 2 ... Disk motor, 3 ... Optical pickup, 4 ... Pickup servo circuit, 5 ... Signal processing circuit, _5-1 ... Phase comparison means, 6 ... Disk motor drive circuit, 7 ... D / A conversion circuit, 8 ... System controller, 9 ... Low-pass filter, 10 ... Voltage controlled oscillator, 11 ...
Doubler circuit.

Claims (1)

[Scope of utility model registration request] 1. Playback of information recorded on an audio disc at a prescribed reproduction speed and 2 of the prescribed reproduction speed.
A PLL circuit that generates a clock signal for reading information detected from an audio disc in an audio disc reproducing device that is configured to be selectable between reproduction at double reproduction speed in response to an instruction from a switching instruction unit, The voltage-controlled oscillator whose frequency is set to the oscillation frequency at the time of reproduction at the specified reproduction speed and the output from the switching instruction means are used to reproduce the oscillation frequency of the voltage-controlled oscillator at the double reproduction speed. When the instruction is given, the output is multiplied by 2 and when the playback instruction is given at the prescribed reproduction speed, the multiplication means is outputted without being multiplied by 2. When the output from the switching instruction means is received, the prescribed reproduction speed is received. And a low-pass filter for increasing the gain at the time of a reproduction instruction by the above-mentioned gain at the time of the reproduction instruction at the double reproduction speed. PLL circuit and outputs the output means to the phase comparator.