JPH0371453U - - Google Patents
Info
- Publication number
- JPH0371453U JPH0371453U JP13251489U JP13251489U JPH0371453U JP H0371453 U JPH0371453 U JP H0371453U JP 13251489 U JP13251489 U JP 13251489U JP 13251489 U JP13251489 U JP 13251489U JP H0371453 U JPH0371453 U JP H0371453U
- Authority
- JP
- Japan
- Prior art keywords
- speed
- playback speed
- pll circuit
- playback
- oscillation frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Rotational Drive Of Disk (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例を用いた２倍速再
生可能なオーデイオデイスク再生装置のブロツク
図。第２図はこの考案の一実施例における２逓倍
回路の１例を示す回路図および波形図。第３図は
この考案の一実施例におけるローパスフイルタの
一例を示す回路図。第４図は従来例のブロツク図
。
１……オーデイオデイスク、２……デイスクモ
ータ、３……光ピツクアツプ、４……ピツクアツ
プサーボ回路、５……信号処理回路、５−１……
位相比較手段、６……デイスクモータ駆動回路、
７……Ｄ／Ａ変換回路、８……システムコントロ
ーラ、９……ローパスフイルタ、１０……電圧制
御発振器、１１……２逓倍回路。
FIG. 1 is a block diagram of an audio disc playback device capable of double speed playback using an embodiment of this invention. FIG. 2 is a circuit diagram and a waveform diagram showing an example of a doubler circuit in an embodiment of this invention. FIG. 3 is a circuit diagram showing an example of a low-pass filter in an embodiment of this invention. FIG. 4 is a block diagram of a conventional example. 1...Audio disk, 2...Disk motor, 3...Optical pickup, 4...Pickup servo circuit, 5...Signal processing circuit, 5-1 ...
Phase comparison means, 6... disk motor drive circuit,
7...D/A conversion circuit, 8...System controller, 9...Low pass filter, 10...Voltage controlled oscillator, 11...2 multiplier circuit.
Claims (1)
を規定の再生速度による再生と前記規定の再生速
度の２倍の再生速度による再生とを切替指示手段
による指示に伴つて選択可能に構成されたオーデ
イオデイスク再生装置において、オーデイオデイ
スクから検出した情報を読み取るためのクロツク
信号を生成するＰＬＬ回路であつて、発振周波数
が前記規定の再生速度による再生のときの発振周
波数に設定された電圧制御発振器と、前記切替指
示手段からの出力を受けて、前記電圧制御発振器
の発振周波数を前記２倍の再生速度による再生指
示のときは２逓倍して出力し、かつ前記規定の再
生速度による再生指示のときは２逓倍せずに出力
する逓倍手段とを備え、逓倍手段の出力を位相比
較へ出力することを特徴とするＰＬＬ回路。 (2) 第１請求項のＰＬＬ回路において、切替指
示手段の出力を受けて、規定の再生速度による再
生のときのゲインを２倍の再生速度による再生の
ときのゲインより増加させるローパスフイルタを
備えたことを特徴とするＰＬＬ回路。[Claims for Utility Model Registration] (1) In accordance with an instruction by a switching instruction means to reproduce information recorded on an audio disc at a specified playback speed and at a playback speed twice the specified playback speed. In an audio disk playback device configured to be selectable, the PLL circuit generates a clock signal for reading information detected from the audio disk, and the oscillation frequency is set to the oscillation frequency when playing back at the specified playback speed. In response to the output from the voltage controlled oscillator and the switching instruction means, the oscillation frequency of the voltage controlled oscillator is doubled and outputted when a reproduction instruction is given at the double reproduction speed; A PLL circuit comprising a multiplier for outputting without doubling when a speed-based reproduction instruction is given, and outputting the output of the multiplier to a phase comparator. (2) The PLL circuit according to claim 1, further comprising a low-pass filter that receives the output of the switching instruction means and increases the gain during playback at a specified playback speed compared to the gain during playback at twice the playback speed. A PLL circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989132514U JPH0734539Y2 (en) | 1989-11-16 | 1989-11-16 | PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989132514U JPH0734539Y2 (en) | 1989-11-16 | 1989-11-16 | PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0371453U true JPH0371453U (en) | 1991-07-19 |
| JPH0734539Y2 JPH0734539Y2 (en) | 1995-08-02 |
Family
ID=31679967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989132514U Expired - Lifetime JPH0734539Y2 (en) | 1989-11-16 | 1989-11-16 | PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0734539Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6441304A (en) * | 1987-08-07 | 1989-02-13 | Toshiba Corp | Pll circuit for disk player |
-
1989
- 1989-11-16 JP JP1989132514U patent/JPH0734539Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6441304A (en) * | 1987-08-07 | 1989-02-13 | Toshiba Corp | Pll circuit for disk player |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0734539Y2 (en) | 1995-08-02 |
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