JP2773822B2 - Automatic gain adjustment circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain adjustment circuit suitable for gain adjustment such as signal processing of a servo system of a video tape recorder.

[Conventional technology]

FIG. 4 shows a capstan servo system of a general video tape recorder. A control signal (CTL signal) is detected from the magnetic tape 4 running by the rotation of the capstan motor 2 through the magnetic head 6, and an FC signal detected through the FG coil 8 is converted into a CP signal through the frequency divider 10.
Extracted as G signal. These CTL signal and CPG signal are applied to an automatic gain adjustment circuit (AGC circuit) 12 and controlled to a constant level, and then applied to a phase servo circuit 14, and a phase servo output is obtained from the phase servo circuit 14.
Although not shown, the output signal of the AGC circuit 12 may be applied to the phase servo circuit 14 through a frequency divider. On the other hand, the FG signal is applied to the speed servo circuit 16, and a speed servo output is obtained from the speed servo circuit 16 based on the FG signal. Capstan drive output is obtained from the driver 18 by each servo output, and the capstan motor 2 is controlled.
The running speed of the magnetic tape 4 is controlled to be constant.

[Problems to be solved by the invention]

By the way, in the AGC circuit installed in such a capstan servo system, conventionally, an amplifier for amplifying the CTL signal is installed, and the output of the amplifier is detected by an absolute value detection or a peak value detection. The linear method of controlling the gain of the control is adopted.

In such an AGC circuit, it is difficult to set an arbitrary gain externally because of linear processing, and since the signal to be handled is an intermittent pulse signal, the attack time and the recovery time for detecting the signal level are reduced. The decision is AG
There were drawbacks such as affecting C performance.

Therefore, the present invention aims to realize arbitrary gain setting and optimize gain control.

[Means for solving the problem]

As shown in FIG. 1, an automatic gain adjustment circuit according to the present invention uses a control signal read from a recording medium as an input signal, and an amplifier (22) for amplifying the input signal.
A resistor circuit formed by connecting a plurality of first resistors (R _{1 to} R ₃₂ ) in series is connected between an output section and an input section of the amplifier, and a first resistor is connected between the input section and a ground point. Two resistors (3
0), the first resistor and the second resistor
A feedback circuit (26) that feeds back an output signal having a resistance ratio to the input side of the amplifier to the input side of the amplifier, and a connection between the first resistance and the second resistance, A plurality of switches (S _{1 to} S ₁₀ ) for selectively changing the resistance value of the second resistor in a stepwise manner with respect to the resistance value of the second resistor; an output level of the amplifier; A first comparator for comparing with a first reference level, generating a first pulse having a pulse width representing a section of the output level exceeding the first reference level, and (405) an output of the amplifier. A level (V1) is compared with a second reference level (V2) set higher than the first reference level, and a pulse width having a pulse width representing the section of the output level exceeding the second reference level is compared. Second comparator that generates two pulses (406) and a plurality of flip-flop circuits are cascaded, a rotation detection signal of the recording medium is applied to a clock input thereof, and the flip-flop is reset by the first pulse. A pulse generating means (D-FF407, 40) which generates a control pulse delayed according to the number of stages of the flip-flop circuit in terms of the period of the rotation detection signal by a logical product of the output of the side and the rotation detection signal.
8, 409 and an AND circuit 411) and the control pulse generated by the pulse generating means, and adds and counts the clock pulse, and receives the second pulse generated by the second comparator from the counted value. A counting means (up-down counter 412) for subtracting and counting the clock pulse; and an open / close signal corresponding to the number of switches indicated by the count value of the count means. The open / close signal selectively opens and closes the plurality of switches. A switch opening / closing means (data matrix 401) for adjusting the amplification gain of the amplifier by changing a resistance ratio of the first resistance to the second resistance according to the output signal level of the amplifier. It is characterized by doing.

[Action]

The feedback circuit 26 of the amplifier 22 includes a plurality of resistors (resistances R ₁ to R ₁ ).
R ₃₂ ), and switches (S _{1 to} S ₁₀ ) are provided as means for selecting the resistors (resistances R _{1 to} R ₃₂ ) from the resistance circuit 28 to the amplifier 22. The switch switch control means (switch control section 40) for controlling the opening and closing of the (S ₁ to S ₁₀₎ is installed, in accordance with the output level of the switch control means (switch control section) 40 in the amplifier 22 counter ( The count value of the up-down counter 412 is increased or decreased, and the switch (S ₁ to
Since opening and closing of the S ₁₀₎ is controlled, the feedback resistor is set stepwise in the feedback circuit 26 in accordance with the output level. By the stepwise setting of the resistance value of the feedback circuit 26, the gain of the amplifier 22 is adjusted in accordance with the output level, and a constant level output is taken out from the amplifier 22.

〔Example〕

FIG. 1 shows an embodiment of the automatic gain adjustment circuit of the present invention.

A magnetic head 6 is installed as a signal source, and the magnetic head 6 reproduces a control (CTL) signal from the running magnetic tape 4. The CTL signal is a pulse having a small amplitude in the positive and negative directions, and is applied to the positive input side of the amplifier 22 through the input terminal 20.

The amplifier 22 is an amplifying unit whose gain is to be adjusted, and is composed of, for example, an operational amplifier. A feedback circuit 26 is provided between the output of the amplifier 22 and the negative input terminal 24 for gain setting. In the feedback circuit 26, a second resistor 30 and a capacitor 32 are provided together with a resistor circuit 28 in which a plurality of resistors are combined. Therefore, amplifier 22
Is adjusted according to the feedback ratio based on the resistance value ratio between the resistor circuit 28 and the resistor 30.

In the resistor circuit 28 of this embodiment, a series circuit of _{32 first} resistors R _{1 to} R _{32 having} the same resistance value is installed as a plurality of resistors. , The negative input m of the amplifier 22 and each point a, b
A plurality of switches S _1, S ₂ ··· S ₁₀ is disposed between the · · j. Switch S ₁ to S ₁₀ is constituted by a transistor, for example, switch S ₁ is used and the resistance R ₁ closed, a portion of the switch S ₂ is closed and the resistor R ₁ resistor R ₂ is a feedback circuit 26 established as a feedback element, also, all of the resistors R ₁ to R ₃₂ is installed in the feedback circuit 26 as a feedback element in the case where all of the switches S ₁ to S ₁₀ is opened, the switch S ₁ ~
The necessary resistance value is set in the feedback circuit 26 stepwise by the resistors R _{1 to} R ₃₂ whose connection is switched by the selective on / off of S ₁₀ . The opening and closing control of each switch S _{1 to} S ₁₀
This is performed by switch control signals SW ₁ , SW _2, ..., SW ₁₀ applied from a decoder matrix 401 as a switch opening / closing means provided in the switch control unit 40.

Then, the CTL signal amplified by the amplifier 22 at an arbitrary amplification gain is applied to a switch control unit 40 for switching the switches S _{1 to} S ₁₀ together with a frequency divider 36 of the rotation control system of the capstan motor 2. The divided output of the frequency divider 36 is applied to the phase servo circuit 14 as a servo input, and the servo output is applied to the capstan motor 2 through the driver 18, so that the rotation of the capstan motor 2 is controlled according to the CTL signal. .

In the switch control unit 40, an inverter 402 and resistors 403 and 404 are provided as a signal inverting circuit in a signal input unit, and the CTL signal from the amplifier 22 is inverted,
Level detection is performed by first and second comparators 405 and 406 provided as signal level detection means.

Different reference levels V ₁ and V ₂ (V ₁ <V ₂ ) are set in the comparators 405 and 406 as comparison values. In the detection of the level of the CTL signal, for example, V ₁ = 3.2 V and V ₂ = 4.0 V are set. If the level of the CTL signal is (a) V ₁ or less, (b) V ₁
If it is less than V ₂ beyond, is set detection mode when exceeding (c) V _2, for example, as shown in A of FIG. 2, beyond the level of the CTL signal is the reference level V ₁ If it is less than the reference level V _2, as shown in B of FIG. 2, compare the output of the high (H) level is obtained as the comparison output from the comparator 405, as shown in C of FIG. 2, the comparator
From 406, a low (L) level comparison output is obtained. In this case, if the CTL signal is below the reference level V ₁ was, the comparison output of the comparator 405 and 406 both go L level. Also,
As shown in D of FIG. 2, if the level of CTL signal exceeds the reference level V _2, as shown in E of FIG. 2, compare the output of both H-level from the comparator 405, 406 is obtained .

The comparison output of the comparator 405 is supplied to D-flip-flop circuits (D-FF) 407, 408,
409 is applied to the reset input R. D-FF407-40
9 is cascade-connected, a CPG signal is applied to an input C through an input terminal 410, and an H-level voltage _VH is applied to a D input of the first stage D-FF407. Therefore,
When the reset is released and the CPG signal shown in FIG. 3G is applied to the input terminal 410, the output shown in FIG. 3I from D-FF407, the output shown in J in FIG. −FF4
From 09, the output indicated by K in FIG. 3 is obtained. And D-
The output of the FF 409 and the CPG signal are applied to an AND circuit 411 to take a logical product, and the CPG signal shown in M of FIG. 3 is obtained with a delay time corresponding to two cycles of the original CPG signal applied to the input terminal 410. Obtained from the AND circuit 411. The CPG signal applied to the input terminal 410 is obtained by dividing the output of the speed servo circuit 16 by the frequency divider 10, as in the circuit shown in FIG.

Since such a delay time is set, the start-up level of the counting up and counting down of the up / down counter 412 has a predetermined width so that frequent ups and downs can be suppressed, and stable and gradual gain adjustment can be performed. It can be carried out.

An up-down counter 412 installed as a counting means for switching the switches S _{1 to} S ₁₀ has an AND
The output of the circuit 411 is a count-up signal, the comparator 406
Is output as a countdown signal. The up / down counter 412 is a decoder matrix 4
It forms the basic data for 01 and switches
S number of bits corresponding to the number of ₁ to S _10, is constituted by 4 bits of the up-down counter in this embodiment.
The clock pulse CLK is counted up and down by the count-up signal and the count-down signal, and the power-on reset signal _Pr is applied to the reset terminal 413.

The count value of the up-down counter 412 is transferred to the decoder matrix 401, the switch control signal SW ₁ to SW ₁₀ for opening and closing the switch S ₁ to S ₁₀ corresponding to the count value of the decoder matrix 401 in the up-down counter 412 is formed It is, are applied to corresponding switches S ₁ to S _10.

Since it is configured as described above, when the level of the CTL signal is the reference level V ₁ or less, each of the comparators 405 and 406 together produce a comparison output of L level, the reset of D-FF407~409 is released state. In this case, the CPG signal applied to the input terminal 410 is delayed by two cycles as shown by M in FIG. 3 from the AND circuit 411 by the delay operation shown by G to K in FIG. 3 by the D-FFs 407 to 409. The obtained CPG signal is obtained and added to the up / down counter 412 as a count up signal.

The up / down counter 412 counts the number of clock pulses CLK based on the count-up signal.
In the decoder matrix 401, the up / down counter 412
The switch control signal SW ₁ to SW ₁₀ occurs according to the count value. For example, switch S by switch control signal SW _5
5 is closed and the resistors R _{1 to} R ₄ are set as feedback elements in the feedback circuit 26.
As long as the switch control signal SW ₆ is generated according to the addition count of 412 and the switch S ₆ is closed, and the addition count continues,
The switches S ₇ , S _8, ... Are selectively switched to increase the resistance value of the feedback circuit 26 to the resistors R _{1 to} R ₄ , R ₅ , R ₆ ,. .

Next, when the level of the CTL signal exceeds the reference level V _1,
The comparator 405 generates an H level comparison output, and the D-FFs 407 to 409 are reset by the comparison output. Therefore, the output from the D-FF 409 is released, the AND circuit 411 generates an L-level output, and the counting of the up / down counter 412 is stopped. As a result, the count value of the up-down counter 412 is maintained, based on the count value, for example, the switch control signal SW ₈ is output from the decoder matrix 401, switch S ₈ is closed amplifier 2
2, a constant gain is set by the resistors R _{1 to} R ₁₂ .

Next, when the level of the CTL signal exceeds the reference level V _2,
Both comparators 405 and 406 generate a comparison output at the H level. The output of comparator 406 is applied as a countdown signal to up / down counter 412, which causes a down count. At this time, since the D-FFs 407 to 409 are reset by the comparison output of the comparator 405, the AND circuit 411 generates an L-level output, and the counting up of the up / down counter 412 is stopped. When the up-down counter 412 performs a subtraction count, the count value is added to the decoder matrix 401 to generate a switch control signal SW ₁ to SW ₁₀ in accordance with the count value of the up the decoder matrix 401 down counter 412. Currently, it is assumed that the switch S ₈ is closed, selectively switched from switch S ₈ to the switch S _7, S ₆ · · ·, resistance values for the feedback circuit 26 is the resistance R ₁₂ to R
₇ , R ₆ ... Gradually decrease, and the amplification gain decreases.

Table 1 shows the opening and closing of the switches S ₁ to S ₁₀ in the case of adjusting and controlling the gain in 11 steps by the resistor R ₁ to R _32, the relationship between the amplification rate set (times) and gain (dB).

As described above, according to the level of the CTL signal, the switch S ₁
By to S ₁₀ is controlled to open and close, the optimum gain resistors R ₁ to R ₃₂ is selected for the feedback circuit 26 of amplifier 22 is set in a range CTL signal reference level V ₁ ~V ₂ Is controlled so that

Basic data for gain setting is up / down counter
Since it is formed by 412, any gain can be easily set from the outside. Moreover, since the counting by the up / down counter 412 is performed in one cycle of the CTL signal,
The attack time and the recovery time are uniquely determined, and when the signal cycle is early or late, a response is made according to the speed, so that a wide signal cycle can be handled.

In the embodiment, the CTL signal of the phase servo system in the video tape recorder has been described as an example. However, the automatic gain adjustment circuit of the present invention can be applied to various signals other than the CPG signal. .

〔The invention's effect〕

As described above, according to the present invention, the opening / closing of the switch is controlled by the switch control means including the counter for increasing or decreasing the count value according to the signal level, and the resistance value for the feedback circuit is changed stepwise by the opening / closing. Therefore, the gain can be easily set externally, and the optimum gain adjustment can be performed in units of the period of the rotation detection signal as a unit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the automatic gain adjustment circuit of the present invention, FIG. 2 is a diagram showing the operation of the comparator of the automatic gain adjustment circuit shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a block diagram showing the operation of a delay circuit in the automatic gain adjustment circuit, and FIG. 4 is a block diagram showing a general capstan servo system in a video tape recorder. 22 Amplifier 26 Feedback circuit 28 Resistor R _{1 to} R ₃₂ First resistor 30 Second resistor S _{1 to} S ₁₀ Switch 401 Decoder matrix (switch open / close means) 405 first comparator 406 second comparator 407, 408, 409 D-FF (pulse generating means) 412 up-down counter (counting means)

Claims (1)

(57) [Claims] An amplifier for amplifying the control signal read from the recording medium, and a resistance circuit formed by connecting a plurality of first resistors in series with an output section of the amplifier. By connecting a second resistor between the input unit and a ground point while connecting the input signal to the input unit, an output signal having a level corresponding to a resistance ratio between the first resistor and the second resistor can be obtained. A feedback circuit that feeds back to the input side of the amplifier; and a feedback circuit that is provided in parallel with the first resistor and selectively switches connection of the first resistor to the second resistor.
A plurality of switches for changing a resistance value of the first resistor side with respect to a resistance value of the second resistor in a stepwise manner; comparing an output level of the amplifier with a first reference level; A first comparator for generating a first pulse having a pulse width representing a section of the output level exceeding a reference level; an output level of the amplifier; and a second reference set higher than the first reference level. Level and compare this second
A second comparator for generating a second pulse having a pulse width representing a section of the output level exceeding the reference level of the above, and a plurality of flip-flop circuits are cascaded, and a rotation detection signal of the recording medium is inputted to a clock input thereof. And the flip-flop is reset by the first pulse, and the logical product of the output of the last stage of the flip-flop circuit and the rotation detection signal is used as a unit of the period of the rotation detection signal. A pulse generating means for generating a control pulse delayed according to the number of stages; receiving the control pulse generated by the pulse generating means, adding and counting clock pulses;
Counting means for receiving the second pulse generated by the comparator and subtracting and counting the clock pulse; and generating an opening / closing signal corresponding to the number of switches represented by the count value of the counting means. A switch opening / closing means for selectively opening and closing the switch, wherein the amplification ratio of the amplifier is changed by changing a resistance ratio of the first resistance to the second resistance according to an output signal level of the amplifier. An automatic gain adjustment circuit for adjusting a gain.