JPH08172151A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08172151A JPH08172151A JP31306194A JP31306194A JPH08172151A JP H08172151 A JPH08172151 A JP H08172151A JP 31306194 A JP31306194 A JP 31306194A JP 31306194 A JP31306194 A JP 31306194A JP H08172151 A JPH08172151 A JP H08172151A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- solder
- island portion
- lead terminal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リード端子に形成され
たアイランド部に半導体チップを半田を介して接続する
といった構造を有するトランジスタ、ダイオード等の半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a transistor or a diode having a structure in which a semiconductor chip is connected to an island portion formed on a lead terminal via solder.
【０００２】[0002]
【従来の技術】一般に、半導体チップをエポキシ樹脂等
からなるモールド部により覆い、該モールド部より複数
のリード端子が突出するタイプの半導体装置は、例え
ば、３端子型のダイオードを例にとり、図７を参照しつ
つ説明すると、次のような構造を有する。2. Description of the Related Art Generally, a semiconductor device of a type in which a semiconductor chip is covered with a mold part made of epoxy resin or the like, and a plurality of lead terminals project from the mold part is shown in FIG. The following structure will be described with reference to FIG.
【０００３】すなわち、このダイオードは、第１リード
端子３１の先端に設けられたアイランド部３２上に、半
導体チップ３３をダイボンディングし、この半導体チッ
プ３３上面に設けられた２つの電極部３４、３５と、こ
れらに対応する第２リード端子３６および第３リード端
子３７との間を、金線等の細い金属線３８によるワイヤ
ボンディングにてそれぞれ電気的に接続したのち、半導
体チップ３３の部分をモールド部３９にてパッケージす
るといった構造を有する。That is, in this diode, a semiconductor chip 33 is die-bonded onto an island portion 32 provided at the tip of the first lead terminal 31, and two electrode portions 34 and 35 provided on the upper surface of the semiconductor chip 33. And the corresponding second lead terminal 36 and third lead terminal 37 are electrically connected by wire bonding with a thin metal wire 38 such as a gold wire, and then the semiconductor chip 33 is molded. It has a structure in which it is packaged in the section 39.
【０００４】上記アイランド部３２と半導体チップ３３
との間には、半田４０が介在している。この半田４０
は、上記半導体チップ３３のダイボンディングの後に、
加熱炉に送り込まれる等して半田４０の融点以上の温度
下に加熱されることにより溶融されて、アイランド部３
２および半導体チップ３３と各々合金化接合される。The island portion 32 and the semiconductor chip 33.
The solder 40 is interposed between the and. This solder 40
After die bonding of the semiconductor chip 33,
The island portion 3 is melted by being heated to a temperature equal to or higher than the melting point of the solder 40 by being sent to a heating furnace.
2 and the semiconductor chip 33 are alloyed and joined.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、半田４
０は、上記合金化時において、一旦溶融されてペースト
状態となった後に、その内部へ収縮する方向に不均一に
流動しつつ固化するので、この流動にともなって半田４
０上の半導体チップ３３を移動させてしまう場合があ
る。この場合、半導体チップ３３は、アイランド部３２
上において、図８（ａ）に示すような回転方向への位置
ずれを起こしたり、図８（ｂ）に示すような横方向への
位置ずれを起こしたりして、該アイランド部３２上にお
ける位置精度が悪くなる。このような位置ずれを起こし
た半導体チップ３３の各電極部３４、３５に対して、ワ
イヤ３８を的確にボンディングすることは難しく、場合
によっては図８（ｃ）に示すように、ワイヤ３８と各電
極部３４、３５との接続面積が小さくなって、その接続
部分での電気抵抗値が大きくなってしまい電気的特性を
悪化させてしまうことがある外、ワイヤ３８と各電極部
３４、３５との未接続を引き起こすこともある。[Problems to be Solved by the Invention] However, the solder 4
At the time of alloying, 0 is solidified while being once melted into a paste state and then inhomogeneously flowing in the direction of contraction to solidify.
The semiconductor chip 33 above 0 may be moved. In this case, the semiconductor chip 33 has the island portion 32.
In the above, the position on the island portion 32 is displaced due to the displacement in the rotation direction as shown in FIG. 8A or the displacement in the lateral direction as shown in FIG. 8B. The accuracy deteriorates. It is difficult to accurately bond the wire 38 to the respective electrode portions 34 and 35 of the semiconductor chip 33 having such a positional deviation, and in some cases, as shown in FIG. In addition to the fact that the connection area with the electrode portions 34 and 35 becomes small and the electric resistance value at the connection portion becomes large, which may deteriorate the electrical characteristics, the wire 38 and the electrode portions 34 and 35 May cause the disconnection of.
【０００６】本発明は、以上のような状況下で考え出さ
れたもので、アイランド部上の半導体チップのボンディ
ング位置をより高精度に維持し、電気的特性の安定した
より信頼性の高い半導体装置を提供することを目的とす
る。The present invention has been devised under the above-mentioned circumstances, and it is possible to maintain the bonding position of the semiconductor chip on the island portion with higher accuracy and to stabilize the electric characteristics and to provide a more reliable semiconductor. The purpose is to provide a device.
【０００７】[0007]
【課題を解決するための手段】この課題を解決するため
に本発明は、上面に複数の電極部を形成した半導体チッ
プと、先端にアイランド部を有し且つ該アイランド部に
前記半導体チップの下面を半田を介して接続した下面側
リード端子と、前記各電極部のそれぞれに接続した複数
の上面側リード端子と、前記半導体チップ、前記下面側
リード端子および前記複数の上面側リード端子を覆うモ
ールド部とを備えた半導体装置において、前記半導体チ
ップの対角方向の２つの隅角部と前記アイランド部との
間にそれぞれ前記半田を設けたことを特徴とする半導体
装置を提供するものである。In order to solve this problem, the present invention is directed to a semiconductor chip having a plurality of electrode portions formed on its upper surface, and an island portion at its tip, and the lower surface of said semiconductor chip at said island portion. A lower surface side lead terminal connected via solder, a plurality of upper surface side lead terminals connected to each of the electrode parts, a mold for covering the semiconductor chip, the lower surface side lead terminal and the plurality of upper surface side lead terminals. In a semiconductor device including a portion, the solder is provided between two diagonal corner portions of the semiconductor chip and the island portion, respectively.
【０００８】[0008]
【発明の作用及び効果】本発明の半導体装置によれば、
半導体チップの対角方向の２つの隅角部とアイランド部
との間にそれぞれ半田を設けたので、各隅角部における
半田は、半導体チップおよびアイランド部に接続される
際に、一旦溶融された後にそれぞれの内部へ収縮する方
向に流動して、各半田上に跨った状態の半導体チップを
互いに引き合うような状態で固化する。この半導体チッ
プを互いに引き合う力は、各半田においてそれぞれの内
部に収縮する方向に不均一に流動して半田上の半導体チ
ップを移動させようとする力を抑制することになる。こ
のため、半導体チップは、アイランド部上で非常に移動
しにくい状態になる。According to the semiconductor device of the present invention,
Since the solder was provided between the two diagonal corners of the semiconductor chip and the island, the solder in each corner was once melted when connected to the semiconductor chip and the island. After that, the semiconductor chips flow inward in the respective contracting directions and solidify the semiconductor chips in a state of straddling each solder so as to attract each other. The force of attracting the semiconductor chips to each other suppresses the force of moving the semiconductor chips on the solder by non-uniformly flowing in the direction of contraction in each solder. Therefore, the semiconductor chip is in a state in which it is extremely difficult to move on the island portion.
【０００９】従って、本発明の半導体装置によれば、ア
イランド部上での半導体チップの接続位置をより高精度
に保てることが可能となり、これにともなって半導体チ
ップに形成された電極部に対するワイヤの接続状態はよ
り良好になる。Therefore, according to the semiconductor device of the present invention, it is possible to maintain the connection position of the semiconductor chip on the island portion with higher accuracy, and accordingly, the wire for the electrode portion formed on the semiconductor chip is connected. The connection will be better.
【００１０】[0010]
【実施例】以下、本発明の一実施例を、半導体装置とし
て３端子型のダイオードを例にとり、図１乃至図４を参
照しつつ説明するが、本発明がこれに限定されることは
ない。図１は、３端子型のダイオードを示す要部斜視図
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4 by taking a three-terminal type diode as an example of a semiconductor device, but the present invention is not limited to this. . FIG. 1 is a perspective view of a main part showing a three-terminal type diode.
【００１１】図１を参照しつつ説明すると、このダイオ
ードは、上面に２つの突起状の電極部１、２を形成した
半導体チップ３と、先端にアイランド部４を有し且つこ
のアイランド部４上に半導体チップ３の下面を半田５を
介して接続した第１リード端子６（下面側リード端子）
と、この第１リード端子６に対向し且つ互いに略平行に
配置された第２リード端子７および第３リード端子８
（上面側リード端子）と、第２リード端子７の先端と電
極部１との間および第３リード端子８の先端と電極部２
との間をそれぞれ従来からのワイヤボンディング方法に
より電気的に接続させた金からなるワイヤ９と、半導体
チップ３、第１乃至第３リード端子６、７、８およびワ
イヤ９を覆うエポキシ樹脂からなるモールド部１０とを
備えたものである。To explain with reference to FIG. 1, this diode has a semiconductor chip 3 having two projecting electrode portions 1 and 2 formed on the upper surface thereof, and an island portion 4 at the tip thereof. First lead terminal 6 (bottom surface side lead terminal) in which the lower surface of the semiconductor chip 3 is connected to the semiconductor chip via solder 5
And a second lead terminal 7 and a third lead terminal 8 facing the first lead terminal 6 and arranged substantially parallel to each other.
(Upper surface side lead terminal), between the tip of the second lead terminal 7 and the electrode portion 1, and between the tip of the third lead terminal 8 and the electrode portion 2.
And a wire 9 made of gold electrically connected to each other by a conventional wire bonding method, and an epoxy resin covering the semiconductor chip 3, the first to third lead terminals 6, 7, 8 and the wire 9. The mold part 10 is provided.
【００１２】上記半田５は、半導体チップ３の対角方向
の２つの隅角部とアイランド部４との間のそれぞれ２つ
の部位に設けられており、図２に示すように、半導体チ
ップ３の隅角部を中心として直径２ｍｍ程度の平面視略
円形状に形成されており、また、その厚み寸法０．１ｍ
ｍ程度となっている。また、この半田５は、Ｓｎ、Ｐｂ
等を含むものであり、従来から用いられているものであ
る。The solder 5 is provided at each of two portions between two diagonal corners of the semiconductor chip 3 and the island portion 4. As shown in FIG. It is formed in a substantially circular shape in plan view with a diameter of about 2 mm centering on the corner portion, and its thickness dimension is 0.1 m.
m. Also, this solder 5 is Sn, Pb
And the like, which are conventionally used.
【００１３】上記モールド部１０には、その両側面の一
方から第１リード端子６が突出し、他方から第２および
第３リード端子７、８が突出している。尚、上記第１乃
至第３リード端子６、７、８は、鉄からなるものであ
り、また、電極部１、２は、銀等からなるものである。
このような構造を有するダイオードは、例えば次のよう
な方法で製造される。The first lead terminal 6 projects from one of both side surfaces of the mold section 10, and the second and third lead terminals 7 and 8 project from the other side. The first to third lead terminals 6, 7, 8 are made of iron, and the electrode parts 1, 2 are made of silver or the like.
The diode having such a structure is manufactured, for example, by the following method.
【００１４】本実施例では、図３に示すような、鉄から
なる金属板より打ち抜いた長尺帯状のリードフレーム１
１を用いる。このリードフレーム１１には、その長さ方
向に沿う左右両縁部に、サイドフレーム１２、１３が形
成されている。サイドフレーム１２には、先端にアイラ
ンド部４を備えた第１リード端子部１４が、また、サイ
ドフレーム１３には、互いに略平行な第２リード端子部
１５および第３リード端子部１６が、それぞれ内向きに
突出し且つ対向するように一体的に形成されている。In this embodiment, as shown in FIG. 3, a long strip-shaped lead frame 1 punched out from a metal plate made of iron.
1 is used. The lead frame 11 has side frames 12 and 13 formed on both left and right edges along the length direction. The side frame 12 has a first lead terminal portion 14 having an island portion 4 at its tip, and the side frame 13 has a second lead terminal portion 15 and a third lead terminal portion 16 which are substantially parallel to each other. They are integrally formed so as to project inward and face each other.
【００１５】このようなリードフレーム１１をその長手
方向に移送する途次において、まず、ペースト状の半田
５を、アイランド部４上面における図４に示す位置に２
カ所塗布する。上記半田５の塗布は、従来から用いられ
ているダイボンディング方法により行われる。具体的に
は、シリンジ１７内に真空状態で収納されたペースト状
の半田５を、シリンジ１７内に空気圧を送入してシリン
ジ１７の先端に接続されたニードル１８から吐出するこ
とにより、アイランド部４上の図４に示すような２つの
部位に塗布される。また、シリンジ１７は、これを移動
させる制御モータ（図示せず）により、アイランド部４
の角部１７を基準位置として予め決められた該アイラン
ド部４上の所望位置へと移動される。During the transfer of the lead frame 11 in the longitudinal direction, first, the paste-like solder 5 is placed at the position shown in FIG.
Apply at several places. The application of the solder 5 is performed by a conventionally used die bonding method. Specifically, the paste-like solder 5 accommodated in the syringe 17 in a vacuum state is supplied with air pressure into the syringe 17 and discharged from the needle 18 connected to the tip of the syringe 17, thereby forming an island portion. 4 is applied to two sites as shown in FIG. 4 above. In addition, the syringe 17 is controlled by a control motor (not shown) that moves the syringe 17, and the island portion 4 is moved.
It is moved to a predetermined position on the island portion 4 which is determined in advance by using the corner portion 17 of the above as a reference position.
【００１６】その後に、半導体チップ３を、その下面に
おける対角方向の２つの隅角部が上記各半田５にそれぞ
れ接続するようにアイランド部４上に載置する。次に、
リードフレーム１１を加熱炉（図示せず）に送り込む等
することにより、半田の融点よりも高い温度に加熱す
る。すると、この加熱により、上記半田５は、溶融して
半導体チップ３とアイランド部４との双方に合金化接合
することになる。After that, the semiconductor chip 3 is placed on the island portion 4 so that the two diagonal corner portions of the lower surface thereof are connected to the solders 5, respectively. next,
The lead frame 11 is heated to a temperature higher than the melting point of the solder by feeding it into a heating furnace (not shown). Then, due to this heating, the solder 5 is melted and alloyed and bonded to both the semiconductor chip 3 and the island portion 4.
【００１７】このとき、半導体チップ３は、溶融状態の
各半田５上で非常にその載置状態が不安定になる。しか
し、このダイオードによれば、半導体チップ３の対角方
向の２つの隅角部とアイランド部４との間の２つの部位
にそれぞれ半田５を設けているので、各隅角部における
半田５は、溶融された後にそれぞれ内部へ収縮する方向
に流動して各半田５上に跨った状態の半導体チップ３を
互いに引き合うような状態で固化される。この半導体チ
ップ３を互いに引き合う力は、各半田５においてそれぞ
れの内部に収縮する方向に不均一に流動して該半田５上
の半導体チップ３を移動させようとする力を抑制するこ
とになる。このため、半導体チップ３は、アイランド部
４上で非常に移動しにくい状態になる。At this time, the mounting state of the semiconductor chip 3 becomes very unstable on the molten solder 5. However, according to this diode, since the solder 5 is provided at each of the two portions between the two diagonal corners of the semiconductor chip 3 and the island portion 4, the solder 5 at each corner is After being melted, the semiconductor chips 3 flow in a direction of contracting inward and straddle each solder 5, and are solidified in a state of attracting each other. The force of attracting the semiconductor chips 3 to each other suppresses the force of moving the semiconductor chips 3 on the solder 5 unevenly by flowing in the shrinking direction in each solder 5. Therefore, the semiconductor chip 3 is in a state in which it is extremely difficult to move on the island portion 4.
【００１８】従って、このダイオードによれば、アイラ
ンド部４上での半導体チップ３の接続位置のずれを低減
することが可能となる。次いで、リードフレーム１１を
加熱炉から取り出した後に、半導体チップ３の電極部
１、２と第２および第３リード端子１５、１６との間と
を従来からのワイヤボンディング方法により、ワイヤ９
にて電気的に接続される。Therefore, according to this diode, it is possible to reduce the displacement of the connection position of the semiconductor chip 3 on the island portion 4. Next, after taking out the lead frame 11 from the heating furnace, the wire 9 is connected between the electrode portions 1 and 2 of the semiconductor chip 3 and the second and third lead terminals 15 and 16 by a conventional wire bonding method.
Electrically connected.
【００１９】このとき、半導体チップ３は、アイランド
部４上での接続位置が高精度に保たれているので、半導
体チップ３に形成された電極部１、２に対するワイヤ９
の接続状態はより良好になる。さらに、上記工程を経た
後に、リードフレーム１１を、従来から用いられるモー
ルド金型（図示せず）間に移送して、半導体チップ３を
覆うように図１に示すような形状のモールド部１０を成
形し、さらに、これも従来から用いられる打ち抜き成形
用の成形金型により、モールド部１０から突出する第１
乃至第３リード端子部１４、１５、１６を分断して、図
１に示すようなダイオードを得るのである。At this time, since the semiconductor chip 3 maintains the connection position on the island portion 4 with high accuracy, the wire 9 for the electrode portions 1 and 2 formed on the semiconductor chip 3 is formed.
The connection status will be better. Further, after the above steps, the lead frame 11 is transferred between conventionally used molding dies (not shown), and the molding portion 10 having a shape as shown in FIG. 1 is formed so as to cover the semiconductor chip 3. The first part that is molded and then protrudes from the mold part 10 by a molding die for punching that is also conventionally used
Thus, the third lead terminal portions 14, 15, 16 are divided to obtain the diode as shown in FIG.
【００２０】本実施例においては、半田５は、半導体チ
ップ３の隅角部を中心とした直径ｍｍ程度の平面視略円
形状に塗布形成されているが、平面視形状についてはこ
れを限定するものでなく、また、塗布形成の大きさにつ
いては半導体チップ３の隅角部を中心として直径１ｍｍ
乃至３ｍｍ程度の範囲内に収まることとが好ましく、直
径２ｍｍ乃至２．５ｍｍ程度の範囲に収まることがより
好ましい。半田５の厚みは、これを限定するものでな
い。In this embodiment, the solder 5 is applied and formed in a substantially circular shape in a plan view having a diameter of about mm centering on the corner of the semiconductor chip 3, but the plan view shape is not limited to this. Also, the size of coating formation is 1 mm in diameter with the corner of the semiconductor chip 3 as the center.
It is preferably within the range of about 3 mm to 3 mm, and more preferably within the range of about 2 mm to 2.5 mm in diameter. The thickness of the solder 5 is not limited to this.
【００２１】また、本実施例においては、半導体装置と
して３端子型のダイオードを例にとっているが、これに
限定するものでなく、図５に示すような半導体チップ１
９上に複数（図５においては３つ）の電極部２０、２
１、２２を形成したものにも適用可能である。この場
合、各電極部２０、２１、２２間の間隔寸法はより幅狭
となるので、ワイヤボンディングする際にアイランド部
２３上における半導体チップ１９の接続位置はより高精
度なものが望まれるが、本発明の半導体装置であれば、
上記半導体チップ１９の接続位置はより高精度なものに
保たれるので、該半導体チップ１９の電極部２０、２
１、２２に対してワイヤボンディングをより高精度に行
うことが可能となる。In this embodiment, the semiconductor device is a three-terminal type diode, but the present invention is not limited to this, and the semiconductor chip 1 as shown in FIG.
A plurality of (three in FIG. 5) electrode portions 20, 2 on the 9
It is also applicable to the case where 1 and 22 are formed. In this case, since the distance between the electrode portions 20, 21 and 22 becomes narrower, it is desired that the connection position of the semiconductor chip 19 on the island portion 23 be higher in accuracy when wire bonding. With the semiconductor device of the present invention,
Since the connection position of the semiconductor chip 19 is maintained at a higher precision, the electrode parts 20, 2 of the semiconductor chip 19 are kept.
It becomes possible to perform wire bonding with higher accuracy on the Nos. 1 and 22.
【００２２】さらに、本実施例においては、半導体チッ
プ上の電極部と上面側リード端子とをワイヤにて電気的
に接続させているが、これに限定するものでなく、図６
に示すように、電極部２４、２５と上面側リード端子２
６、２７とを半田２８を介して直接接続するタイプの半
導体装置に対しても適用可能である。Further, in the present embodiment, the electrode portion on the semiconductor chip and the upper surface side lead terminal are electrically connected by a wire, but the invention is not limited to this, and FIG.
As shown in FIG.
The present invention is also applicable to a semiconductor device of the type in which 6 and 27 are directly connected via solder 28.
【図１】本発明の半導体装置を示す要部斜視図である。FIG. 1 is a perspective view of essential parts showing a semiconductor device of the present invention.
【図２】本発明の半導体装置を示す要部平面図である。FIG. 2 is a main part plan view showing a semiconductor device of the present invention.
【図３】本発明の半導体装置を製造する際に用いるリー
ドフレームを示す要部平面図である。FIG. 3 is a main part plan view showing a lead frame used in manufacturing the semiconductor device of the present invention.
【図４】本発明の半導体装置を製造する途次においてア
イランド部上に半田を塗布する様子を説明する説明図で
ある。FIG. 4 is an explanatory diagram illustrating a state in which solder is applied onto the island portion during the manufacturing of the semiconductor device of the present invention.
【図５】本発明の半導体装置の変形例を示す要部斜視図
である。FIG. 5 is a main part perspective view showing a modified example of the semiconductor device of the present invention.
【図６】本発明の半導体装置の変形例を示す要部斜視図
である。FIG. 6 is a main part perspective view showing a modified example of the semiconductor device of the present invention.
【図７】従来の半導体装置を示す要部斜視図である。FIG. 7 is a main part perspective view showing a conventional semiconductor device.
【図８】従来の半導体装置においてアイランド部上で半
導体チップが位置ずれを起こす様子を説明する説明図で
ある。FIG. 8 is an explanatory diagram for explaining how a semiconductor chip is displaced on an island portion in a conventional semiconductor device.
１ 電極部 ２ 電極部 ３ 半導体チップ ４ アイランド部 ５ 半田 ６ 第１リード端子 ７ 第２リード端子 ８ 第３リード端子 ９ ワイヤ １０ モールド部 １１ リードフレーム １２ サイドフレーム １３ サイドフレーム １４ 第１リード端子 １５ 第２リード端子 １６ 第３リード端子 １７ シリンジ １８ ニードル １９ 半導体チップ ２０ 電極部 ２１ 電極部 ２２ 電極部 ２３ アイランド部 ２４ 電極部 ２５ 電極部 ２６ 上面側リード端子 ２７ 上面側リード端子 ２８ 半田 1 Electrode Part 2 Electrode Part 3 Semiconductor Chip 4 Island Part 5 Solder 6 First Lead Terminal 7 Second Lead Terminal 8 Third Lead Terminal 9 Wire 10 Mold Part 11 Leadframe 12 Sideframe 13 Sideframe 14 First Lead Terminal 15th 2 lead terminal 16 third lead terminal 17 syringe 18 needle 19 semiconductor chip 20 electrode part 21 electrode part 22 electrode part 23 island part 24 electrode part 25 electrode part 26 upper surface side lead terminal 27 upper surface side lead terminal 28 solder
Claims (1)
ップと、先端にアイランド部を有し且つ該アイランド部
に前記半導体チップの下面を半田を介して接続した下面
側リード端子と、前記各電極部のそれぞれに接続した複
数の上面側リード端子と、前記半導体チップ、前記下面
側リード端子および前記複数の上面側リード端子を覆う
モールド部とを備えた半導体装置において、 前記半導体チップの対角方向の２つの隅角部と前記アイ
ランド部との間にそれぞれ前記半田を設けたことを特徴
とする半導体装置。1. A semiconductor chip having a plurality of electrode portions formed on an upper surface thereof, a lower surface side lead terminal having an island portion at a tip thereof and the lower surface of the semiconductor chip being connected to the island portion through solder, In a semiconductor device comprising a plurality of upper surface side lead terminals connected to each of the electrode portions, the semiconductor chip, the lower surface side lead terminals and a mold portion covering the plurality of upper surface side lead terminals, a diagonal of the semiconductor chip A semiconductor device, wherein the solder is provided between each of two corner portions in the direction and the island portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31306194A JPH08172151A (en) | 1994-12-16 | 1994-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31306194A JPH08172151A (en) | 1994-12-16 | 1994-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08172151A true JPH08172151A (en) | 1996-07-02 |
Family
ID=18036748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31306194A Pending JPH08172151A (en) | 1994-12-16 | 1994-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08172151A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261604A (en) * | 2015-11-11 | 2016-01-20 | 扬州扬杰电子科技股份有限公司 | Jumper wire of novel diode module |
-
1994
- 1994-12-16 JP JP31306194A patent/JPH08172151A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261604A (en) * | 2015-11-11 | 2016-01-20 | 扬州扬杰电子科技股份有限公司 | Jumper wire of novel diode module |
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