JPH08167699A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To simplify manufacturing process and reduce manufacturing cost by forming a capacitor insulating film of a trench-type capacitor and a gate insulating film from the same insulating film in the same step when a DRAM cell having the trench-type capacitor is manufactured, and by forming a capacitor plate and gate wiring from the same electrically conductive film in the same step. CONSTITUTION: This manufacturing process comprises steps of, forming a trench in a semiconductor substrate, forming a storage node 5 of a capacitor in an inner surface of the trench, forming a first insulating film 6 on the whole surface of the semiconductor substrate after the formation of the storage node, removing the first insulating film except the storage node region, and forming a second insulating film 7 on the whole surface of the semiconductor substrate thereafter. Further, it comprises steps of, forming a first electrically conductive film 14 on the second insulating film, and forming a plate of the capacitor and gate wiring of 13 of an MOS transistor by patterning the first electrically conductive film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a D-type device having a trench type capacitor.
The present invention relates to a method for forming a RAM (Dynamic Random Access Memory) cell.

[0002]

7 to 10 show a conventional manufacturing process of a DRAM cell having a trench type capacitor. First, as shown in FIG. 7, after forming an element isolation region 2 on a semiconductor substrate 1, a first silicon nitride film 3 having a film thickness of 150 nm and a first silicon oxide film 4 having a film thickness of 700 nm are formed, and lithography and By anisotropic etching, a trench mask having an opening above the trench capacitor formation planned region is formed, and anisotropic etching is used to form a trench in the semiconductor substrate.

Next, an impurity-doped polysilicon film is formed inside the trench, and thermal diffusion is used to form the storage node 5 of the capacitor around the trench. Then, the trench mask (first silicon nitride film 3 and first trench mask 3
The silicon oxide film 4) is removed.

Next, as shown in FIG. 8, the storage node 5 of the above-mentioned capacitor and a capacitor plate 8 to be described later.
In order to insulate and
A second silicon nitride film 6 having a thickness of m and a second silicon oxide film 7 having a thickness of 9 nm are formed. After this, a first 300 nm-thick first film serving as a capacitor plate is formed on the second silicon oxide film 6.
Polysilicon 8 is formed, and part of the first polysilicon 8 (transfer gate MOS transistor formation planned region) is removed by lithography and anisotropic etching.

Next, as shown in FIG. 9, the second silicon nitride film 6 and the second silicon nitride film 6 are formed on the semiconductor substrate 1 except for the inside of the trench.
The silicon oxide film 7 is removed by wet etching and isotropic etching. Thereafter, a third silicon oxide film 9 having a film thickness of 50 nm is formed as a gate insulating film, and second polysilicon 10 is further formed on the third silicon oxide film 9.
Anisotropic etching and wet etching are performed so that the polysilicon 10 is left in the gap inside the trench and the third silicon oxide film 9 on the transistor formation region is removed.

Next, as shown in FIG. 10, the second polysilicon 10 inside the trench and the gate wiring 12 described later are formed.
A fourth silicon oxide film 11 having a film thickness of 15 nm is formed in order to insulate and. After this, a film thickness of 300 is formed on the entire surface of the substrate.
nm third polysilicon 12 is formed, and the third polysilicon 12 is formed by lithography and anisotropic etching.
Is patterned to form the gate wiring 12.

Further, a diffusion layer 16 having the same carrier as that of the storage node 5 is formed between the storage node 5 and the gate wiring 12 to connect the storage node 5 and the gate wiring 12. At the same time, a diffusion layer 16 having the same carrier as the storage node 5 is formed between the gate wirings 12 of the adjacent DRAM cells. Thereafter, a fifth silicon oxide film 17 and a third silicon nitride film 18 are formed on the entire surface of the substrate in order to electrically insulate the gate wiring 12 and a bit line 20 described later, and then as an interlayer insulating film. A sixth silicon oxide film 19 is formed, and a self array contact (S
AC) to form bit lines 20 to complete the DRAM cell.

In the manufacturing process of the DRAM cell as described above, the second silicon nitride film 6 and the second silicon oxide film 7 are formed in order to form the capacitor insulating film of the trench type capacitor.
And the fourth silicon oxide film 11 is formed to form a gate insulating film. Further, in order to form the capacitor plate and the gate wiring, the first polysilicon 8 and the third polysilicon 12 are correspondingly formed and processed.

[0009]

As described above, according to the conventional method of manufacturing a DRAM cell, the capacitor insulating film and the gate insulating film of the trench type capacitor are formed by different insulating films in different steps, and the capacitor plate and the gate are formed. Since the conductive film and the wiring are formed in different steps and processed, the manufacturing process becomes complicated and the manufacturing cost increases.

The present invention has been made to solve the above problems, and when manufacturing a DRAM cell having a trench type capacitor, the capacitor insulating film and the gate insulating film of the trench type capacitor can be formed in the same step, An object of the present invention is to provide a semiconductor device manufacturing method capable of forming a capacitor plate and a gate wiring by the same conductive film in the same process, simplifying the manufacturing process, and reducing the manufacturing cost.

[0011]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a trench in a semiconductor substrate, a step of forming a storage node of a capacitor on an inner surface of the trench, and a step of forming the storage node after the formation of the storage node. Forming a first insulating film on the entire surface of the semiconductor substrate; removing the first insulating film except on the storage node region; and subsequently forming a second insulating film on the entire surface of the semiconductor substrate. And a step of forming a first conductive film on the second insulating film, and a step of patterning the first conductive film to form a plate of the capacitor and a gate wiring of a MOS transistor. To do.

[0012]

A second silicon nitride film for insulating the storage node and the plate of the trench type capacitor is formed, the second silicon nitride film other than on the storage node region is removed, and then the second silicon oxide film is formed. Therefore, the second silicon oxide film also serves to insulate the substrate and the gate wiring.

As described above, the second capacitor insulating film
The silicon oxide film and the gate insulating film are formed in the same process,
Further, since the plate and the gate wiring are formed of the same first polysilicon in the same process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 to 5 are cross-sectional views of a substrate in a manufacturing process of a DRAM cell according to an embodiment of the present invention, showing an example of a plane pattern of a completed DRAM cell.
Is shown in.

First, as shown in FIG. 1, after forming an element isolation region 2 on a semiconductor substrate (for example, a silicon substrate) 1, a first silicon nitride film having a thickness of 150 nm and a thickness of 700 are formed.
A first silicon oxide film having a thickness of 1 nm is formed, a trench mask having an opening above the trench capacitor formation planned region is formed by lithography and anisotropic etching, and a trench is formed in the semiconductor substrate by anisotropic etching.

Next, a polysilicon film doped with impurities is formed inside the trench, and thermal diffusion is used to form the storage node 5 of the capacitor on the inner surface of the trench. Then, the trench mask (first silicon nitride film and first silicon oxide film) is removed.

Next, a second silicon nitride film 6 having a film thickness of 8 nm is formed in order to insulate the storage node 5 of the capacitor from a capacitor plate 14 which will be described later and to improve the breakdown voltage. After this, except inside the trench
The second silicon nitride film 6 is removed by isotropic etching. Thereafter, the storage node 5 of the capacitor and the plate are insulated from each other on the entire surface of the substrate, and the substrate 1
In order to insulate the gate wiring 13 described later from
A second silicon oxide film 7 having a thickness of nm is formed.

Next, as shown in FIG. 2, a third silicon oxide film 13 is formed on the entire surface of the substrate, and the third silicon oxide film 13 is formed in the central portion of the element activation region on the substrate in the word line direction. To be left linearly, that is, to form a step made of the third silicon oxide film 13 on one side of the region adjacent to the gate wiring formation planned region, using lithography and anisotropic etching.

Next, a first polysilicon 14 having a film thickness of 300 nm to be a capacitor plate and a gate wiring is formed on the entire surface of the substrate. After that, a region from the element isolation region 2 between the trenches of the adjacent DRAM cells to the trench central portion is covered with the photoresist 15.

Next, as shown in FIG. 3, the first polysilicon layer 1 is formed in the capacitor plate forming region including the sidewall portion of the third silicon oxide film 13 along the word line direction and the inside of the trench.
Anisotropic etching is performed on the first polysilicon 14 so that 4 is left. The pair of first polysilicons 14 left on the sidewalls of the third silicon oxide film 13 along the word line direction become the gate wirings of the adjacent DRAM cells. The pitch of the gate wiring 14 has a substantially constant value determined by the width of the third silicon oxide film 13.

Next, as shown in FIG. 4, a fourth silicon oxide film 9 having a film thickness of 50 nm is formed on the entire surface of the substrate, a second polysilicon 10 is further formed, and the second polysilicon 10 is formed. Anisotropic etching and wet etching are performed so as to remove the fourth silicon oxide film 9 on the region where the transistor is to be formed, leaving the gap inside the trench.

Next, a diffusion layer 16 having the same carrier as the storage node 5 is formed between the storage node 5 and the gate wiring 14 in order to connect the storage node 5 and the gate wiring 14, and The third silicon oxide film 13 is removed by anisotropic etching.

Next, as shown in FIG. 5, adjacent DRAs
A diffusion layer 16 having the same carrier as the storage node 5 is formed between the gate wirings 12 of the M cell. After that, the DRAM cell is completed by a normal manufacturing process.
That is, in order to electrically insulate the gate wiring 14 and a bit line 20 described later, a fifth silicon oxide film 17 and a third silicon nitride film 18 are formed on the entire surface of the substrate, and then a second interlayer insulating film is formed. A 6 silicon oxide film 19 is formed, and a bit line 20 is formed by self array contact (SAC) to complete a DRAM cell.

According to the method of forming the DRAM cell having the trench type capacitor formed as described above, the second silicon nitride film 6 for insulating the storage node 5 of the capacitor and the plate 14 is formed, and the storage node is formed. Since the second silicon oxide film 7 is formed after removing the second silicon nitride film 6 other than on the region 5, the second silicon oxide film 7 also serves to insulate the substrate 1 and the gate wiring 14. .

As described above, the gate insulating film is formed in the same step as the second silicon oxide film 7 for the capacitor insulating film,
Further, since the plate and the gate wiring are formed by the same first polysilicon 14 in the same process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0026]

As described above, according to the method of manufacturing the semiconductor device of the present invention, the DRA having the trench type capacitor is provided.
When manufacturing the M cell, the capacitor insulating film and the gate insulating film of the trench type capacitor can be formed in the same process, and the capacitor plate and the gate wiring can be formed by the same conductive film in the same process. The cost can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a part of a manufacturing process of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a cross-sectional view showing a step after the step of FIG.

3 is a cross-sectional view showing a step after the step of FIG.

FIG. 4 is a cross-sectional view showing a step after the step of FIG.

FIG. 5 is a cross-sectional view showing a step after the step of FIG.

6 is a diagram showing a plane pattern corresponding to FIG.

FIG. 7 is a cross-sectional view showing a part of the conventional semiconductor device manufacturing process.

8 is a cross-sectional view showing a step after the step of FIG.

9 is a cross-sectional view showing a step after the step of FIG.

10 is a cross-sectional view showing a step after the step of FIG.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Element isolation region, 3 ... First silicon nitride film (trench mask), 4 ... First silicon oxide film (trench mask), 5 ... Storage node, 6 ... Second
Silicon nitride film (capacitor insulating film), 7 ... Second silicon oxide film (capacitor insulating film, gate insulating film), 9 ... Fourth silicon oxide film, 10 ... Second polysilicon, 13 ... Third silicon oxide film, 14 ... first polysilicon (capacitor plate, gate wiring), 16 ... diffusion layer, 17 ... fifth
Silicon oxide film, 18 ... Third silicon nitride film, 19 ... Sixth silicon oxide film, 20 ... Bit line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822 29/78 21/336 H01L 29/78 301 G 301 Y

Claims (2)

[Claims] 1. A step of forming a trench in a semiconductor substrate, a step of forming a storage node of a capacitor on an inner surface of the trench, and a step of forming a first insulating film over the entire surface of the semiconductor substrate after the storage node is formed. A step of removing the first insulating film other than on the region of the storage node, a step of forming a second insulating film on the entire surface of the semiconductor substrate after that, and a step of forming a first conductive film on the second insulating film. A method of manufacturing a semiconductor device, comprising: a forming step; and a step of patterning the first conductive film to form a plate of the capacitor and a gate wiring of a MOS transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the gate wiring, a step made of a third insulating film is formed on one side of a region of the semiconductor substrate adjacent to the gate wiring formation planned region. Forming step, forming the first conductive film on the semiconductor substrate including the step, and leaving the first conductive film only on the sidewall portion of the third insulating film and the capacitor plate formation region portion. And a step of etching the semiconductor device.