JPH08163473A - Image display device - Google Patents

Abstract

PURPOSE: To realize distribution of video signal data to a pulse width modulation(PWM) circuit used for the image display device with configuration of a small circuit scale. CONSTITUTION: The display device is provided with a video signal rearrangement device 500 which changes an address increase/decrease step by a step being a multiple of N of the increase/decrease step at one-preceding horizontal period with respect to a memory and reads out video data of one preceding horizontal scanning as a required sequence by each pulse width modulation(PWM) circuit 137, that is, every N-set of the data through read modified write for each address to rearrange sampling video signals and with a sample-and-hold circuit 501 with a capacity by a 1/9 horizontal valid pattern period holding video signal data from the video signal and rearrangement device 500 to attain distribution of the video signal data to the pulse width modulation (PWM) circuit 137 through configuration of a small circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device in video equipment.

[0002]

2. Description of the Related Art Heretofore, a cathode ray tube has been mainly used as a color television image display element. However, a cathode ray tube has a very long depth compared to a screen, and it is not possible to manufacture a thin television receiver. It was possible.
Therefore, EL display elements, plasma display elements, liquid crystal display elements, and the like have been developed as flat panel display elements, but they are all insufficient in terms of performance such as brightness, contrast, and color reproducibility. Therefore, for the purpose of displaying a high-quality image similar to that of a cathode ray tube on a flat device using an electron beam, the screen on the screen is divided into matrix-shaped sections without any gaps, and an electron beam is generated for each section. 2. Description of the Related Art There is an image display apparatus that deflects and scans a phosphor to emit light to form a color television image as a whole.

An example of the above-mentioned conventional image display device will be described below with reference to the drawings. FIG. 5 is an exploded perspective view of a display element of a conventional image display device.

In FIG. 5, 1 is a back electrode, 2 is a line cathode as an electron beam source, 3 is an extraction electrode, 4 is a signal electrode,
Reference numerals 5 and 6 are focusing electrodes, 7 is a horizontal deflection electrode, and 8 is a vertical deflection electrode.
It is housed in the flat glass plate 10 and the inside of the container is evacuated.

The four corners of the back electrode 1 are chamfered because the bases (not shown) of the supporting frame for the various electrodes and the line cathode 2 are placed.

The line cathodes 2 are stretched in the horizontal direction so as to generate an electron flow that is uniformly distributed in the horizontal direction, and a plurality of such line cathodes 2 are provided in the vertical direction at appropriate intervals. There is. These line cathodes 2 have a structure in which, for example, a surface of a tungsten wire is coated with an oxide cathode material.

The back electrode 1 is formed by coating a conductor on the back glass plate 10 and is provided in parallel with the line cathode 2. The extraction electrode 3 is opposed to the back electrode 1 through the line cathode 2, and the through-holes 1 are provided at appropriate intervals in the horizontal direction.
It consists of a conductive plate having one row on a horizontal line facing each line cathode. The through hole 11 is circular in the embodiment, but may be elliptical or rectangular, or may be slit-shaped.

The signal electrode 4 is composed of a row of vertically elongated conductive plates 12 arranged in a plurality at a position facing each of the through-holes 11 in the extraction electrode 3 with a predetermined interval,
Each conductive plate has a similar through hole 13 at a position facing the through hole 11 of the extraction electrode 3. Through hole 1
The shape of 3 may be an ellipse or a rectangle, or may be an elongated slit in the vertical direction.

The focusing electrode 5 is made of a conductive plate having through holes 14 at positions facing the through holes 13 of the signal electrode 4, respectively. The shape of the through hole 14 may be a circle, an ellipse, or a slit shape. The focusing electrode 6 has a slit hole 15 which is vertically connected at a position facing the through hole 14 of the focusing electrode 5. The shape of the slit hole 15 may be a round hole, an ellipse, or a rectangular shape.

The horizontal deflection electrode 8 is composed of conductive plates 16 and 17 which are connected to each other at two comb-shaped ends which are meshed with each other at an appropriate interval on the same plane.
The space 18 formed between 7 and 7 is opposed to the through slit hole 15 of the focusing electrode 6. As shown in FIG. 5, the vertical deflection electrode 8 has a structure in which conductive plates 19 and 20 connected to each other at the ends, that is, two comb-shaped conductive plates 19 and 20 are in the same plane and are meshed with each other at an appropriate interval. Consists of.

The screen 21 is formed by applying a phosphor 22 which emits light by irradiation of an electron beam to the inner surface of the glass container 9 and adding a metal back layer (not shown) on the phosphor 22.

Further, the extraction electrode 3, the signal electrode 4, and the
Focusing electrodes 5 and 6, horizontal deflection electrode 7, vertical deflection electrode 8
Are bonded together with an insulating adhesive (not shown here) to form an integral electrode block 24.

The operation of the image display device configured as described above will be briefly described. First, the wire cathode 2 is heated by passing a heater current in order to facilitate electron emission. Appropriate voltage is applied to the back electrode 1, the line cathode 2, and the extraction electrode 3 in a heated state to emit a sheet-shaped electron beam from the surface of the line cathode 2. The sheet-shaped electron beam is divided into a plurality of pieces by the through hole 11 of the extraction electrode 3 and becomes a large number of electron beam streams 23.

The passing amount of the electron beam stream 23 is individually adjusted by the signal electrode 4 in accordance with the image signal applied to the signal electrode 4. Next, the electron beam that has passed through the signal electrode 4 passes through the through holes 14, 1 of the focusing electrodes 5, 6.
After being focused and shaped by the electrostatic lens effect of No. 5, the horizontal deflection is performed horizontally and vertically by the potential difference given to the adjacent conductive plates 16 and 17 of the horizontal deflection electrode 7 and the adjacent conductive plates 19 and 20 of the vertical deflection electrode 8. Biased. Further, a high voltage (for example, 10 KV) is applied to the metal back layer of the screen 21, and the electron beam is accelerated to high energy and collides with the metal back, causing the phosphor to emit light.

Next, a main portion of a drive circuit for displaying a television image on this display element will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of a drive circuit of a conventional image display device.

First, the electron beam stream 23 is directed to the screen 21.
A drive portion for irradiating the surface with the light to make the raster emit light will be described.

The power supply circuit 122 is a circuit for applying a predetermined voltage to each electrode of the display element.
A DC voltage is applied to each of the extraction electrode 3, the focusing electrode 5, and the screen 21.

A composite video signal of a television signal is applied to the input terminal 123, and a vertical sync signal V and a horizontal sync signal H are separated and extracted by a sync separation circuit 124. The vertical deflection circuit 140 includes the comb-shaped conductive plates 19 and 20 of the vertical deflection electrode 8.
The vertical deflection signals DV and DV 'are output to the. The horizontal deflection circuit 141 outputs horizontal deflection signals DH and DH ′ to the comb-shaped conductive plates 16 and 17 of the horizontal deflection electrode 7.

On the other hand, the line cathode control circuit 126 includes the line cathode 2
Drive pulses K1, K2, ... K44 are generated. Figure 7
FIG. 4 is an operation waveform diagram of a main part of the drive circuit when the number of line cathodes is 44, the number of horizontal deflection stages is 9, and the number of vertical deflection stages per each line cathode is 5.

As shown in FIG. 7, the DV and DV 'signals change stepwise in opposite directions for each horizontal synchronizing signal H, and the electron beam flow 23 is vertically deflected in five steps by the difference voltage. . The staircase waveforms of DV and DV 'alternately rise and fall because the comb-shaped conductive plates 19 and 20 of the vertical deflection electrode 8 are alternately switched up and down as viewed from the electron beam flow every 5 horizontal scanning periods. Is. Further, regarding the DH and DH 'signals, the electron beam is deflected in the horizontal direction in nine stages by the difference voltage during one horizontal scanning line period.

Further, the line cathode control pulse is K in (FIG. 7).
1, K2, ..., K44, each line cathode line has a low potential only for 5 horizontal scanning periods (hereinafter referred to as 5H period) within the entire vertical period, and electrons are emitted during this low potential period.
During the other period, a high potential is applied so that the electron emission is not performed, and a current is applied to the wire cathode to heat it so that the electron emission may be facilitated during the low potential period. . In this way, during the effective vertical scanning period, electrons are emitted from the upper to lower line cathodes in order for every 5 horizontal scanning periods.

As a result of the above, the electron beam is emitted for 5H periods in sequence from the one above the 44 line cathodes, and each electron beam corresponds to one line from the top to the bottom in 44 sections in the vertical direction. The vertical deflection is sequentially performed, and raster lines are sequentially drawn on the screen 22 from the first line at the upper end to the 220 line at the lower end.

Further, in each raster, each electron beam divided into a plurality of pieces in the horizontal direction is deflected in the horizontal direction in nine steps, and the nine steps are divided into R and R for three pixels in each section on the screen 22. Corresponding to each of the G and B phosphors, they are sequentially irradiated.

Hereinafter, for convenience of explanation, this first pixel is referred to as R.
i, Gi, Bi, and the second pixel is Ri + 1, Gi +
1, Bi + 1, and the third pixel is Ri + 2, Gi + 2, B
i + 2. R for the electron beam for each horizontal section
i, Gi, Bi, Ri + 1, Gi + 1, Bi + 1, Ri
A color television image can be displayed by modulating with the video signals of +2, Gi + 2, and Bi + 2.

Next, the modulation control portion of the electron beam will be described again with reference to FIG.

First, the composite video signal applied to the television signal input terminal 123 is applied to the color demodulation circuit 130 to output R, G, B primary color signals (hereinafter referred to as RGB video signals). The output RGB video signal is A / D
It is digitally converted by the converter 300.

Next, the digitally converted RGB video signal is added to the sample hold circuit group 131. Each sample and hold circuit group 131 has Ri, Gi,
Bi, Ri + 1, Gi + 1, Bi + 1, Ri + 2, Gi
It has nine sample and hold circuits for +2 and Bi + 2. These sample and hold outputs are added to the holding memory set 132, respectively.

The reference clock oscillator 133 is composed of a PLL circuit or the like, and generates a reference clock SCK having a constant phase with respect to the horizontal synchronizing signal H. The reference clock SCK is applied to the timing pulse generating circuit 134, and here, various timing pulses are generated based on the horizontal synchronizing signal H and the vertical synchronizing signal V.

In the leading sample and hold circuit 131,
The sampling of the video signal is started based on the sampling start pulse t1 corresponding to the first pixel in the effective horizontal scanning line period. The sampling start pulse t1 is sequentially transmitted to the next sample and hold circuit by a shift register or the like, and sampling is performed respectively. As a result, each sample and hold circuit group 131 has Ri, Gi, Bi, Ri + 1, Gi + 1, and
The video signals of Bi + 1, Ri + 2, Gi + 2 and Bi + 2 are individually held.

The held video signals are simultaneously transferred to the memory group 132 in synchronization with the horizontal synchronizing signal H after the sample and hold for one line is completed. This held Ri, Gi, Bi, Ri + 1, Gi + 1, Bi +
The signals of 1, Ri + 2, Gi + 2, Bi + 2 are applied to the switch circuit 135. Each switch circuit 135 is controlled by a pulse “H9” obtained by dividing each horizontal period from the timing pulse generation circuit 134 into nine, and Ri, Gi, Bi, Ri + 1, Gi + 1,
The video signals of Bi + 1, Ri + 2, Gi + 2 and Bi + 2 are time-divided every 1/9 horizontal synchronization period and are sequentially output to the pulse width modulation (PWM) circuit 137.

In the pulse width modulation (PWM) circuit 137,
Ri, Gi, Bi, Ri + 1, Gi + 1, Bi + 1, R
A pulse width modulated (PWM) signal electrode control signal V12 is output according to the magnitude of each of the video signals i + 2, Gi + 2, and Bi + 2. Further, the signal electrode control signals are individually applied to the conductive plates 12 of the signal electrodes 4 of the display element. In this way, the horizontal deflection and the switching of the switch circuit 135 are completely synchronized, and as a result of the above, each pixel in the scanning line is luminescently displayed according to the video signal. In this example, this control is sequentially performed for the 5 × 44 220 lines from the upper line, and the television image is displayed.

[0032]

However, according to the above configuration, the sample and hold circuit group needs to have a capacity corresponding to twice the total number of pixels in the effective horizontal scanning line period. This capacity is, for example, 8 bits for each RGB video signal.
, And each RGB sampling number in the effective screen period is 666, then 8 × 666 × 3 × 2
=> 32 kbit. Further, the sample hold circuit is usually a data flip-flop (hereinafter referred to as DFF).
Since it is composed of etc., this is GateArra
If it is configured by y or the like, about 160 kgate is required for the configuration of the 1-bit DFF as 5 gates.

In view of the above problems, the present invention utilizes a readable / writable memory (RAM, hereinafter simply referred to as memory),
By rearranging the order of video signals and sending pixel data to the pulse width modulation (PWM) circuit at appropriate timing,
An object of the present invention is to provide an inexpensive image display device that does not require the large-capacity sample and hold circuit.

[0034]

In order to achieve the above object, an image display device of the present invention comprises a video signal rearranging device comprising a memory and a memory control circuit whose total capacity corresponds to a horizontal effective screen period. And a sample hold circuit for holding the video signal data from the video signal rearranging device, which has a capacity of 1/9 horizontal effective screen period.

[0035]

In the memory, the address increment / decrement step is changed by N times the increment / decrement step of one horizontal period before, and the read-modify-write is performed for each address to convert the video data of one horizontal scan before each pulse width modulation (PWM). ) By reading in the order required by the circuit, i.e. every Nth,
The sampling video signals can be rearranged.

When N = 9 is set, from the video signal rearranging apparatus configured as described above, first, the R pixel at the head of the usually three trio pixels, which is necessary for the pulse width modulation (PWM) circuit, is first of all. A video signal corresponding to 1/9 horizontal effective screen period corresponding to is output sequentially. This video signal (usually 3 for each)
The first trio R pixel data of the trio is sequentially held by the sample hold circuit, and when the hold for the 1/9 horizontal effective screen period is completed, all the held data is transferred to the pulse width modulation (PWM) circuit and pulsed. In the width modulation (PWM) circuit, based on this data, pulse width modulation (P
WM).

During this pulse width modulation (PWM) period, the video signal of the next 1/9 horizontal effective screen period, normally the G pixel of the head trio, is sequentially output from the video signal rearranging device,
Similarly, it is held by the sample hold circuit. By repeating this operation 9 times during the horizontal scanning period, pulse width modulation (PWM) corresponding to a video signal for 3 trios is performed, so that the sample hold circuit has a capacity equivalent to 1/9 horizontal effective scanning line period. Can be displayed.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image display device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a drive circuit of an image display device according to an embodiment of the present invention. In FIG. 1, the same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, reference numeral 500 designates a data division circuit 9.
00 and the memory R / W control circuit 901, the video signal rearrangement circuit rearranges the sampled video signal in the order required by each pulse width modulation (PWM) circuit by using the memory. . FIG. 2 is a timing diagram showing input / output signals of the data division circuit 900.

As shown in FIG. 2, the data division circuit 900
In accordance with the processing by the memory R / W control circuit 901 in the subsequent stage, the R, G, B input video signals are divided into three groups and output. The division of the R, G, B input signals into the three groups in this way will be described later, but the memory R /
This is to match the processing in the W control circuit 901. Further, in the memory R / W control circuit 901, as shown in FIG. 1, three processing circuits of the same configuration are used in parallel with a, b and c for each group.

The operation of the memory R / W control circuit 901 will be described below with reference to the drawings. FIG. 3 shows the memory R
It is a block diagram showing an example of 1 composition of / W control circuit 901a. The memory R / W control circuits 901b and 901c have the same configuration.

In FIG. 3, reference numeral 600 is a data line changeover switch for switching data input / output signals to / from the memory.

Reference numeral 601 denotes a readable / writable memory (RAM)
So, one is one of the number of sampling dots in one horizontal effective screen.
602a, b, c having a capacity of about / 3 are OR circuits, 603a, b, c are 4-bit 9-ary counters,
As shown in the figure, they are connected in three stages. A shift register 604 shifts Q1, Q2, and Q3 outputs for each H pulse. A data flip-flop 605 latches and outputs the data at the fall of the reference clock SCK.
Reference numerals 701 and 702 are a data input terminal and a data output terminal, respectively.

The operation of the video signal rearrangement circuit configured as described above will be described below with reference to FIG. FIG. 4 is an operation waveform diagram showing operation waveforms of the main part of FIG.

The actual trio number of pixels in one horizontal period is 65.
Although the number of trio data is 0 to 750, the number of trio data in one horizontal period is 729 trio, and all the horizontal periods are horizontal effective screen periods for the sake of simplicity. In FIG. 3, V and H represent a vertical synchronization signal (hereinafter, simply referred to as V synchronization) and a horizontal synchronization signal (hereinafter, simply referred to as H synchronization), respectively. The V1, Q2, and Q3 outputs of the shift register 604 are preset to Low, Low, and High, respectively, and the shift operation is repeated every H synchronization as shown in FIG.

Numerals 603a, b, and c are 4-bit 9-ary counters that count 0 to 8 for each SCK, and when they reach 8, a ripple carry output (hereinafter referred to as RCO).
Is output to the ripple carry input (hereinafter, referred to as RCI) of the upper counter. In addition, the memory 601
, The reference clock SCK is connected to the R / W terminal and the reference clock SCK is connected to the data terminal.
Since the input / output of data to / from the memory is switched by the data selection switch 600 controlled by, the read-modify-write operation is performed for each address.

First, the shift register 604 outputs Q1 and Q
2, the operation when the Q3 output is Low, Low, High will be described. At this time, the RCI of the counter 603a is Hi.
Since it is gh, the output Qa repeatedly counts 0 to 8 for each clock SCK as shown in the figure. Also, the counter 60
Since the RCI of 3b is connected to the RCO of the counter 603a via the OR circuit 602a, the counter 60
It counts up each time the RCO of 3a is output. Further, the counter 603c similarly counts up at its upper level.

Thus, the output Q of the shift register 604
When the outputs of 1, Q2 and Q3 are Low, Low and High, the counter 603a operates as a LSB side counter. On the other hand, at this time, d0 to d728 are input to the data input terminal 701 as shown in FIG. 4, and the data is written in the memory 601 in this order.

When the next horizontal scanning line is reached and the horizontal synchronizing signal H is input, the output Q1 of the shift register 604 is output.
, Q2, Q3 outputs shift to High, Low, Low. At this time, the RCI of the counter 603b is High.
Therefore, the output Qb repeatedly counts 0 to 8 for each clock SCK as shown in the figure. Also, the counter 603c
RCI of the OR circuit 6 is added to the RCO of the counter 603c.
Since it is connected via 02b, the counter 603b
Each time the RCO of is output, it counts up. Further, the counter 603a similarly counts up at the upper level.

Thus, the output Q of the shift register 604
When the outputs of 1, Q2 and Q3 are High, Low and Low, the counter 603b operates as an LSB side counter.

On the other hand, at this time, in the memory 601, a read-modify-write operation of reading the memory contents is performed for each address when the reference clock SCK is High, and writing is performed when the SCK is Low. Therefore, as shown in (FIG. 4), the video signal data written in the previous horizontal synchronization period is read from the memory 601 every 9th data as d0, d9, d18, ....

When the next horizontal scanning line is entered and the horizontal synchronizing signal H is input, the shift register 604 output Q1 is output.
, Q2, Q3 outputs are shifted to Low, High, Low, and the counter 603c operates as an LSB side counter. Therefore, from the memory 601, the video signal data written in the previous horizontal synchronization period is output every 9th. To d
0 ', d9', d18 ', ... Are read.

Further, when the horizontal synchronizing signal H is input,
Shift register 604 outputs Q1, Q2, Q3 outputs are Lo
The operation shifts to w, Low, High and returns to the first operation in which the counter 603a operates as the LSB side counter, and similarly, the video signal data written in the previous horizontal synchronization period is read every 9th.

As described above, the address increment / decrement step is changed in the memory at 9 times the increment / decrement step of one horizontal period before, and the read / modify write is performed for each address to obtain the video data of one horizontal scan before. The sampling video signals can be rearranged by reading out the necessary order in the pulse width modulation (PWM) circuit, that is, by reading out every nine.

The operation of the image display apparatus of the present invention will be further described below with reference to FIG. In FIG. 1, reference numeral 234 denotes a timing pulse generation circuit, which generates various timing pulses as in the conventional example, but in the conventional example, the sampling start pulse t1 corresponding to the beginning of the effective horizontal screen period is used as the sampling start pulse. However, here, the pulse signal “H9” having a rate 9 times the horizontal synchronizing period is used.

Reference numeral 501 is a sample and hold circuit. In the sample and hold circuit 131 of the conventional example, Ri, Gi, B are used.
i, Ri + 1, Gi + 1, Bi + 1, Ri + 2, Gi +
2, Bi + 2 and each pulse width modulation (PWM) circuit 137 required a capacity for 9 pixels, but here, each PWM
Each circuit has a capacity of one pixel. Reference numeral 502 is a shift register, and the sample hold start timing is set to "H".
Each sample hold 501 based on 9 "signal pulse
To be distributed and supplied at an appropriate timing.

The operation of the video signal rearrangement circuit configured as described above will be described below with reference to FIG. 1 again.

From the video signal rearrangement circuit 500, first, which corresponds to the R pixel at the beginning of the three trio pixels, which is usually necessary for the pulse width modulation (PWM) circuit 137,
The video signals R1, R4, R7, R10, R13, ... For the / 9 horizontal effective screen period are sequentially output.

This video signal (usually the R pixel of the head trio of each 3 trios) data is sequentially held in the sample hold circuit 501 at the timing from the shift register 502, and the hold for 1/9 horizontal effective screen period is completed. Then, all the held data are simultaneously transferred to the pulse width modulation (PWM) circuit 137 by the "H9" pulse, and in the pulse width modulation (PWM) circuit 137, based on this data, in each signal electrode, the R of the head trio is read. Pulse width modulation (PWM) corresponding to pixels is performed. During this pulse width modulation (PWM) period, the video signal of the next 1/9 horizontal effective screen period, usually the G pixel of the first trio, G1, G4, G7.
Are sequentially output from the video signal rearranging device and are similarly held by the sample hold circuit 501. By repeating this operation 9 times during the horizontal scanning period, pulse width modulation (PWM) corresponding to the video signal for 3 trios is performed, so that the sample hold circuit has a capacity equivalent to 1/9 horizontal effective screen period. It can be displayed.

Further, the total capacity of the memory (RAM) used for rearranging the video signals in the present invention is one horizontal effective screen period, which is 1/2 of the total capacity of the sample and hold circuit in the conventional example. Become. Furthermore, the area occupied by the RAM on the ASIC is usually about 0.5 gate / bit per 1 bit (5 gate / bi if the DFF is used as in the conventional example).
Since it corresponds to t), it is possible to significantly reduce the circuit scale even if the RAM control circuit and the like are taken into consideration.

[0061]

As described above, according to the present invention, a video signal rearrangement device comprising a memory and a memory control circuit whose total capacity corresponds to a horizontal effective screen period, and an image from the video signal rearrangement device. Hold signal data, 1
An inexpensive image display device can be provided by providing a sample hold circuit having a capacity for a / 9 horizontal effective screen period.

[Brief description of drawings]

FIG. 1 is a block diagram of a drive circuit of an image display device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a main part of the image display device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a main part of an image display device according to an embodiment of the present invention.

FIG. 4 is an operation waveform diagram of a main part of the image display device according to the first embodiment of the present invention.

FIG. 5 is an exploded perspective view of a main part of a display element of a conventional image display device.

FIG. 6 is a block diagram of a drive circuit of a conventional image display device.

FIG. 7 is an operation waveform diagram of a main part of a drive circuit of a conventional image display device.

[Explanation of symbols]

 1 Rear Electrode 2 Wire Cathode 3 Extraction Electrode 4 Signal Electrode 5, 6 Focusing Electrode 7 Horizontal Deflection Electrode 8 Vertical Deflection Electrode 9 Front Glass Container 10 Rear Glass Plate 24 Electrode Block 137 Pulse Width Modulation (PWM) Circuit 500 Video Signal Sorting Device 501 sample and hold circuit

Claims (1)

[Claims] 1. A conductor is provided on an inner surface of the back glass plate in a space sandwiched between a front glass container having a phosphor coated therein and a back glass plate closing a rear opening of the front glass container. The pulse width modulation (PWM) is performed by applying a back electrode by a conductive plate, a plurality of line cathodes, a lead electrode composed of a single or a plurality of conductive plates, and a video signal corresponding to each pixel in the scanning line. ) A plurality of signal electrodes, a single or a plurality of focusing electrodes, an electrode block in which horizontal deflection electrodes and vertical deflection electrodes are superposed in front and back, and a control circuit for driving each of the above electrodes by a television signal. In addition to the above, the address increase / decrease step is changed by N times the increase / decrease step of one horizontal period before for each memory in the memory whose total capacity is equivalent to the video data of one horizontal effective screen. A read-modify-write for each address reads out N pieces of video data of one horizontal scan before, and sequentially holds the output of the video signal rearrangement device that rearranges the sampling video signals and the video signal rearrangement device. And a sample-hold circuit for the number of pixels corresponding to the number of the signal electrodes, the sample-hold circuit performs sample-hold for the number of pixels of the signal electrode and then performs pulse width modulation in synchronization with horizontal deflection. An image display device characterized in that pixel data is transferred all at once to a (PWM) circuit.