JP3275591B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for video equipment.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube is mainly used as a color television image display device. However, a cathode ray tube has a very long depth compared to a screen, and it is impossible to manufacture a thin television receiver. It was possible.
Accordingly, EL display elements, plasma display elements, liquid crystal display elements, and the like have been developed as display elements on a flat plate, but all of them are insufficient in performance such as luminance, contrast, and color reproducibility. Therefore, in order to display a high-quality image comparable to a cathode ray tube on a flat panel device using electron beams, the screen on the screen is divided into matrix-like sections without gaps, and the electron beam is applied to each section. 2. Description of the Related Art There is an image display apparatus that emits phosphors by deflection scanning to form a color television image as a whole.

An example of the above-described conventional image display device will be described below with reference to the drawings. FIG. 5 is an exploded perspective view of a display element of a conventional image display device.

In FIG. 5, 1 is a back electrode, 2 is a line cathode as an electron beam source, 3 is an extraction electrode, 4 is a signal electrode,
5 and 6 are focusing electrodes, 7 is a horizontal deflection electrode, and 8 is a vertical deflection electrode.
The container is housed in the positive glass plate 10 and the inside of the container is evacuated.

The reason why the four corners of the back electrode 1 are chamfered is that the base (not shown) of the support frame for the various electrodes and the linear cathode 2 is placed.

The linear cathodes 2 are stretched in the horizontal direction so as to generate an electron flow uniformly distributed in the horizontal direction. A plurality of such linear cathodes 2 are provided in a vertical direction at appropriate intervals. I have. These line cathodes 2 have, for example, a structure in which an oxide cathode material is coated on the surface of a tungsten wire.

The back electrode 1 is formed by applying a conductor on the back glass plate 10, and is provided in parallel with the linear cathode 2. The extraction electrode 3 faces the back electrode 1 via the linear cathode 2 and has through holes 1 provided at appropriate intervals in the horizontal direction.
It consists of a conductive plate having one column on a horizontal line facing each line cathode. The through-hole 11 is circular in the embodiment, but may be elliptical or rectangular, or may be slit-shaped.

The signal electrode 4 comprises a row of a plurality of vertically elongated conductive plates 12 arranged at predetermined positions at positions opposing each of the through holes 11 in the extraction electrode 3.
Each conductive plate has a similar through-hole 13 at a position facing the through-hole 11 of the extraction electrode 3. Through hole 1
The shape of 3 may be an ellipse or a rectangle, or may be a vertically elongated slit.

The focusing electrode 5 is formed of a conductive plate having a through hole 14 at a position facing the through hole 13 of the signal electrode 4 respectively. The shape of the through hole 14 may be a circle, an ellipse, or a slit. The focusing electrode 6 has a slit hole 15 vertically connected to a position facing the through hole 14 of the focusing electrode 5. The shape of the slit hole 15 may be a round hole, an ellipse, or a rectangular shape.

The horizontal deflection electrode 8 is composed of conductive plates 16 and 17 which are connected to each other at two comb-shaped ends which mesh with each other at an appropriate interval on the same plane.
7 is opposed to the through slit hole 15 of the focusing electrode 6. As shown in FIG. 5, the vertical deflection electrode 8 has a structure in which conductive plates 19 and 20 connected at the ends, that is, two comb-shaped conductive plates 19 and 20 are meshed with each other at an appropriate interval in the same plane. Consists of

The screen 21 has a structure in which a phosphor 22 that emits light by irradiation with an electron beam is applied to the inner surface of the glass container 9 and a metal back layer (not shown) is added thereon.

Further, the aforementioned extraction electrode 3, signal electrode 4,
Focusing electrodes 5 and 6, horizontal deflection electrode 7, vertical deflection electrode 8
Are joined with an insulating adhesive (not shown here) to form an integral electrode block 24.

The operation of the image display device configured as described above will be briefly described. First, the line cathode 2 is heated by supplying a heater current to facilitate electron emission. In a heated state, an appropriate voltage is applied to the back electrode 1, the line cathode 2, and the extraction electrode 3 to emit a sheet-like electron beam from the surface of the line cathode 2. The sheet-like electron beam is divided into a plurality of pieces by the through-holes 11 of the extraction electrode 3 to form a large number of electron beam flows 23.

The passing amount of the electron beam stream 23 is individually adjusted by the signal electrode 4 according to the video signal applied to the signal electrode 4. Next, the electron beam that has passed through the signal electrode 4 is applied to the through-holes 14, 1 of the focusing electrodes 5, 6.
5 after being converged and shaped by the electrostatic lens effect of FIG. 5, horizontally and vertically by the potential difference applied to the adjacent conductive plates 16 and 17 of the horizontal deflection electrode 7 and the adjacent conductive plates 19 and 20 of the vertical deflection electrode 8. Be deflected. Further, a high voltage (for example, 10 KV) is applied to the metal back layer of the screen 21, and the electron beam is accelerated to high energy and collides with the metal back to cause the phosphor to emit light.

Next, a main part of a driving circuit for displaying a television image on the display element will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of a driving circuit of a conventional image display device.

First, the electron beam flow 23 is applied to the screen 21.
A driving portion for irradiating light to emit a raster will be described.

The power supply circuit 122 is a circuit for applying a predetermined voltage to each electrode of the display element.
A DC voltage is applied to each of the extraction electrode 3, the focusing electrode 5, and the screen 21.

A composite video signal of a television signal is applied to an input terminal 123, and a vertical synchronizing signal V and a horizontal synchronizing signal H are separated and extracted by a sync separation circuit 124. The vertical deflection circuit 140 includes a comb-shaped conductive plate 19, 20 for the vertical deflection electrode 8.
Output vertical deflection signals DV and DV '. The horizontal deflection circuit 141 outputs horizontal deflection signals DH and DH ′ to the comb-shaped conductive plates 16 and 17 of the horizontal deflection electrode 7.

On the other hand, the linear cathode control circuit 126
, K44 are generated. FIG.
FIG. 5 shows an operation waveform diagram of a main part of the drive circuit when the number of line cathodes is 44, the number of horizontal deflection stages is 9, and the number of vertical deflection stages per line cathode is 5.

As shown in FIG. 7, the DV and DV 'signals change stepwise in directions opposite to each other for each horizontal synchronizing signal H, and deflect the electron beam stream 23 vertically in five steps by the difference voltage. . The staircase waveforms DV and DV 'alternately show rise and fall because the comb-like conductive plates 19 and 20 of the vertical deflection electrode 8 alternately turn up and down every five horizontal scanning periods as viewed from the electron beam flow. It is. The DH and DH 'signals deflect the electron beam in nine levels in the horizontal direction by the difference voltage during one horizontal scanning line period.

The linear cathode control pulse is represented by K in FIG.
Like K1, K2,..., K44, the potential of each of the cathode lines becomes low for only 5 horizontal scanning periods (hereinafter referred to as 5H period) within the entire vertical period, and electrons are emitted during this low potential period.
In other periods, a high potential is applied so as not to emit electrons, and a current is applied to the wire cathode to heat the line cathode so that the electrons can be easily emitted in the low potential period. . As described above, during the effective vertical scanning period, the electron emission is performed in order from the top toward the lower line cathode for every five horizontal scanning periods.

As a result, the electron beams are emitted in order from the top of the 44 line cathodes for 5H periods, and each electron beam is sequentially extended by one line from top to bottom within 44 divisions in the vertical direction. As a result, the raster is sequentially drawn on the screen 22 from the first line at the upper end to the 220 line at the lower end.

Further, in each raster, each electron beam divided into a plurality of parts in the horizontal direction is deflected in nine steps in the horizontal direction, and these nine steps correspond to R, R and R for three pixels in each section on the screen 22. Irradiation is performed sequentially for each of the G and B phosphors.

Hereinafter, for convenience of explanation, this first pixel is referred to as R
i, Gi, Bi, and the second pixel is Ri + 1, Gi +
1, Bi + 1, and the third pixel is Ri + 2, Gi + 2, B
Let it be i + 2. The electron beam for each horizontal section is denoted by R
i, Gi, Bi, Ri + 1, Gi + 1, Bi + 1, Ri
By modulating with +2, Gi + 2, Bi + 2 video signals, a color television image can be displayed.

Next, the modulation control portion of the electron beam will be described again with reference to FIG.

First, the composite video signal applied to the television signal input terminal 123 is applied to a color demodulation circuit 130 to output R, G, B primary color signals (hereinafter referred to as RGB video signals). The output RGB video signal is A / D
The digital conversion is performed by the converter 300.

Next, the digitally converted RGB video signals are applied to a sample and hold circuit set 131. Each sample-and-hold circuit set 131 includes Ri, Gi,
Bi, Ri + 1, Gi + 1, Bi + 1, Ri + 2, Gi
It has nine sample and hold circuits for +2 and Bi + 2. These sample hold outputs are respectively applied to a holding memory set 132.

The reference clock oscillator 133 is constituted by a PLL circuit or the like, and generates a reference clock SCK having a constant phase with respect to the horizontal synchronization signal H. The reference clock SCK is applied to the timing pulse generation circuit 134. Here, various timing pulses are generated based on the horizontal synchronization signal H and the vertical synchronization signal V.

In the first sample and hold circuit 131,
The sampling of the video signal is started based on the sampling start pulse t1 corresponding to the first pixel of the effective horizontal scanning line period. The sampling start pulse t1 is sequentially transmitted to the next sample and hold circuit by a shift register or the like, and sampling is performed. As a result, each sample and hold circuit set 131 has three trio pixels Ri, Gi, Bi, Ri + 1, Gi + 1, Gi + 1,
Each video signal of Bi + 1, Ri + 2, Gi + 2, Bi + 2 is individually held.

The held video signal is simultaneously transferred to the memory set 132 in synchronization with the horizontal synchronizing signal H after the sample and hold for one line is completed. The held Ri, Gi, Bi, Ri + 1, Gi + 1, Bi +
The signals 1, Ri + 2, Gi + 2, and Bi + 2 are applied to the switch circuit 135. Each switch circuit 135 is controlled by a pulse “H9” obtained by dividing each horizontal period from the timing pulse generation circuit 134 into nine, and Ri, Gi, Bi, Ri + 1, Gi + 1, Gi + 1,
Each of the video signals Bi + 1, Ri + 2, Gi + 2, and Bi + 2 is time-divided for each 1/9 horizontal synchronization period, and is sequentially output to a pulse width modulation (PWM) circuit 137.

In the pulse width modulation (PWM) circuit 137,
Ri, Gi, Bi, Ri + 1, Gi + 1, Bi + 1, R
A pulse width modulated (PWM) signal electrode control signal V12 is output according to the magnitude of each of the video signals i + 2, Gi + 2, and Bi + 2. Further, this signal electrode control signal is individually applied to the conductive plate 12 of the signal electrode 4 of the display element. As described above, the horizontal deflection and the switching of the switch circuit 135 are completely synchronized, and as a result, each pixel in the scanning line is illuminated and displayed according to the video signal. This control is sequentially performed from the upper line for 220 lines of 5 × 44 in this example, and a television image is displayed.

[0032]

However, according to the above configuration, the group of sample-and- hold circuits includes a sample- hold circuit.
Memory circuit 132 and memory 132
The total capacity of the memory is required to be twice the capacity of all the pixels in the effective horizontal scanning line period. This capacity is, for example, when each RGB video signal is 8 bi.
t, and if the number of RGB samples in the effective screen period is 666, then 8 × 666 × 3 ×
2 => 32 kbit. Furthermore, since the sample-and-hold circuit is usually composed of a data flip-flop (hereinafter, referred to as DFF),
If it is configured by a ray or the like, the configuration of a 1-bit DFF requires about 160 kgate as 5 gates.

In view of the above problems, the present invention utilizes a readable / writable memory (RAM, hereinafter simply referred to as a memory),
By rearranging the order of video signals and sending pixel data to the pulse width modulation (PWM) circuit at appropriate timing,
It is an object of the present invention to provide an inexpensive image display device that does not require the large-capacity large-capacity sample-hold circuit.

[0034]

In order to achieve the above object, an image display apparatus according to the present invention comprises a video signal rearranging apparatus comprising a memory having a total capacity corresponding to about a horizontal effective screen period and a memory control circuit; A sample / hold circuit for holding video signal data from the video signal rearranging device and having a capacity of 1/9 horizontal effective screen period.

[0035]

In the memory, the address increment / decrement step is written with one time (N = 1) of the increment / decrement step one horizontal period ago.
In this case, each memory address is Ai (i is an integer of 0 or more),
The data to be written is Di (i is an integer of 0 or more)
And data D0 is address A0 and data D1 is address
A1, data D2 is address A2,... Data Di is
It is stored at the address Ai. Next, increase / decrease one horizontal period before
Nine times of step "1", that is, N = 9, the memory address
Data Di, data Di becomes data D0, data D
.. Are read in the order of 9,. At this time, each day
Immediately after reading the data, write data for the next scan line.
Mode modify write operation (to the same address memory
In contrast, the first half reads data and the second half writes.
By performing the above operation , the video data before one horizontal scan is read out in a necessary order by each pulse width modulation (PWM) circuit, that is, every N data, so that the sampling video signals can be rearranged.

When N = 9, the video signal rearranging apparatus having the above-described configuration starts with the first R pixel required for the pulse width modulation (PWM) circuit, which is usually the first of three trio pixels. Are sequentially output for a 1/9 horizontal effective screen period. This video signal (normally 3
The data of the first trio of the trio (R pixel) is sequentially held by the sample and hold circuit, and when the hold for the 1/9 horizontal effective screen period is completed, all the held data is transferred to the pulse width modulation (PWM) circuit, and the pulse is output. In the width modulation (PWM) circuit, a pulse width modulation (PW) corresponding to the R pixel of the leading trio is applied to each signal electrode based on this data.
WM).

In the pulse width modulation (PWM) period, the video signal of the next 1/9 horizontal effective screen period, usually, the G pixel of the first trio, is sequentially output from the video signal rearranging device.
Similarly, the data is held by the sample hold circuit. By repeating this operation nine times in the horizontal scanning period, pulse width modulation (PWM) corresponding to a video signal for three trios is performed, so that the sample-and-hold circuit has an image capacity of 1/9 horizontal effective scanning line period. Can be displayed.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a drive circuit of an image display device according to one embodiment of the present invention. In FIG. 1, the same portions as those of the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, reference numeral 500 denotes a data dividing circuit 9.
00 and a memory R / W control circuit 901 which rearranges the sampled video signals in the order required by each pulse width modulation (PWM) circuit using a memory by using a memory. . FIG. 2 is a timing chart showing input / output signals of the data division circuit 900.

As shown in FIG. 2, the data dividing circuit 900
In this example, the R, G, and B input video signals are output in three groups in accordance with the processing in the memory R / W control circuit 901 at the subsequent stage. The reason why the R, G, and B input signals are divided into three groups will be described later.
This is to match the processing in the W control circuit 901. In the memory R / W control circuit 901, three processing circuits having the same configuration are used in parallel with a, b, and c for each group as shown in FIG.

The operation of the memory R / W control circuit 901 will be described below with reference to the drawings. FIG.
FIG. 3 is a block diagram illustrating a configuration example of a / W control circuit 901a. The memory R / W control circuits 901b and 901c have the same configuration.

In FIG. 3, reference numeral 600 denotes a data line switch for switching data input / output signals to / from the memory.

Reference numeral 601 denotes a readable / writable memory (RAM)
And the data division circuit 900 converts the R, G, B input video signals
Since the output is divided into three groups, one of them has a capacity of about 1/3 of the number of sampling dots of one horizontal effective screen. Reference numerals 602a, 602b, and 602c denote OR circuits, and 603a, 603b, and 603c denote 4-bit 9-digit counters, which are connected in three stages as shown. A shift register 604 shifts the outputs of Q1, Q2, and Q3 every H pulse. A data flip-flop 605 latches and outputs data at the falling edge of the reference clock SCK. 701 and 702 are data input terminals and output terminals, respectively.

Hereinafter, the operation of the video signal rearranging circuit configured as described above will be described with reference to FIG. FIG. 4 is an operation waveform diagram showing operation waveforms of main parts in FIG.

The actual number of trios of pixels in one horizontal period is 65.
Although it is used in about 0 to 750 trios, here, for simplicity of description, the number of trio data in one horizontal period is set to 729, and the entire horizontal period is described as a horizontal effective screen period. In FIG. 3, V and H indicate a vertical synchronization signal (hereinafter simply referred to as V synchronization) and a horizontal synchronization signal (hereinafter simply referred to as H synchronization), respectively. The shift register 604 presets the outputs Q1, Q2, and Q3 to Low, Low, and High by V synchronization, and repeats the shift operation every H synchronization as shown in FIG.

Reference numerals 603a, 603b, and 603c denote 4-bit ninth-counter counters each having a value of 0 to 8 for each SCK.
When the count reaches 8, a ripple carry output (hereinafter, referred to as RCO) is output to a ripple carry input (hereinafter, referred to as RCI) of an upper counter. As shown in the figure, the memory 601 has a reference clock SCK connected to an R / W terminal and a data selection switch 600 controlled by the reference clock SCK to a data terminal.
As a result, the input / output of data to / from the memory is switched, so that a read-modify-write operation is performed for each address. The operation will be described below.

First, the outputs Q 1,
The operation when Q2 and Q3 are respectively Low, Low and High will be described. At this time, the RCI of the counter 603a
Is High, the output Qa is clock SCK as shown in the figure.
The count from 0 to 8 is repeated every time. Since the RCI of the counter 603b is connected to the RCO of the counter 603a via the OR circuit 602a, the RCI counts up each time the RCO of the counter 603a is output. Further, the counter 603c similarly counts up at the higher rank.

As described above, the output of the shift register 604
Q1, Q2 and Q3 are Low, Low and High respectively.
, Counters 603c, 603b, 6
The signal consisting of each output of 03a is used as an address.
The data is input to the memory 601. 4 bit data from each counter
When data is output, 12 bits are stored in the memory 601.
As an address, and then the counter 603a
Operate as a counter on the LSB side. On the other hand, at this time, d0 to d728 are input to the data input terminal 701 as shown in FIG. 4, and data is written into the memory 601 in this order.

When the next horizontal scanning line is input and the horizontal synchronizing signal H is input, the output Q 1 of the shift register 604 is output.
, Q2, Q3 outputs are shifted to High, Low, Low. At this time, the RCI of the counter 603b is High.
Therefore, the output Qb repeatedly counts from 0 to 8 every clock SCK as shown in the figure. Also, the counter 603c
RCI of the counter 603c is added to the OR circuit 6
02b, the counter 603b
Counts up every time the RCO is output. Further, the counter 603a similarly counts up at the higher rank.

As described above, the output Q of the shift register 604
When the outputs of 1, Q2 and Q3 are High, Low and Low, the counter 603b operates as a counter on the LSB side.

On the other hand, at this time, the memory 601 performs a read-modify-write operation for each address when the reference clock SCK is High, and reads out the memory contents when the SCK is Low. I have . This
The step of increasing / decreasing the read address is performed one horizontal period before.
Since it changes at 9 times the increase / decrease step (N = 9), as shown in FIG. 4, the video signal data written in the previous horizontal synchronizing period is ninth from the memory 601 , that is,
The address A9 is followed by the address A9, and the address A is followed by the address A
18 are respectively written in data d0,
Data d9, data d18,... Are read.

When the next horizontal scanning line is input and the horizontal synchronizing signal H is input, the output Q1 of the shift register 604 is output.
, Q2, and Q3 output are shifted to Low, High, and Low, and the counter 603c operates as a counter on the LSB side. Therefore, from the memory 601, every nine video signal data written in the previous horizontal synchronization period are also output. To d
0 ', d9', d18 ',...

Further, when the horizontal synchronizing signal H is input,
Shift register 604 outputs Q1, Q2, Q3 outputs Lo
The signal is shifted to w, Low, and High, and returns to the initial operation in which the counter 603a operates as the counter on the LSB side. Similarly, the video signal data written in the previous horizontal synchronization period is read out every nine.

As described above, for the memory, the address increase / decrease step is changed by 9 times the increase / decrease step one horizontal period earlier, and the video data one horizontal scan earlier is read for each address by the read modify write. By reading in the order required by the pulse width modulation (PWM) circuit, that is, by reading every nine, it is possible to rearrange the sampled video signals.

Hereinafter, the operation of the image display apparatus of the present invention will be further described with reference to FIG. In FIG. 1, reference numeral 234 denotes a timing pulse generation circuit which generates various timing pulses in the same manner as in the conventional example. In the conventional example, the sampling start pulse t1 corresponding to the head of the effective horizontal screen period is used as the sampling start pulse. However, here, a pulse signal “H9” having a rate nine times the horizontal synchronization period is used.

Reference numeral 501 denotes a sample and hold circuit. In the conventional sample and hold circuit 131, Ri, Gi, B
i, Ri + 1, Gi + 1, Bi + 1, Ri + 2, Gi +
2, Bi + 2 and each pulse width modulation (PWM) circuit 137 required a capacity of 9 pixels.
Each circuit is composed of a capacitor for one pixel. Reference numeral 502 denotes a shift register which sets the sample / hold start timing to "H".
Each sample and hold 501 based on a 9 "signal pulse
To be distributed at an appropriate timing.

Hereinafter, the operation of the video signal rearranging circuit configured as described above will be described with reference to FIG. 1 again.

The video signal rearranging circuit 500 reads
The increment / decrement step of the address to be output is
9 times (N = 9) of the horizontal synchronization period.
Every nine video signal data written in between are output,
That is , the pulse width modulation (PWM) circuit 137 is required first, and usually corresponds to the first R pixel of three trio pixels.
The video signals R1, R10, R19, R28, R37,... For the 1/9 horizontal effective screen period are sequentially output.

The video signal (normally, the R pixel of the first trio of each trio) data is sequentially held by the sample and hold circuit 501 in accordance with the timing from the shift register 502, and the hold for the 1/9 horizontal effective screen period is completed. Then, all the held data is transferred all at once to the pulse width modulation (PWM) circuit 137 by the “H9” pulse. In the pulse width modulation (PWM) circuit 137, each signal electrode uses the R of the first trio based on this data. Pulse width modulation (PWM) corresponding to the pixel is performed. During this pulse width modulation (PWM) period, the video signal of the next 1/9 horizontal effective screen period, usually the G pixel of the first trio, G1, G4, G7
Are sequentially output from the video signal rearranging device, and are similarly held in the sample hold circuit 501. By repeating this operation nine times during the horizontal scanning period, pulse width modulation (PWM) corresponding to a video signal for three trios is performed. Therefore, the sample-and-hold circuit has an image capacity of 1/9 horizontal effective screen period. The display can be performed.

Further, the total capacity of the memory (RAM) used for rearranging the video signals in the present invention is equivalent to one horizontal effective screen period, which is 1/2 of the total capacity of the sample and hold circuit in the conventional example. Become. Further, the area occupied by the RAM on the ASIC is generally about 0.5 gate / bit per bit (5 gates / bit using a DFF as in the conventional example).
Since this corresponds to t), the circuit scale can be significantly reduced even if the control circuit of the RAM is considered.

[0061]

As described above, according to the present invention, a video signal rearranging apparatus comprising a memory having a total capacity corresponding to about the horizontal effective screen period and a memory control circuit, and an image from the video signal rearranging apparatus are provided. Hold signal data, 1
By providing a sample-and-hold circuit having a capacity corresponding to the / 9 horizontal effective screen period, an inexpensive image display device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a driving circuit of an image display device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a main part of the image display device according to one embodiment of the present invention.

FIG. 3 is a block diagram of a main part of the image display device according to one embodiment of the present invention.

FIG. 4 is an operation waveform diagram of a main part of the image display device according to one embodiment of the present invention.

FIG. 5 is an exploded perspective view of a main part of a display element of a conventional image display device.

FIG. 6 is a block diagram of a driving circuit of a conventional image display device.

FIG. 7 is an operation waveform diagram of a main part of a drive circuit of a conventional image display device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 back electrode 2 line cathode 3 lead electrode 4 signal electrode 5, 6 focusing electrode 7 horizontal deflection electrode 8 vertical deflection electrode 9 front glass container 10 rear glass plate 24 electrode block 137 pulse width modulation (PWM) circuit 500 video signal rearranging device 501 Sample hold circuit

Claims (1)

(57) [Claims] An electric conductor is provided on the inner surface of the rear glass plate in a space between a front glass container having a phosphor applied therein and a rear glass plate closing a rear opening of the front glass container. A pulse width modulation (PWM) using a back electrode formed by coating or a conductive plate, a plurality of line cathodes, an extraction electrode formed of a single or a plurality of conductive plates, and a video signal corresponding to each pixel in a scanning line. ), A plurality of signal electrodes, a single or a plurality of focusing electrodes, an electrode block in which horizontal deflection electrodes and vertical deflection electrodes are superposed one on the other, and a control circuit for driving each of the above electrodes by a television signal. And an address increase / decrease step.
Is changed by N times the increase / decrease step one horizontal period before
The video data is read out every N
Read-modify-write operation for each
Output in a different order from the data order of the input video signal
Comprising a rearranged video signal apparatus, and a sample hold circuit of the pixel number corresponding to the number of the signal electrodes which sequentially holds the output of the video signal rearrangement unit, the sample-and-hold circuit, the number of the signal electrodes An image display device, comprising: performing pixel-sample sampling and holding, and simultaneously transferring pixel data to a pulse width modulation (PWM) circuit in synchronization with horizontal deflection.