JPS6228633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention vertically divides a screen into a plurality of sections, generates an electron beam in each section, and deflects each electron beam in the vertical direction for each section. It relates to a device that displays multiple lines on the screen to display the television image as a whole, and performs interlaced display operation by performing accurate vertical deflection so that each line can be displayed correctly in a predetermined position on the screen. The purpose is to provide a device that can do this.

Conventionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size, making it difficult to create thin television receivers. It was impossible. In addition, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of brightness, contrast, and color reproducibility in color display, and have not yet been put into practical use.

Therefore, the aim was to create a device that could display color television images on a flat display device using electron beams, and the screen was divided vertically into multiple sections. Each section generates an electron beam, deflects each electron beam in the vertical direction to display multiple lines, and further divides it into multiple sections horizontally to display R, G, B, etc. phosphors are made to emit light in sequence, and the amount of electron beam irradiation to the R, G, B, etc. phosphors is controlled by a color video signal, and the television image as a whole is displayed. Something to display was devised.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
Back electrode 1, line cathode 2 as an electron beam source, vertical focusing electrodes 3, 3', vertical deflection electrode 4, electron beam flow control electrode 5, horizontal focusing electrode 6, horizontal deflection electrode 7, electron beam accelerating electrode 8 and screen. Board 9
These are housed in the evacuated interior of a flat glass bulb (not shown). Line cathode 2 as electron beam source
is stretched in the horizontal direction so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of such linear cathodes 2 are arranged vertically at appropriate intervals (here, 2 A to 2 D). (Only books shown) provided. In this embodiment, it is assumed that 15 pieces are provided. Let's say 2i~2yo. These wire cathodes 2 are constructed by applying an oxide cathode material to the surface of a tungsten wire having a diameter of 10 to 20 μΦ, for example. Then, as will be described later, the electron beams are controlled to be emitted sequentially from the upper line cathode 2a for a fixed period of time. The back electrode 1 creates a potential gradient with a vertical focusing electrode 3, which will be described later, and prevents the generation of electron beams from other line cathodes 2 other than the line cathode 2 which is controlled to emit electron beams for a certain period of time. It acts to suppress the generated electron beam and push it only in the forward direction. The back electrode 1 may be formed by a coating of a conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2I to 2Y, and extracts the electron beam emitted from the line cathode 2 through the slit 10, and focus in a direction. The slit 10 may be provided with crosspieces at appropriate intervals in the middle, or may be substantially configured as a slit by a row of many through holes arranged horizontally at small intervals (nearly touching intervals). may have been done. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this configuration example, the electron beam from one line cathode 2 is vertically deflected to positions corresponding to 16 lines by a pair of conductors 13, 13'. And, by 16 vertical deflection electrodes 4, 15
Fifteen conductor pairs corresponding to each of the book line cathodes 2 are constructed, and the electron beam is ultimately deflected to draw 240 horizontal lines on the screen 9.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 15 are arranged in parallel in the horizontal direction at predetermined intervals. In this configuration example, 320 control electrode conductive plates 15a to 15n are provided (only 10 are shown in the figure). Each of the control electrodes 5 separates and extracts the electron beam into one picture element in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, if 320 control electrodes 5 are provided, 320 picture elements can be displayed per horizontal line. Also,
In order to display images in color, each picture element is R.
Display is performed using phosphors of three colors, G and B, and R, G, and B video signals are sequentially applied to each control electrode 5. In addition, 320 sets of video signals for one line are simultaneously applied to the 320 control electrodes 5.
Video for each line is displayed at once.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (320 slits 16) opposite to the slits 14 of the control electrode 5. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is composed of a plurality of conductive plates 18 arranged vertically in the middle of each of the slits 16, and a horizontal deflection voltage is applied between each conductive plate 18 for each picture element. The electron beams are each deflected in the horizontal direction, and the R, G, and B phosphors are sequentially irradiated on the screen 9 to cause them to emit light. In this embodiment, the deflection range is the width of one picture element for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by applying a phosphor 20 that emits light when irradiated with an electron beam to the back surface of a glass plate 21, and adding a metal back layer (not shown). The phosphor 20 is the control electrode 5
For one slit 14, that is, for each horizontally divided electron beam,
A pair of phosphors in each of the three colors R, G, and B are provided, and are applied in stripes in the vertical direction. In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view in Fig. 2, one section partitioned by these two has R, G, and B phosphors 20 for one pixel in the horizontal direction, and 16 lines in the vertical direction. It has a width of
For example, the size of one section is 1 in the horizontal direction.
mm, and the vertical direction is 16 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this embodiment, only one pair of R, G, and B phosphors 20 are provided for one picture element for one control electrode 5, that is, one electron beam, but two
Of course, two or more pairs for more than two picture elements may be provided, and in that case, R, G, and B video signals for two or more picture elements are sequentially applied to the control electrode 5.
Horizontal deflection is performed in synchronization with this.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to cause the phosphor to emit light and generate a raster will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
V ₃ , V ₃ ′ V 6 to the horizontal focusing electrode 6, V ₆ to the accelerating electrode 8
A DC voltage of V ₈ and V ₉ is applied to the screen 9.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H. The vertical drive pulse generation circuit 25 is constituted by a counter etc. that is reset by the vertical retrace pulse and counts the horizontal pulse, and is configured to operate during an effective vertical scanning period (here, 240H) excluding the vertical retrace period of the vertical period. 15 drive pulses of length of 16H period [a], [b]...
[Y] occurs. This driving pulse [a]...
[Y] is applied to the line cathode drive circuit 26, where it is inverted, and the line cathode drive pulse [A'] is made to have a low potential only during each pulse period and to a high potential of about 20 volts during the other periods. , [B']...[Yo'] and added to each line cathode 2a, 2ro, . . . 2yo. A current is passed through each line cathode 2a, ... 2yo during the high potential of the drive pulses [a'] to [yo'], and the low potential period of the drive pulses [a'] to [yo']. The heated state is maintained so that electrons can also be emitted. As a result, low potential drive pulses [A'] to
Electrons are emitted only during the 16H period when [Yo'] is added. During the period when a high potential is applied, the potential at the line cathode 2 is lower than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the applied high potential becomes positive, the line cathode 2
No electrons are emitted from 2yo. Thus, in the line cathode 2, during the effective vertical scanning period, from the upper line cathode 2A to the lower line cathode 2Y,
Electrons are emitted every 16H period. The emitted electrons are pushed forward by the back electrode 1, pass through the opposing slits 10 of the vertical focusing electrode 3, and are focused in the vertical direction to form a flat electron beam.

Next, as will be described later, the vertical deflection drive circuit 27 includes a counter that is reset by the vertical synchronizing signal and counts the horizontal synchronizing signal, a digital memory that is addressed by the count output, and a counter that reads data from the digital memory. It is composed of a conversion circuit that D/A converts the digital signal, etc., and each vertical drive pulse [A] ~
During the 16H period of [Y], a pair of step-like waveform vertical deflection signals V and V' which change in 16 steps by 1H are generated. The center voltage of both vertical deflection signals V and V′ is
For _V4 , V increases sequentially and V' decreases sequentially, so that they change in opposite directions. These vertical deflection signals V and V' are applied to the electrodes 13 and 13' of the vertical deflection electrode 4, respectively, and as a result, the electron beams generated from the respective line cathodes 2A to 2Y are deflected in 16 steps in the vertical direction. As mentioned above, on the screen 9, one electron beam is deflected so as to sequentially draw a raster line of 16 lines one line at a time from the top.

As a result of the above, electron beams are emitted for 16H periods in order from the one above the 16 line cathodes 2I to 2Y.
Each electron beam is deflected one line at a time from the top to the bottom within the 15 sections in the vertical direction, so that the electron beams are deflected one line at a time from the 1st line at the top to the 240th line at the bottom on the screen 9. The electron beam is vertically deflected line by line, creating a raster of 240 lines in total.

The electron beam thus vertically deflected is horizontally deflected by 320 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The R, G, and B phosphors 2 on the screen 9 are deflected horizontally in three stages.
0 sequentially.

That is, the horizontal drive pulse generation circuit 28 is composed of three continuously connected monostable multivibrators, etc., and is triggered by a horizontal synchronization signal to generate three horizontal drives with equal pulse widths within one horizontal period. Generate pulses r, g, b. Here, as an example, each pulse width is approximately 17μ
sec, three pulses r, g, and b are generated during an effective horizontal scanning period of 50 μsec. These horizontal drive pulses r, g, and b are applied to the horizontal deflection drive circuit 29. The horizontal deflection drive circuit 29 generates a pair of horizontal deflection signals h and h' that change in three stages by being switched by the horizontal drive pulses r, g, and b. horizontal deflection signal h,
Both h' have a center voltage of V ₇ , and change in opposite directions such that h increases sequentially and h' decreases sequentially. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively. As a result, each horizontally divided electron beam is transmitted to the screen 9 during each horizontal period.
It is horizontally deflected so that the phosphor B is sequentially irradiated for 17 μsec each. However, in the display element of FIG. 1, one conductor 18 is used in the horizontal deflection electrode 7.
Or, since 18' is used to deflect the electron beams of two adjacent sections and is designed to produce a deflection effect on the adjacent electron beams in mutually opposite directions, the electron beams of 320 sections are The beam is deflected in the order of R→G→B in the odd numbered sections, and vice versa in the order of B→G→R in the even numbered sections.
Every segment is deflected in the opposite direction.

Thus, in each line raster, the electron beam is divided into R, G,
Each phosphor 20 of B is sequentially irradiated.

Therefore, a color television image can be displayed on the screen 9 by modulating the electron beam with R, G, and B video signals for each horizontal section of each line.

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 23 is applied to the color demodulation circuit 30,
Here, the color difference signals of R-Y and B-Y are demodulated,
The G-Y color difference signals are matrix-synthesized, and further, they are combined with the luminance signal Y to generate R, G,
B primary color signals (hereinafter referred to as R, G, and B video signals) are output. These R, G, and B video signals are processed by 320 sample and hold circuit sets 31a to 3.
Added to 1n. Each sample hold circuit group 3
1a to 31n each have three sample and hold circuits for R, G, and B. The sample and hold outputs of these sample and hold circuit sets 21a to 31n are held by memory sets 32a to 32n, respectively.
32n.

On the other hand, the sampling reference clock oscillator 33
is composed of a PLL (phase locked loop) circuit, etc., and generates a reference clock of about 6.4 MHz in this embodiment. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H. This reference clock is applied to the sampling pulse generation circuit 34, where it is delayed by one clock period by a shift register, etc., so that during the effective horizontal scanning period (approximately 50 μsec) of the horizontal period (63.5 μsec), 320 sampling pulses a to n are generated in sequence, followed by one rotation pulse. These sampling pulses a to n correspond to each picture element when one line of the video to be displayed is divided into 320 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled by.

These 320 sampling pulses a to n correspond to the above 320 sample and hold circuit sets 31.
a to 31n, thereby providing one line to each sample and hold circuit set 31a to 31n.
When divided into 320 picture elements, the R, G, and B video signals of each picture element are individually sampled and held. The sampled and held 320 sets of R, G, and B video signals are stored in 320 sets of memories 32a to 32a after completion of sample and hold for one line.
32n all at once by a transfer pulse t,
Here, it is held for the next one horizontal scanning period.

One line of R, G, and B video signals held in the memories 32a to 32n are applied to 320 switching circuits 35a to 35n, respectively. The switching circuits 35a to 35n each have R, G,
B individual input terminals and a common output terminal that sequentially switches and outputs them, and the output of each switching circuit 35a to 35n is sent to the control electrode 5 of the display element as a control signal for modulating the electron beam.
are individually applied to each of the 320 conductive plates 15a to 15n. Each switching circuit 35a to 35
n are simultaneously switched and controlled by a switching pulse applied from a switching pulse generating circuit 36. The switching pulse generation circuit 36 receives pulses r,
g and b, and the effective horizontal scanning period of each horizontal period is approximately 50μsec, divided into three to approximately 17μsec.
Switch the switching circuits 35a to 35n one by one,
The R, G, and B video signals are time-divisionally output alternately and sequentially, and switching signals r, g, and b are generated to be supplied to the control electrodes 15a to 15n. However, among the switching circuits 35a to 35n, the odd numbered switching circuits 35a, 35c...
→B, and the even-numbered switching circuits 35b, 35d...35n are switched in the order of B→G→
The switching is made in the order of R.

What should be noted here is that the switching circuit 3
The switching of the supply of R, G, and B video signals in 5a to 35n and the horizontal deflection of the horizontal deflection of the electron beam irradiation to the R, G, and B phosphors by the horizontal deflection drive circuit 29 are performed both in timing and order. This means that they are synchronously controlled so that they match perfectly. As a result, when the electron beam is irradiating the R phosphor, the irradiation amount of the electron beam is controlled by the R video signal, and G and B are similarly controlled, so that the R and G of each picture element are controlled in the same manner. , B phosphors are respectively controlled by the R, G, and B video signals of the picture elements, and each picture element is displayed by emitting light in accordance with the input video signal. Such control is performed simultaneously on 320 pixels for one line to display one line of video, and then sequentially performed for 240 minutes from the upper line to display one video on screen 9. That will happen.

The above operations are repeated for each field of the input television signal, and as a result,
The screen 9 is similar to a normal television receiver.
The television footage of the video is shown above.

As described above, television images are displayed on this display device.

Note that the terms "horizontal direction" and "vertical direction" in the above explanation mean that the direction in which line units are displayed when displaying an image is the horizontal direction, and the direction in which the lines are stacked and turned is the vertical direction. It is used in this sense, and is not directly related to the vertical and horizontal directions on the actual screen.

As described above, television images are projected on this display device, but due to assembly errors of each electrode during the manufacturing of display elements, the vertical deflection is not uniform, and as a result, the screen The spacing between the lines on the top may become uneven, or the ends of each line may shift vertically.
The scanning lines of each line may overlap or there may be gaps.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a device that can correctly display each raster line on a screen at a predetermined position at a predetermined constant interval when using the above-mentioned image display element. The purpose is to

First, a conventional vertical deflection drive circuit will be explained. FIG. 4 shows the basic configuration of the vertical deflection drive circuit 27. The ring counter 37 receives vertical drive pulses [A]~ from the vertical drive pulse generation circuit 25.
It is reset at each leading edge of [Y], and then the horizontal synchronizing signal H is counted to sequentially generate switching pulses a to π from the 16 output terminals every horizontal period. On the other hand, the variable resistor 38 is provided with 16 output terminals, from which output voltages in 16 stages for vertical deflection are taken out via analog switches 39a to 39π. Each of the analog switches 39a to 39π is sequentially turned on for one horizontal period by switching pulses a to π, respectively, and the step waveform is divided into 16 stages between the lowest terminal and the highest terminal, and the level increases successively. The output is obtained. The output voltage is taken out via a transistor 40 connected as an emitter follower, its amplitude is adjusted by a variable resistor 41, and amplified by a class B amplifier circuit 45 made up of transistors 42, 43, and 44, and then output terminal. 46
A vertical deflection signal V is created from this. On the other hand, the vertical deflection signal V' is also created by a completely similar circuit, but in the above case, the analog switches 39a' to 39a'
The only difference is that 9π' is switched in the reverse order by the switching pulses a to π, thereby creating a step-like output V' whose level is successively lower, which is output from the output terminal 46'. .

The vertical deflection signals V and V' thus created are:
It is applied to the conductive plates 13 and 13' of the vertical deflection electrode 4, whereby the electron beam is deflected in 16 steps in each section in the vertical direction, and a raster of 16 lines is drawn with one electron beam. .

This device provides a circuit suitable for interlaced display operation when using the above-mentioned image display element,
The present invention is also characterized in that the positions of the scanning lines can be adjusted arbitrarily.

FIG. 5 shows a block diagram of an embodiment of the present invention. Here, it is assumed that the memories 52 and 53 are memories in which the number of data bits is 8 bits and the number of address bits is 9 bits.

In the memories 52 and 53, as shown in FIG. 6 M1 and M2, first field deflection data V _o ,
V _o ′ is stored in memory, and the next field is V
Deflection data is stored as _(o+1) and V′ _(o+1) . A specific example of the data is shown in FIG. 6M.

The 8 bits of addresses _A0 to _A7 correspond to the scanning line of each field, and _A8 corresponds to whether the field is an odd number or an even number, with an odd number field being "0" and an even number field being "1". The counter 50 is an up counter and is reset by a vertical pulse V.
Count horizontal pulse H for 240H. The count output is supplied to address terminals of memories 52 and 53.

The field detection circuit 51 detects the phase shift between the horizontal pulse H and the vertical pulse V, and determines whether the field is an odd field or an even field. In odd fields, the vertical pulse V and the horizontal pulse H are in the same phase, and in this case "0" is output. On the other hand, in an even field, there is a phase shift of 1/2H between the vertical pulse V and the horizontal pulse H, and in this case, "1" is output.

Based on this detection output, addresses "0" to "239" in the memories 52 and 53 are accessed in the odd field, and V _o and V _o ' are read out and output. On the other hand, in an even field, addresses “255” to
Access "495" and read and output V _(o+1) and V' _(o+1) . Its output is D/A converter 5
4 and 55, an analog deflection waveform as shown in FIG. 8 is obtained. In the first field, lines 1 to 240 are displayed, and in the next field, lines 241 to 480, which are shifted by 1/2 line, are displayed, and an interlaced display operation is performed.

The data in the memories 52 and 53 can be rewritten using a microcomputer, and by inputting data corresponding to each line, the position of each line can be adjusted.

The counter 50 is an up counter that counts horizontal pulses H for 240 hours as shown in FIG.

In this way, it is possible to provide a deflection circuit that can perform interlacing with a simple configuration of the memories 52, 53, the D/A converters 54, 55, the counter 50, and the field detection circuit 51, and the deflection positions of each can be arbitrarily adjusted. can do.

By interlacing in this way, vertical resolution is improved. Furthermore, the above-mentioned drawback of the image element, which is the variation in deflection position, can be eliminated by adjusting the position for each line.

[Brief explanation of the drawing]

FIG. 1 is an exploded perspective view showing the basic configuration of an example image display element used in the image display device of the present invention;
Figure 2 is an enlarged view of the screen, Figure 3 is a block diagram showing the basic configuration of the drive circuit of the device, and Figure 4 is a block diagram showing the basic configuration of the drive circuit of the device.
The figure is a circuit diagram showing the basic configuration of the vertical deflection drive circuit in the same circuit, FIG. 5 is a block diagram of the vertical deflection drive circuit of an image display device according to an embodiment of the present invention, and FIG. The schematic diagrams illustrating the memory mode, FIGS. 7 and 8, are waveforms illustrating the operation of the vertical deflection drive circuit. 2... Line cathode, 3... Vertical focusing electrode, 4... Vertical deflection electrode, 9... Screen, 13, 13'...
...Conductor, 25...Vertical drive pulse generation circuit, 2
6... Line cathode drive circuit, 27... Vertical deflection drive circuit, 50... Counter, 51... Field detection circuit, 52, 53... Memory, 54, 55...
D/A converter.

Claims (1)

[Claims] 1 The screen surface is vertically divided into multiple sections, and an electron beam is generated in each section,
A display element is provided in each section to display a plurality of lines on the screen by vertically deflecting each electron beam, and a stepped waveform is created to vertically deflect the electron beam within each section. The means includes a counter for counting horizontal synchronization signals, and means for supplying the output of the counter to an address in the digital memory;
It has means for outputting a digital signal corresponding to the address as an output of the digital memory, and a D-A converter for converting the output digital signal into an analog signal, and the digital memory is configured to output deflection data of an odd field. It is characterized by comprising a first memory for storing deflection data for even fields and a second memory for storing deflection data for even fields, and the first memory is accessed for odd fields, and the second memory is accessed for even fields. image display device.