JPH08162856A - Amplifier circuit - Google Patents

Abstract

PURPOSE: To obtain the amplifier circuit in which a voltage range of an input signal is extended. CONSTITUTION: Emitters of NPN transistors(TRs) T3, T8 are connected to a resistor R1. PNP TRs T4, T9 are connected to the TRs T3, T8. PNP TRs T5, T10 are connected through a resistor T2. Input signals Vin1, Vin2 are given to emitters of the TRs T3, T8. Output currents Io1, Io2 are outputted from collectors of TRs T5, T10. The output currents Io1, Io2 are given to emitters of PNP TRs T13, T18 and collectors of the TRs T13, T18 are connected to collectors of NPN TRs T14, T15. The collector of the TR T18 is connected to an input terminal of an operational amplifier OP1, from which an output signal Vout is outputted. A voltage Vref2 obtained by dividing voltages of the signal Vout and a reference voltage Vref1 with resistors R3, R4, R5 is fed back to the TR T13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit.

[0002]

2. Description of the Related Art As a conventional amplifier circuit, Japanese Patent Laid-Open No. 6-232
There is one disclosed in Japanese Patent No. 645. As shown in FIG. 5, this amplifier circuit includes an input circuit section 21 and a feedback circuit section 22.

The input circuit section 21 is a PNP transistor T3.
1, T34, NPN transistors T32, T33, T3
5, T36, resistors R21 and R22, and constant current sources S21-
S26 is provided. The input signal Vin1 is input to the base of the PNP transistor T31, the emitter of the transistor T31 is connected to the emitter of the NPN transistor T32, and the collector of the transistor T31 is the ground GN.
D.

A collector current is supplied to the collector of the NPN transistor T32 from a power source Vcc through a constant current source S21. The base of the NPN transistor T33 is connected to the constant current source S21 and the base current is supplied from the identification current source S21. The collector current of the transistor T33 is supplied from the power source Vcc through the constant current source S22. To be done.

The emitter of the NPN transistor T33 is N
It is connected to the base of the PN transistor T32 and is also connected to the ground GND via the constant current source S23.

The input signal Vin2 is input to the base of the PNP transistor T34, the emitter of the transistor T34 is connected to the emitter of the NPN transistor T35, and the collector of the transistor T34 is grounded.
It is connected to the.

A collector current is supplied to the collector of the NPN transistor T35 from the power supply VCC through the constant current source S24. The base of the NPN transistor T36 is connected to the constant current source S24, and the base current is supplied from the identification current source S24. The collector current of the transistor T36 is supplied from the power source Vcc through the constant current source S25. To be done.

The emitter of the NPN transistor T36 is N
It is connected to the base of the PN transistor T35 and is also connected to the ground GND via the constant current source S26.

The collectors of both NPN transistors T33 and T36 are connected to each other via a resistor R21, and the emitters of both transistors T33 and T36 are connected to each other via a resistor R22.

The input circuit section 21 receives the input signals Vin1 and V1 from the collectors of the NPN transistors T33 and T36.
Output currents Io3 and Io4 based on in2 are output to the feedback circuit unit 22.

The feedback circuit section 22 includes a PNP transistor T.
41, T42, T45, T46, NPN transistor T
43, T44, diodes D1, D2, resistors R23 to R
25, an operational amplifier OP0, and constant current sources S27 and S28. The output current Io3 of the input circuit section 21 is P
The output current Io4 is input to the emitter of the NP transistor T42, and the output current Io4 is input to the emitter of the PNP transistor T46.

The base of the PNP transistor T42 is connected to the anode of the diode D1. Diode D
A forward current is supplied from the power source Vcc to the anode of No. 1 through the constant current source S27, and the cathode of the diode D1 is connected to the emitter of the PNP transistor T41. The reference voltage V is applied to the base of the PNP transistor T41.
ref5 is input and the collector is connected to the ground GND.

The base of the PNP transistor T46 is connected to the anode of the diode D2. A forward current is supplied to the anode of the diode D2 from the power supply VCC through the constant current source S28, and the cathode of the diode D2 is connected to the emitter of the PNP transistor T45. The base of the PNP transistor T45 is a resistor R23.
Is connected to the base of the PNP transistor T41 via a resistor R24 and to the ground GND via a resistor R24, and the collector of the transistor T46 is connected to the ground GND.
D.

The collectors of the PNP transistors T42 and T46 are connected to the collectors of the NPN transistors T43 and T44, respectively. NPN transistor T4
The bases of T3 and T44 are connected to each other and to the collector of the transistor T44, and the NPN transistors T43 and T44 form a current mirror circuit. Both emitters of the NPN transistors T43 and T44 are connected to the ground GND.

The inverting input terminal of the operational amplifier OP0 is NPN.
It is connected to the collector of the transistor T43 and its non-inverting input terminal is connected to the ground GND. Operational amplifier O
The output terminal of P0 is connected to the base of a PNP transistor T45 via a resistor R25. Operational amplifier OP0
Outputs the output signal Vout0 from the output terminal. Therefore, P
The voltage Vref6 obtained by dividing the output signal Vout0 and the reference voltage Vref5 by the resistors R23 to R25 is input to the base of the NP transistor T45.

[0016]

However, in the amplifier circuit configured as shown in FIG. 5, the NP of the input circuit section 21 is
The emitter potential of the N-transistor T33 is the input signal Vin
It has a value obtained by adding the base-emitter voltage of two PNP transistors T31 and T32 to the voltage of 1. For the collector potential of the NPN transistor T33, the base-emitter voltage for two PNP transistors T41 and T42 and the voltage at which the diode D1 turns on are used as the reference voltage Vref5.
It will be the value added to. Similarly, the NPN transistor T36
Has a value obtained by adding the base-emitter voltage for two PNP transistors T34 and T35 to the voltage of the input signal Vin2. The collector potential of the NPN transistor T36 is the same as that of the PNP transistors T45 and T46.
This is a value obtained by adding the base-emitter voltage for one and the voltage at which the diode D2 is turned on to the voltage Vref6.

Then, NPN transistors T33 and T3
6 is turned on, each NPN transistor T33,
It is necessary that the emitter potential of T36 is lower than the collector potential. However, if the voltages of the input signals Vin1 and Vin2 are set to arbitrary values, the emitter potentials of the NPN transistors T33 and T36 may become higher than the collector potential depending on the values of the reference voltages Vref5 and Vref6.
As a result, the NPN transistors T33 and T36 may be turned off and the amplifier circuit may not operate. That is, the input signals Vin1 and Vin2 for operating the amplifier circuit
The voltage range of is limited by the values of the reference voltages Vref5 and Vref6.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an amplifier circuit which can operate even if the voltage range of an input signal is expanded.

[0019]

FIG. 1 is a diagram illustrating the principle of the present invention. The amplifier circuit includes an input circuit unit 1 and a feedback circuit unit 2. The input circuit unit 1 connects the emitters of the first and second bipolar transistors T3 and T8 to each other via the input resistor R1. The first and second transistors T4 and T9 are connected to the collectors of the first and second bipolar transistors T3 and T8, respectively, and the first current mirror circuit 13 is constituted by the first transistor T4 and the third transistor T5. And the second transistor T9 and the fourth transistor T10 form a second current mirror circuit 14. The third and fourth transistors T5 and T10 are connected to each other via the output resistor R2, and the first and second bipolar transistors T3 and T3 are connected.
The first and second input signals Vin1 and Vin are applied to the emitter of T8.
2 is input to each of the third and fourth transistors T
5, T10 outputs first and second output currents Io1 and Io2, respectively.

The feedback circuit unit 2 inputs the first and second output currents Io1 and Io2 to the emitters of the third and fourth bipolar transistors T13 and T18, respectively, and the third and fourth bipolar transistors T13 and T18. The collectors of are connected to the fifth and sixth transistors T14 and T15, respectively, which form the third current mirror circuit 15.
The reference voltage Vref1 is input to the base of the fourth bipolar transistor T18, and the collector of the fourth bipolar transistor T18 is connected to the input terminal of the operational amplifier OP1 to output the output signal Vout1 from the operational amplifier OP1 and output the same. The voltage Vref2 obtained by dividing the signal Vout1 and the reference voltage Vref1 by the resistors R3, R4 and R5 is input to the base of the third bipolar transistor T13 as a feedback signal.

According to a second aspect of the present invention, a plurality of feedback circuit sections are provided, and at least one feedback circuit section has second and first feedback circuits at the emitters of the third and fourth bipolar transistors, respectively.
Is connected to the input circuit part so that the output currents of the first and second output currents of the other feedback circuit parts are input to the emitters of the third and fourth bipolar transistors, respectively. Is connected to the input circuit section.

[0022]

According to the present invention, the collectors of the first and second bipolar transistors T3 and T8 are respectively connected to the first and second transistors T4 and T9 forming the first and second current mirror circuits 13 and 14, respectively. The third and fourth transistors T5 and T10 which are connected and constitute the first and second current mirror circuits 13 and 14 have first and second outputs to the emitters of the third and fourth bipolar transistors T13 and T18. Outputs currents Io1 and Io2. Therefore, the first
And the collector voltages of the second bipolar transistors T3 and T8 are the first and second current mirror circuits 13 and 14, respectively.
And is not limited by the reference voltage Vref1. Therefore, the first and second input signals Vin
Even if the voltage range of 1 and Vin2 is expanded, the first and second bipolar transistors T3 and T8 are turned on, and the input circuit unit 1
Works fine.

According to the second aspect of the present invention, it is possible to obtain output signals of opposite phases from the plurality of feedback circuit sections with respect to the first and second input signals input to one input circuit section. Further, since the input circuit unit is common to the plurality of feedback circuit units, it is possible to reduce the relative error of the plurality of output signals output from the plurality of feedback circuit units and improve the relative accuracy.

[0024]

【Example】

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIG. For convenience of explanation, the same components as those in FIG. 1 will be described with the same reference numerals.

The amplifier circuit 10 comprises an input circuit section 11 and a feedback circuit section 12. The input circuit unit 11 includes PNP transistors T1 and T6 and a multi-collector PNP transistor T.
2, T7, NPN transistors T3 and T8 as first and second bipolar transistors, an input resistor R1, an output resistor R2, constant current sources S1 to S4, and first and second current mirror circuits 13 and 14. .

The base of the PNP transistor T1 has a first
Input signal Vin1 is input, the emitter of the transistor T1 is connected to the base of the PNP transistor T2,
The collector of the transistor T1 is connected to the ground GND.

An emitter current is supplied to the emitter of the PNP transistor T2 from the power supply VCC through the constant current source S1. Of the two collectors of the PNP transistor T2, one is connected to the emitter of the PNP transistor T1 and the other one is connected to the ground GND. P
The NP transistor T2 reduces the emitter current of the PNP transistor T1 to reduce the emitter current of the PNP transistor T1.
The base current of 1 is reduced.

The current mirror circuit 13 comprises a PNP transistor T4 as a first transistor and a PNP transistor T5 as a third transistor. The emitters of both transistors T4 and T5 are connected to the power supply Vcc, and the bases of both transistors T4 and T5 are connected to the collector of transistor T4.

The constant current source S1 is connected to the base of an NPN transistor T3, and the transistor T3 is supplied with a base current from the identification current source S1. The collector of the NPN transistor T3 is connected to the collector of the PNP transistor T4, and the collector current is supplied to the NPN transistor T3 from the power supply VCC through the PNP transistor T4. The emitter of the NPN transistor T3 is connected to the ground GND via the constant current source S2.

A second terminal is provided at the base of the PNP transistor T6.
Input signal Vin2 is input, the emitter of the transistor T6 is connected to the base of the PNP transistor T7,
The collector of the transistor T6 is connected to the ground GND.

An emitter current is supplied to the emitter of the PNP transistor T7 from the power supply VCC through the constant current source S3. Of the two collectors of the PNP transistor T7, one is connected to the emitter of the PNP transistor T6 and the other one is connected to the ground GND. P
The NP transistor T7 reduces the emitter current of the PNP transistor T6 to reduce the PNP transistor T7.
The base current of 6 is reduced.

The current mirror circuit 14 comprises a PNP transistor T9 as a second transistor and a PNP transistor T10 as a fourth transistor. The emitters of both transistors T9 and T10 are connected to the power supply Vcc, and the bases of both transistors T9 and T10 are connected to the collector of transistor T9.

The base of the NPN transistor T8 is connected to the constant current source S3, and the base current is supplied to the transistor T8 from the identification current source S3. The collector of the NPN transistor T8 is connected to the collector of the PNP transistor T9, and the collector current is supplied to the NPN transistor T8 from the power supply VCC through the PNP transistor T9. The emitter of the NPN transistor T8 is connected to the ground GND via the constant current source S4.

The emitters of both NPN transistors T3 and T8 are connected to each other via an input resistor R1. PNP transistors T5 of the current mirror circuits 13 and 14
The collectors of T10 are connected to each other via the output resistor R2.

The input circuit section 11 receives the input signals Vin1 and Vin from the collectors of the PNP transistors T5 and T10.
The first and second output currents Io1 and Io2 based on 2 are output to the feedback circuit unit 12.

The feedback circuit section 12 includes a PNP transistor T.
11, T16, multi-collector PNP transistor T1
2, T17, PNP transistors T13 and T18 as third and fourth bipolar transistors, and resistors R3 to
R5, operational amplifier OP1, constant current sources S5, S6 and third
The current mirror circuit 15 of FIG.

The reference voltage Vref1 is input to the base of the PNP transistor T16, the emitter of the transistor T16 is connected to the base of the PNP transistor T17,
The collector of the transistor T16 is connected to the ground GND.

An emitter current is supplied to the emitter of the PNP transistor T17 from the power supply VCC through the constant current source S6. Of the two collectors of the PNP transistor T17, one is connected to the emitter of the PNP transistor T16 and the other one is connected to the ground GND. The PNP transistor T17 is the PNP transistor T
By reducing the emitter current of 16, the base current of PNP transistor T16 is reduced.

The current mirror circuit 15 comprises an NPN transistor T14 as a fifth transistor and an NPN transistor T15 as a sixth transistor.
The emitters of both transistors T14 and T15 are ground G
Connected to ND, the bases of both transistors T14 and T15 are connected to the collector of transistor T14.

The base of a PNP transistor T18 is connected to the constant current source S6. The emitter of the PNP transistor T18 is the PNP transistor T1.
The output current Io2 is input to the emitter of the PNP transistor T18. The collector of the PNP transistor T18 is the NPN transistor T1.
It is connected to 5 collectors.

The base of the PNP transistor T11 is connected to the base of the PNP transistor T16 via the resistor R3 and to the ground GND via the resistor R4, and the collector of the transistor T11 is connected to the ground G.
It is connected to ND.

An emitter current is supplied to the emitter of the PNP transistor T12 from the power supply VCC through the constant current source S5. Of the two collectors of the PNP transistor T12, one is connected to the emitter of the PNP transistor T11, and the other one is connected to the ground GND. The PNP transistor T12 is the PNP transistor T
By reducing the emitter current of 11, the base current of the PNP transistor T11 is reduced.

The base of a PNP transistor T13 is connected to the constant current source S5. The emitter of the PNP transistor T13 is the PNP transistor T5.
The output current Io1 is input to the emitter of the PNP transistor T13. The collector of the PNP transistor T13 is the NPN transistor T14.
Connected to the collector.

The inverting input terminal of the operational amplifier OP1 is PNP.
It is connected to the collector of the transistor T18, and a constant voltage is input to the non-inverting input terminal. The output terminal of the operational amplifier OP1 is connected to the PNP transistor T11 via the resistor R5.
Connected to the base of. The operational amplifier OP1 outputs the output signal Vout1 from the output terminal. Therefore, the voltage Vref2 obtained by dividing the output signal Vout1 and the reference voltage Vref1 by the resistors R3 to R5 is input to the base of the PNP transistor T11.

Next, the amplifier circuit 1 configured as described above.
The operation of 0 will be described. Each of the transistors T1 to T3
The base-emitter voltage drop of T6 to T8, T11 to T13, and T16 to T18 is VBET1 to VBET3, VBET6 to VBE.
T8, VBET11 to VBET13, VBET16 to VBET18.

The emitter potential of the transistor T3 is set to V
Letting a be Va = Vin1 + VBET1 + VBET2-VBET3 ────────────────────────────────────────────────────────────────────── ((1)] be the emitter potential of the transistor T8 is Vb. (2)

Here, assuming that the potential difference between the input signals Vin1 and Vin2 is ΔVin, ΔVin = Vin1−Vin2 ─────────── (3)

Further, VBET1 = VBET6 ────────── (4) VBET2 = VBET7 ────────── (5) VBET3 = VBET8 ────────── (6) Then, the voltage between both terminals of the input resistor R1 can be calculated by the equation (1) to
From (6), Va−Vb = Vin1−Vin2 = ΔVin ─────────── (7) Therefore, the current ΔIR1 flowing through the input resistor R1 is ΔIR1 = ΔVin / R1

When the collector currents of the transistors T4 and T5 are ICT4 and ICT5, since the transistors T4 and T5 form the current mirror circuit 13, ICT4 = ICT5 ──────────── (9) .

The emitter current of the transistor T5 is set to IE T5
Then, since the base current of the transistor T5 is sufficiently smaller than its collector current, assuming that the emitter current IET5 of the transistor T5 and the collector current ICT5 of the transistor T5 are equal, ICT5 = IET5 ────────── ( 10) becomes.

Therefore, the current value of the constant current sources S2 and S4 is I
If it is 1, ICT5 = I1 + ΔIR1 ─────────── (11) On the other hand, the collector currents of the transistors T9 and T10 are ICT
9 and ICT10, the transistors T9 and T10 form the current mirror circuit 14, so that ICT9 = ICT10 ─────────── (12).

The emitter current of the transistor T10 is IET
If it is set to 10, the base current of the transistor T10 is sufficiently smaller than the collector current of the transistor T10.
Assuming that the emitter current IET10 of 10 and the collector current ICT10 of the transistor T10 are equal, ICT10 = IET10 ─────────── (13).

Therefore, ICT10 = I1−ΔIR1 ────────── (14) From equations (11) and (14), ICT5-ICT10 = 2 · ΔIR1 ────────── (15) The output current Io1 flowing through the emitter of the PNP transistor T13 is larger by 2ΔIR1 than the output current Io2 flowing through the emitter of the PNP transistor T18. However, since the transistors T14 and T15 form the current mirror circuit 15, the value of the collector current of the transistor T14 is equal to the value of the collector current of the transistor T15.

Therefore, the operational amplifier OP1 raises the emitter potential of the transistor T13, a potential difference is generated across the output resistor R2, and a current ΔIR2 flows through the output resistor R2. When no current flows in or out of the inverting input side of the operational amplifier OP1, Io1 = Io2. At this time, ICT5 = Io1 + ΔIR2 ────────── (16) ICT10 = Io2−ΔIR2 ───────── (17) From equations (16) and (17), ICT5−ICT10 = 2・ ΔIR2 ────────── (18) Therefore, from equations (15) and (18), ΔIR1 = ΔIR2 ───────── (19) Here, both terminals of the output resistance R2 When the inter-electrode voltage is ΔVo, ΔVo = R2 · ΔIR2 ────────── (20).

Therefore, from the equations (8), (19) and (20), ΔVo = R2.ΔIR1 = (R2 / R1) .ΔVin ──────────── (21) Therefore, from the above equation, the amplification factor AV of the input circuit unit 11 is
11 is AV11 = ΔVo / ΔVin = R2 / R1 ────────── (22).

In this way, the amplification factor AV of the input circuit section 11 is
Since 11 is determined only by the resistance values of the input resistance R1 and the output resistance R2, the input / output characteristics of the input circuit section 11 are excellent in linearity.

The relationship between the reference voltage Vref1 and the voltage Vref2 is Vref2 + VBET11 + VBET12 + VBET13-ΔVo-VBET18-VBET17-VBET16 = Vref1 ────────── (23).

Here, VBET11 = VBET16 ────────── (24) VBET12 = VBET17 ───────── (25) VBET13 = VBET18 ───────── (26 ), Vref2 = Vref1 + ΔVo ─────────── (27) is obtained from the equations (23) to (26).

If ΔVo = 0, the output signal V
out1 becomes an output signal Vout1 (0) which is a constant value when the potential difference ΔVin = 0 between the input signals Vin1 and Vin2, and Vref1 =
It becomes Vref2. Therefore, Vref1 / R4 = (Vout1 (0) -Vref1) / R5 ─────── (28), and as a result, Vout1 (0) = Vref1 · (R4 + R5) / R4 ─────── (29) ).

Next, the amplification factor AV12 of the feedback circuit section 12 is obtained. First, assuming that the fluctuation amount of the output signal Vout1 is ΔVout1, ΔVo / R3 + ΔVo / R4 = (ΔVout1−ΔVo) / R5 ───────────── (30) Therefore, ΔVout1 / R5 = ΔVo. (1 / R3 + 1) / R4 + 1 / R5) ───────────────────── (31), and the amplification factor AV12 of the feedback circuit section 12 is AV12 = ΔVout1 / ΔVo = R5. R3 + R4) / (R3 · R4) ────────── (32)

Therefore, the output signal Vou output with respect to the input signals Vin1 and Vin2 input to the amplifier circuit 10.
The amplification factor AV1 of t1 is AV1 = ΔVout1 / ΔVin = (ΔVo / ΔVin) · (ΔVout1 / ΔVo) = AV11 · AV12 = (R2 / R1) · {1 + R5 · (R3 + R4) from the equations (22) and (32). / (R3 ・ R4)} ────────── (33)

Then, the fluctuation amount of the output signal Vout1 is set to ΔVou.
Assuming t1, the fluctuation amount ΔVout1 with respect to the potential difference ΔVin between the input signals Vin1 and Vin2 is ΔVout1 = ΔVin · (R2 / R1) · {1 + R5 · (R3 + R4) / (R3 · R4)} ──────── ─ (34)

As described above, the amplification factor AV1 of the amplifier circuit 10 of this embodiment is the input resistance R1, the output resistance R2, and the resistance R.
Since the resistance value is set to 3 to R5, the amplifier circuit 10 can obtain an input / output characteristic having excellent linearity.

In the input circuit section 11 of the amplifier circuit 10 of this embodiment, the PNP transistors T4 and T5 constitute a current mirror circuit 13, and the PNP transistors T9 and T10 constitute a current mirror circuit 14. Then, the NPN transistors T3 and T
The collector of 8 is connected to the collectors of PNP transistors T4 and T9, respectively.
The collector of 0 is connected to the emitters of PNP transistors T13 and T18 and outputs output currents Io1 and Io2. Therefore, the collector voltages of the NPN transistors T3 and T8 are not limited by the reference voltage Vref1 of the feedback circuit section 12, and the current mirror circuits 13 and 14 lower the power source Vcc by the base-emitter voltage of the PNP transistors T4 and T9. It becomes a value. Therefore, in the range where the emitter voltage of the NPN transistors T3 and T8 is lower than the collector voltage of the NPN transistors T3 and T8,
Even if the voltage range of the first and second input signals Vin1 and Vin2 is expanded, the NPN transistors T3 and T8 can be turned on, the input circuit unit 11 is normally operated, and the input signals Vin1 and Vin2 are input from the amplifier circuit 10. Output signal V based on
Out1 can be output.

Further, in the amplifier circuit 10 of the present embodiment, the output signal Vout1 (0) is set based on the reference voltage Vref1 as shown in the equation (29), so that the value of the reference voltage Vref1 is arbitrarily set. As a result, the value of the output signal Vout1 (0) can be set arbitrarily.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. The same components as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

The amplifier circuit 16 of this embodiment includes the input circuit section 11 and the feedback circuit section 17. Feedback circuit section 17
Are PNP transistors T21 and T26, multi-collector PNP transistors T22 and T27, and PNP transistor T as third and fourth bipolar transistors.
23, T28, resistors R13 to R15, operational amplifier OP
2. The constant current sources S15 and S16 and the third current mirror circuit 18 are provided. First output current I of the input circuit unit 11
o1 is input to the emitter of the PNP transistor T28,
The second output current Io2 is input to the emitter of the PNP transistor T23.

The reference voltage Vref1 is input to the base of the PNP transistor T26, the emitter of the transistor T26 is connected to the base of the PNP transistor T27,
The collector of the transistor T26 is connected to the ground GND.

The emitter of the PNP transistor T27 is supplied with the emitter current from the power source Vcc through the constant current source S16. Of the two collectors of the PNP transistor T27, one is connected to the emitter of the PNP transistor T26, and the other one is connected to the ground GND. The PNP transistor T27 is the PNP transistor T
By reducing the emitter current of 26, the base current of PNP transistor T26 is reduced.

The current mirror circuit 18 comprises an NPN transistor T24 as a fifth transistor and an NPN transistor T25 as a sixth transistor.
The emitters of both transistors T24 and T25 are ground G
Connected to ND, the bases of both transistors T24 and T25 are connected to the collector of the transistor T24.

The base of a PNP transistor T28 is connected to the constant current source S16. The emitter of the PNP transistor T28 is the PNP transistor T
The output current Io1 is input to the emitter of the PNP transistor T28. The collector of the PNP transistor T28 is the NPN transistor T2.
It is connected to 5 collectors.

The base of the PNP transistor T21 is connected to the base of the PNP transistor T26 via the resistor R13, and the ground GND is connected via the resistor R14.
The collector of the transistor T21 is connected to the ground GND.

The emitter of the PNP transistor T22 is supplied with the emitter current from the power source Vcc through the constant current source S15. Of the two collectors of the PNP transistor T22, one is connected to the emitter of the PNP transistor T21 and the other one is connected to the ground GND. The PNP transistor T22 is the PNP transistor T
By reducing the emitter current of 21, the base current of the PNP transistor T21 is reduced.

The base of a PNP transistor T23 is connected to the constant current source S15. The emitter of the PNP transistor T23 is the PNP transistor T
10 is connected to the collector of PNP transistor T23
The output current Io2 is input to the emitter of the. PNP
The collector of the transistor T23 is an NPN transistor T
It is connected to 24 collectors.

The inverting input terminal of the operational amplifier OP2 is PNP.
It is connected to the collector of the transistor T28, and a constant voltage is input to the non-inverting input terminal. The output terminal of the operational amplifier OP2 is connected to the PNP transistor T2 via the resistor R15.
1 is connected to the base. The operational amplifier OP2 outputs the output signal Vout2 from the output terminal. Therefore, at the base of the PNP transistor T21, a voltage Vref3 obtained by dividing the output signal Vout2 and the reference voltage Vref1 by the resistors R13 to R15.
Is entered.

The feedback circuit section 17 has the same circuit configuration as the feedback circuit section 12, and the corresponding elements are formed in the same size and have the same electrical characteristics. That is, each of the transistors T11 to T16 of the feedback circuit unit 12 and the feedback circuit unit 17
The transistors T21 to T26 are formed to have the same size and have the same electric characteristics. In addition, constant current sources S5, S
The current supplied from 6 has the same magnitude as the current supplied from the constant current sources S15 and S16, and the operational amplifier OP1
And the operational amplifier OP2 have the same amplification factor. Furthermore, the resistance values of the resistors R3 to R5 and the corresponding resistors R13 to R15 are the same. Therefore, the characteristics of the feedback circuit section 12 and the feedback circuit section 17 are also the same, and the voltage V
The ref2 and the voltage Vref3 across the resistor R13 are equal.

In the amplifier circuit 16 configured as above, when the variation amount of the output signal Vout2 is ΔVout2, the variation amount ΔV with respect to the potential difference ΔVin between the input signals Vin1 and Vin2.
out2 is −ΔVo / R14 = (ΔVout2 + ΔVo) / R15 + ΔVo / R13 ────────── (35) Therefore, ΔVout2 = −ΔVo ・ {1 + R15 ・ (R13 + R14) / (R13 ・ R14)} = − ΔVin · (R2 / R1) · {1 + R15 · (R13 + R14) / (R13 · R14)} ────────── (36)

Here, the feedback circuit section 12 and the feedback circuit section 17
And have the same configuration and characteristics. Therefore, the formula (3
From (4) and (36), it can be seen that ΔVout2 = −ΔVout1 ─────────── (37), and the phase of the output signal Vout2 is inverted with respect to the output signal Vout1. Therefore, it can be seen that the output signal Vout2 of the amplifier circuit 16 is inverted in phase with respect to the output signal Vout1 of the amplifier circuit 10.

Therefore, in the amplifier circuit 16, the output current Io1,
Io2 can be input to the emitters of the PNP transistor T28 (fourth bipolar transistor) and the PNP transistor T23 (third bipolar transistor) to form an inverting amplifier circuit having the same amplification factor as the amplifier circuit 10. it can.

Since the input circuit section 11 is used also in the amplifier circuit 16 of this embodiment, even if the voltage range of the first and second input signals Vin1 and Vin2 is expanded, the input signals Vin1 and Vin2 are expanded. It is possible to output the output signal Vout2 based on

[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. The amplifier circuit 19 of this embodiment is
The input circuit unit 11 (shown in FIGS. 2 and 3), the feedback circuit unit 12 (shown in FIG. 2), and the feedback circuit unit 17
(Shown in FIG. 3) and outputs two output signals having mutually opposite phases.

That is, the output current Io1 is input to the emitter of the PNP transistor T13 (third bipolar transistor) of the feedback circuit section 12, and the PNP transistor T13 is supplied.
The output current Io2 is input to the emitter of 18 (fourth bipolar transistor). PNP of the feedback circuit unit 17
Transistor T28 (fourth bipolar transistor)
Of the PNP transistor T23 (third bipolar transistor) is supplied with the output current Io2.

Then, the feedback circuit section 12 and the feedback circuit section 17
Have the same configuration and electrical characteristics, the feedback circuit unit 1
Output signals Vout1 and Vout2 having opposite phases from 2 and 17
Can be obtained.

In the amplifier circuit 19 of this embodiment, feedback circuits 12 and 17 having the same circuit configuration and the same electric characteristics are connected to one input circuit section 11 to provide outputs having opposite phases. The signals Vout1 and Vout2 are obtained.
Therefore, the amplifier circuit 19 need only be provided with one input circuit section 11 as compared with the case where two amplifier circuits 10 and 16 are provided to obtain the output signals Vout1 and Vout2, and the number of elements constituting the amplifier circuit 19 is increased. Can be suppressed. Further, even if the amplification factors of the feedback circuit units 12 and 17 vary due to variations in the manufacturing process, the input circuit unit 11 is common to the feedback circuit units 12 and 17. Therefore, the output signal Vout of the feedback circuit units 12 and 17
The difference between the amplification factors of 1 and Vout2 can be reduced, and the relative accuracy of the output signals Vout1 and Vout2 can be improved.

The present invention can be embodied by being arbitrarily modified as follows. (A) Two feedback circuit units 12 may be connected to the input circuit unit 11 and a plurality of output signals in phase may be obtained from each feedback circuit unit 12. Also in this case, it is only necessary to provide one input circuit section 11 for the two output signals,
It is possible to suppress an increase in the number of elements forming the amplifier circuit and improve the relative accuracy of each output signal even if the amplification factors of the two feedback circuit units 12 vary.

(B) An arbitrary number of feedback circuit units of three or more may be connected to the input circuit unit 11 for implementation. Also in this case, the input circuit unit 11 is set to 1 for two output signals.
It is only necessary to provide one and it is possible to suppress an increase in the number of elements constituting the amplifier circuit. At this time, all the output signals output from the feedback circuit units may be connected so as to have the same phase, or at least one output signal may be connected so as to have an opposite phase to the other output signals. Good. In this case, the amplification circuit may be formed by arbitrarily setting the ratio of the output signal having the same phase and the output signal having the opposite phase.

(C) The amplifier circuit has a bi-CMOS structure including a bipolar transistor and a CMOS transistor, and the first and second current mirror circuits 13 and 14 are provided.
Each of which is composed of a pair of PMOS transistors, and each of the third current mirror circuits 15 and 18 has N transistors.
Consist of a MOS transistor pair.

[0088]

As described in detail above, according to the first aspect of the invention, the voltage range of the input signal can be expanded.

According to the second aspect of the present invention, it is possible to obtain output signals of opposite phases from the plurality of feedback circuit sections and reduce relative errors of the plurality of output signals output from the plurality of feedback circuit sections. The relative accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an amplifier circuit of the first embodiment.

FIG. 3 is a circuit diagram showing an amplifier circuit according to a second embodiment.

FIG. 4 is a circuit diagram showing an amplifier circuit according to a third embodiment.

FIG. 5 is a circuit diagram showing a conventional amplifier circuit.

[Explanation of symbols]

1 Input Circuit Section 2 Feedback Circuit Section 13 First Current Mirror Circuit 14 Second Current Mirror Circuit 15 Third Current Mirror Circuit Io1 First Output Current Io2 Second Output Current OP1, OP2 Operational Amplifier R1 Input Resistance R2 Output resistance R3, R4, R5, R13, R14, R15 Resistance T3 NPN transistor as first bipolar transistor T4 NPN transistor as first transistor T5 NPN transistor as third transistor T8 As second bipolar transistor NPN transistor T9 NPN transistor as second transistor T10 NPN transistor as fourth transistor T13 PNP as third bipolar transistor
Transistor T14 NPN transistor as fifth transistor T15 NPN transistor as sixth transistor T18 PNP as fourth bipolar transistor
Transistor Vin1 First input signal Vin2 Second input signal Vout1, Vout2 Output signal Vref1 Reference voltage Vref2 Voltage

Claims (2)

[Claims] 1. The emitters of the first and second bipolar transistors are connected to each other via an input resistor, and the collectors of the first and second bipolar transistors are connected to the first and second transistors, respectively. The first transistor and the third transistor form a first current mirror circuit, and the second transistor and the fourth transistor form a second current mirror circuit. Transistors are connected to each other through an output resistor, first and second input signals are input to the emitters of the first and second bipolar transistors, respectively, and the first and second transistors are output from the third and fourth transistors. The input circuit section which outputs the output current of 2 and the emitters of the third and fourth bipolar transistors, respectively. Beauty a second output current respectively inputted, the third
The collectors of the fourth and fourth bipolar transistors are respectively connected to the fifth and sixth transistors that form the third current mirror circuit, and the reference voltage is input to the base of the fourth bipolar transistor, and the fourth bipolar transistor is connected to the fourth bipolar transistor. The collector of the bipolar transistor is connected to the input terminal of the operational amplifier, outputs an output signal from the operational amplifier, and feeds back a voltage obtained by dividing the output signal and the reference voltage by a resistor to the base of the third bipolar transistor. An amplifier circuit including a feedback circuit unit for inputting as a signal. 2. A plurality of feedback circuit units, comprising at least one
One feedback circuit unit is connected to the input circuit unit so that the second and first output currents are input to the emitters of the third and fourth bipolar transistors, and the other feedback circuit unit is The amplifier circuit according to claim 1, wherein the amplifier circuits are connected to the input circuit section so that the first and second output currents are input to the emitters of the third and fourth bipolar transistors, respectively.