JPH11312931A - Gm cell and current interpolation a/d converter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gm cell reduced in power consumption and capable of quickly resetting. SOLUTION: This cell is provided with a current source 30a which includes a differential amplifier 52, a differential amplifier 53, an output part 50 and an output part 51 and further has one end connected to a power source line 47 (a voltage VDD), a PMOSFET 43 with a drain terminal connected to the current source 30a, and a current source 35 (a current Ir ) connected between a source terminal of this PMOSFET 43 and a power source line 47. The device is also equipped with a current source 30 one end of which is connected to the power source line 47. a PMOSFET 44 a drain terminal of which is connected to the current source 30b, and a current source 36 (the current Ir ) connected between the source terminal of this PMOSFET 44 and the power source line 47, and the gate terminals of the MPOSFET 43 and the PMOSFET 43 have a fixed bias voltage VB applied to.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a gm cell and a current interpolation A / D converter using the gm cell.

[0002]

2. Description of the Related Art A conventional current interpolation A / D converter of this type is disclosed in, for example, "IEEE Journal of
Solid-State Circuits, VOL. 31, NO. 7, July 1996; "A 17
5MS / S, 6b, 160mW, 3.3V CMOS A / D Converter "".

In particular, FIG. 2 (FIG. 2) of this document shows a block diagram of this current interpolation AD converter. This current interpolation AD
In the converter, first, the gm cell 1 provided in the preceding stage is used.
To each of the analog input voltage input and two predetermined reference voltages ref. top (higher reference voltage)
And ref. A reference voltage divided by a predetermined division pattern between bottom (lower reference voltage) is input.

[0004] Each gm cell outputs a differential current proportional to the voltage difference inputted thereto. Specifically, FIG.
As shown in the figure, the gm cell 20 has a P input 21 and an N input 2
2 as an input terminal, a P output 23 with an output current of Ip, and an N output 24 with an output current of In as an output terminal, and “Ip = (Vp−Vn) · gm, I
n = − (Vp−Vn) · gm, where Vp and Vn are the voltages applied to the P input 21 and the N input 22, respectively.
ref ".

[0005] Further, an interpolating circuit interpolates each differential current with a current further divided between adjacent gm cells. The principle of this interpolation itself is described in FIG.
(Fig.3: In case of differential current, Fig.4 (Fig.3
This principle will not be described in detail in the present specification because it has been described in detail using)).

In the above document, each differential current is interpolated by further dividing the current into six different currents between adjacent gm cells, so that 11 × 6 = 66 differential currents are output. You. Then, the comparator
The (tor) unit compares each of the interpolated differential currents and outputs a comparison result. The comparison result is, for example, “000” from the upper side to the lower side, ie, from the gm1 side to the gm12 side.
0 ... 001111 ... 111 "becomes 66 digital signals. In addition, digital decoding (digit
al decoding) performs digital-to-analog conversion by outputting a digital signal in accordance with a predetermined rule based on the comparison result. The principle of the AD conversion is the same as that of the flash AD.

FIG. 4 shows nine gm cells (gm cells 0 to gm).
FIG. 9 is a schematic explanatory view showing operations of an m cell 8), an interpolator, and a plurality of comparators, and shows a case where each interpolator divides a differential current between gm cells into eight. FIG. 4 shows, as a representative example, a state where each of the P output and the N output of the gm cell 8 is divided into eight.

Each current is compared by a corresponding comparator, and the comparison result is output. In this case, 64 comparators are provided. FIG. 5 shows each g when the sine wave voltage Vin is input.
The output waveform of m cells is shown. In the circuit shown in FIG. top and ref. As for the reference voltage obtained by the voltage dividing circuit using the resistor between the bottoms, the reference voltage input to gm8 becomes the maximum and the reference voltage input to gm0 becomes the minimum.

When a certain voltage Vin is input, as described above, since the reference voltage input to gm8 is the maximum, the P output current becomes minimum and the N output current becomes maximum according to the above equation. Conversely, since the reference voltage input to gm0 is the minimum, the P output current is maximized and the N output current is minimized according to the above-described equation. Therefore, the P output and the N output are inverted at a certain gm cell.

The P output and the N output are each output to an interpolator, and the interpolator divides the P output current of gm8 and the P output current of gm7 into eight and performs an interpolation operation of the differential current. Similarly, the N output current is similarly divided into eight to perform the differential current interpolation operation. These are P1, P
2, ..., P7, P8, N1, N2, ..., N7, N8. Similarly, hereinafter, gm7 and gm6, gm6 and gm5,
.., The interpolation operation is performed by dividing the output current into eight. As a result, since the P output and the N output are divided into 64, the comparators P1 and N1, P2 and N2,.
64 and outputs the result of the comparison. as a result,
64 digital signals "000000 ... 001111 ..."
111 "is output.

Referring to FIG. 5, when a sine wave is input as an input signal, the P output waveform and the N output waveform of gm4 are respectively symmetric, but the P output becomes positive as the cell moves to the gm0 side. , The N output moves in the zero direction. Similarly, as we move to the cell on the gm8 side,
The P output moves in the 0 direction, and the N output moves in the positive direction.

[0012]

By the way, in the conventional circuit, all the gm cells are operated linearly without performing the clamp operation. In order for all gm cells to operate linearly, Von of the transistors of the input differential pair of gm cells
(“Vgs (gate-source voltage) −Vt (threshold voltage)”) in the input range (“ref. Top-ref.
bottom ”) or more. That is, if Id is a drain current, k ′ is a constant, W is a gate width, and L is a gate length, “Von = √ (Id / k ′ (W / L))>
It is necessary to satisfy the condition of "input range", and there is a constraint between the transistor size and the bias current. Here, when the transistor size W / L is reduced, the offset of the A / D conversion increases due to the variation of the elements. Therefore, a certain size transistor size is required.

Further, there is a demand for increasing the gm value (gain) in order to improve the A / D conversion accuracy.
m = √ (4k ′ (W / L) Id) ”holds, so that to increase the gm value, it is necessary to increase W / L, but on the other hand, it is desirable to set the current Id to a value that is so large. There is also a problem that there is no. However, as long as the above-described constraints exist, it is necessary to flow an unnecessarily large current, so that the current consumption in the related art is large.

Therefore, current consumption is not increased and W
To increase the gm value by increasing / L to some extent,
What is necessary is just to eliminate the above-mentioned constraint condition. That is, gm where the input voltage is close to the reference voltage
Only the cell needs to be operated linearly, specifically, to reduce the current range. When the P output and the N output approach each near 0, clipping occurs without linear operation and the inverted current is also the same. Clip to

FIG. 5 also shows the state of such a current. For example, the P output of gm8 approaches 0 and clips.
Its inverted output is also clipped. Similarly, N of gm0
The output also approaches 0 and clips.

However, as a result of comparing the P output and the N output, the result of the clipping does not change,
Only the portion where the P output and the N output are inverted affects the output. However, the part where the P output and the N output are inverted should operate linearly, but this is not the case. FIG. 6 shows such a state.

In FIG. 6, the horizontal axis represents time, and the vertical axis represents output current. When the P output current approaches 0 and returns to the linear operation state again (hereinafter referred to as “return”), the P output and the N when the linear operation state has been passed for a while have passed.
The intersection of the outputs is shifted, and the current value for the intersection A and the current value for the intersection B are different as shown in the figure. That is, complete linear operation is not immediately performed immediately after the return, and there is a problem that such a shift of the intersection causes hysteresis in the output code as a result of the AD conversion, so that an accurate AD conversion operation cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a gm cell which consumes low power and can quickly perform a return operation. Another object of the present invention is to provide a highly accurate current interpolation A / D converter using the gm cell.

[0019]

According to the first aspect of the present invention, there is provided a gm cell for flowing a differential current according to an input signal difference. A differential amplifier unit for amplifying the input signal difference, and an output unit having at least one of a P output and an N output,
A current source for flowing a current of a predetermined value is connected to the output unit, and the current flowing to the output unit is configured not to be smaller than the predetermined value. A gm cell is provided, wherein each of the gm cells is configured to connect a diode-connected transistor so that a drain voltage value of each of the differential transistors is limited to a predetermined value.

Here, the limitation of the drain voltage value within the predetermined value includes, for example, preventing the drain voltage from dropping below the predetermined voltage value. According to the present invention, the current from the current source is supplied to the P output section and the N output section, and a current that does not become smaller than a predetermined value flows to the transistor constituting the output section, thereby preventing the transistor from being turned off. In addition, when the differential transistor draws an excessive current, the drain voltage of the differential transistor is prevented from dropping below a predetermined voltage, and the recovery speed can be improved.

According to a second aspect of the present invention, a plurality of gm cells including at least one gm cell according to the first aspect and the differential current are divided into a plurality of types of currents between adjacent gm cells. An interpolation unit for interpolating with current,
A comparison circuit that compares each of the interpolated differential currents and outputs a result of the comparison, and a logic circuit that outputs a digital signal according to a predetermined rule based on the comparison result. Is a current interpolation A / D converter.

The gm cell according to claim 1 may be used particularly for a gm cell where an output clamp occurs. That is, in claim 2, the g according to claim 1
A current interpolation A / D converter is also conceivable in which the m cell is used for the gm cell where the output clamp occurs.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a fully differential folded cascode type gm cell according to an embodiment of the present invention.

This gm cell includes a differential amplifier 52, a differential amplifier 53, an output unit 50, and an output unit 51, and further has a current source connected at one end to a power supply line 47 (voltage VDD). 30a and a P having a drain terminal connected thereto.
MOSFET (hereinafter “P-type MOSFET” is simply referred to as “PM
OSFET) 43 and the PMOSFET 43
Current source 35 (current I _r ) connected between the power supply line 47 and a current source 30b having one end connected to the power supply line 47, and a PMOSFET 44 having a drain terminal connected to the current source 30b. And this PMOS
A current source 36 (current I _r ) connected between the source terminal of the FET 44 and the power supply line 47;
A fixed bias voltage V _B is applied to the gate terminals of the SFET 43 and the PMOSFET 44.

The differential amplifier 52 includes a transistor NMOSFET 38 (hereinafter, simply referred to as an “NMOSFET”) 38 constituting a differential pair, an NMOSFET
39, a constant current source 30c connected to the source terminals of both transistors, an NMOSFET 38 and a power supply line 4
7 and an NMOSFET 37 which is diode-connected (connects the drain terminal and the gate terminal).

The differential amplifier 53 includes transistors NMOSFET 40 and NMOSFET 41 forming a differential pair,
A constant current source 30d connected to the source terminals of these two transistors, and a diode-connected NMOSFET 37 provided between the NMOSFET 41 and the power supply line 47.
And

The current source 30a and the PMOSFET 43
And NMOSFET 37 and NMOSFET 3
8 and the drain terminal of the NMOSFET 40 have a common potential, while the current source 30b and the PMO
The connection point with the SFET 44, the NMOSFET 42 and the NM
The connection point with the OSFET 41 and the drain terminal of the NMOSFET 39 have a common potential.

The output unit 50 is a diode-connected NMO
It comprises an SFET 45, and its gate terminal is an N output. The output unit 51 is composed of a diode-connected NMOSFET 46, and its gate terminal is a P output.

The current sources 30a and 30b are constant current sources for supplying currents of the same current value, and the current sources 30c and 30d are constant current sources for supplying currents of the same current value. The fixed voltages Vrefp and Vrefn are applied to the respective gate terminals.

Now, the drain current of the NMOSFET 38,
Drain current of NMOSFET 39, PMOSFET4
3 and the drain current of the PMOSFET 44 as Ia, Ib, Ic and Id, respectively,
The gate terminals of the FET 38 and the NMOFET 41 (Vi
Suppose that a sine wave is applied between (np, Vinn) and the voltage of Vinp rises. As a result, when the current Ia increases,
Since the current source 30c is a constant current source, the current Ib decreases. When the current Ia increases, the current Ic decreases because the current source 30a is a constant current source, and the N output decreases. On the other hand, the current Ib
Decreases, the current Id is constant because the current source 30b is a constant current source.
Increases, and the P output increases.

On the other hand, if the voltage of Vinp decreases, the current Ia decreases, and the current Ib increases because the current source 30c is a constant current source. When the current Ia decreases, the current Ic increases because the current source 30a is a constant current source, and the N output increases. When the current Ib increases, the current source 30b
Is a constant current source, the current Id decreases, and the P output decreases. In this description, the operation has been described with particular attention to the operation of the differential amplifier 52. However, when the gm cell performs the full differential operation,
The output when a sine wave is input is as shown in FIG.

[0032] Incidentally, s current source 35 and 36 respectively, always supplied to the output unit 50, 51 a constant current I _r, P output, N output will not be less than a predetermined value. That is,
By providing the current sources 35 and 36, the NMOS FE
This makes it possible to improve the return speed by preventing T45 and 46 from being turned off.

The NMOSFET 37 and the NMOSFE
T42 prevents the drain voltage from dropping below a predetermined voltage even when the MOSFET of the differential pair draws an excessive current, so that the recovery speed can be improved.

Therefore, according to this gm cell, FIG.
No hysteresis as shown in FIG. FIG. 8 is a waveform diagram of the P output and the N output of this gm cell, where the horizontal axis represents time and the vertical axis represents output current. Since P output current is restored to not less than I _r (about 270Myuei) improves recovery speed, the intersection point C of the P output and the N output, without D is shifted, the current for the current value and the intersection D with respect to the intersection point C The value becomes the same and the occurrence of hysteresis in the output code does not occur. Moreover, only a slight change in the circuit configuration without increasing power consumption,
The occurrence of such hysteresis can be prevented.

FIG. 2 is a circuit diagram of a single output (single ended) folded cascode type gm cell according to another embodiment of the present invention. The gm cell includes a differential amplifier 70 and an output unit 71, and further includes a current source 60b having one end connected to a power supply line (power supply voltage VDD) 47,
60c, 61 (current value I _r ), 62 (current value I _r );
A PMOSFET 63 having a drain terminal connected to the current source 60b and a source terminal connected to the current source 61, and a drain terminal connected to the current source 60c and a source terminal connected to the current source 62.
And a PMOSFET 64 connected to the PMOSFET.
Further, a PMOSFET 63 and a PMOSFET 64
Is applied with a fixed bias voltage.

The differential amplifier 70 includes transistors NMOSFET 56 and NMOSFET 57 forming a differential pair,
A constant current source 60a connected to the source terminals of both transistors, and a diode-connected NMOSFET 54 provided between the NMOSFET 56 and the power supply line 58.
And a diode-connected NMOSFET 55 provided between the NMOSFET 57 and the power supply line 58.

The NMOSFET 54 and the NMOS FE
Connection point with T56, current source 60b and PMOSFET 6
3 has a common potential and the NMO
The connection point between the SFET 55 and the NMOSFET 57 and the connection point between the current source 60c and the PMOSFET 64 have a common potential.

The output unit 71 includes an NMOSFET 58 and an NM
A current mirror connection is made with the OSFET 59, and the drain terminal of the NMOSFET 59 is a P output terminal. Further, the current sources 60b and 60c are constant current sources that supply currents of the same current value.
A fixed voltage Vref is applied to the gate terminal 57.

Now, the drain current of the NMOSFET 56,
Drain current of NMOSFET 57, PMOSFET 6
3 as Ie, If, Ig, and Ih, respectively.
Applying a sine wave to the gate terminal (Vin) of the FET 56,
It is assumed that the voltage of Vin increases. As a result, when the current Ie increases, the current If decreases because the current source 60a is a constant current source. When the current Ie increases, the current Ig decreases because the current source 60b is a constant current source. On the other hand, when the current If decreases, the current Ih increases because the current source 60c is a constant current source, and the P output increases. I do.

On the other hand, if the voltage of Vin falls,
The current Ie decreases, and the current If increases because the current source 60a is a constant current source. When the current Ie decreases, the current source 60
b is a constant current source, the current Ig increases, and the current If
Increases, current source 60c is a constant current source and current Ih
Decreases, and the P output decreases. This is a single output gm
This is the operation of the cell.

By the way, even in this gm cell, the current
The sources 61 and 62 each have a constant current I _rTo the output unit 71.
And the P output does not become smaller than the predetermined value.
No. That is, by providing the current sources 61 and 62, N
MOSFETs 58 and 59 are not turned off
To improve the return speed.

The NMOSFET 54 and the NMOSFE
T55 prevents the drain voltage from dropping below a predetermined voltage even when the MOSFET of the differential pair draws an excessive current, so that it is possible to improve the recovery speed.

Thus, g according to this embodiment is
Even in the m cell, the occurrence of hysteresis in the output code does not occur. Moreover, the occurrence of such hysteresis can be prevented by only slightly changing the circuit configuration without increasing the power consumption.

FIG. 9 shows a block diagram of a current interpolation A / D converter using such a gm cell. This AD converter has a gm cell unit 100 including a plurality of gm cells, an interpolation 200 unit, a comparison circuit 300, and a logic circuit 400.

It is not always necessary to use all the gm cells according to the present embodiment as gm cells. Particularly, in such a conventional AD converter of this type, an output clamp is generated.
The gm cell of the present invention may be used instead of the m cell.

Now, each gm constituting the gm cell unit 100 will be described.
The cell outputs a differential current according to the input voltage. Then, the interpolation unit 200 interpolates the differential current output from each gm cell with a current divided into a plurality of types of currents between adjacent gm cells.

Further, the comparison circuit 300 compares each of the interpolated differential currents and outputs a comparison result, and the logic circuit 400 outputs a digital signal according to a predetermined rule based on the comparison result. I do. In this way, the analog signal input is converted to a digital signal by the AD.
A conversion operation is performed.

According to this AD converter, since the gm cell as described above is used, the digital code as the AD conversion result does not have hysteresis, and high-precision AD conversion can be performed. Also, a diode-connected MO
Since the gm cell can be improved by a simple change of the configuration such as addition of an SFET and a current source, the power consumption during AD conversion does not need to be increased much as compared with the conventional case, and an increase in manufacturing cost can be suppressed.

[0049]

As described above, according to the first aspect of the present invention, a current source is connected to the output section so that the current flowing through the output section does not become smaller than a predetermined value, and each of the differential transistors has By connecting diode-connected transistors, the drain voltage value of each of the differential transistors is configured to be limited to a predetermined value, thereby realizing a gm cell with low power consumption and high recovery speed. It becomes possible.

According to the second aspect of the present invention, the current interpolation A / D converter is configured using such a gm cell.
An effect is obtained that hysteresis does not occur in the digital code as the AD conversion result.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a gm cell according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a gm cell according to another embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional gm cell.

FIG. 4 is a schematic explanatory diagram of an operation of a conventional current interpolation AD converter.

FIG. 5 is a schematic diagram illustrating the operation of a conventional current interpolation AD converter.

FIG. 6 is an explanatory diagram of an operation of a conventional gm cell.

FIG. 7 is an explanatory diagram of an operation of a gm cell.

FIG. 8 is an explanatory diagram of an operation of a gm cell.

FIG. 9 is a block diagram of a current interpolation AD converter according to the embodiment of the present invention.

[Explanation of symbols]

37, 38, 39, 40, 41, 42, 45, 46 N
MOSFET 43 PMOSFET 44 PMOSFET 47 Power line 30a Current source 30b Current source 30c Current source 30d Current source 35 Current source 36 Current source 47 Power line 50 Output unit 51 Output unit 52 Differential amplification unit 53 Differential amplification unit 60a Current source 60b Current Source 60c Current source 61 Current source 62 Current source 54, 55, 56, 57, 58, 59 NMOSFET 63 PMOSFET 64 PMOSFET 70 Differential amplification unit 71 Output unit 100 gm cell unit 200 Interpolation unit 300 Comparison circuit 400 Logic circuit

Claims (2)

[Claims] 1. A gm through which a differential current corresponding to an input signal difference flows.
A cell, comprising: a differential amplifying unit for amplifying the input signal difference; and an output unit having at least one of a P output and an N output, wherein a current source for flowing a current of a predetermined value is connected to the output unit. A current flowing through the output unit is not less than the predetermined value, and each of the differential transistors constituting the differential amplifying unit includes
A gm cell, wherein a diode-connected transistor is connected so that a drain voltage value of each of the differential transistors is limited to a predetermined value. 2. A plurality of gm cells including at least one gm cell according to claim 1, and an interpolator for interpolating the differential current with a current divided into a plurality of types of currents between adjacent gm cells. A comparison circuit that compares each of the interpolated differential currents and outputs a result of the comparison, and a logic circuit that outputs a digital signal according to a predetermined rule based on the result of the comparison. A current interpolation A / D converter.