JP2023039271A - Current sense circuit, and dc/dc converter - Google Patents

Abstract

To provide a current sense circuit capable of widening an in-phase input range while reducing the size of a circuit scale, and a DC/DC converter.SOLUTION: Resistors R4 and R5 are connected in series between a junction point between an emitter of a transistor Q1 and a resistor R1 and a junction point between an emitter of a transistor Q2 and a resistor R2. A voltage V1 at a junction point between the resistor R4 and the resistor R5 and a predetermined voltage (V+-V2) are compared and when the junction point voltage V1 is higher than the predetermined voltage (V+-V2), a current I1 flows through transistors MP6 and MN5, a current M×I1 flows through a transistor MN4, and a current M×I1/2 flows from the resistor R1 and the resistor R2 toward a junction point between the resistors R4 and R5.SELECTED DRAWING: Figure 2

Description

The present invention relates to current sense circuits and DC/DC converters.

As a current sense circuit that outputs a current detection signal Vis corresponding to the voltage drop occurring in the sense resistor Rs, the one described in Patent Document 1, for example, has been proposed. The current sensing circuit described in Patent Document 1 includes transistors Q11 to Q13 and resistors R11 to R15, as shown in FIG. Transistors Q11-Q13 are composed of PNP transistors.

The base-emitter voltage V _BEQ11 of transistor Q11 must be higher than the minimum operating voltage V _BEQ11MIN as shown in equation (1) below.
_VBEQ11 =VIN-(VR13+VR11)> _VBEQ11MIN (1)
VIN: Input voltage input to one end of sense resistor Rs VR13: Voltage across resistor R13 VR11: Voltage across resistor R11

Therefore, the common-mode input voltage of the input voltage VIN becomes as shown in the following equation (2), and cannot handle a low input voltage VIN.
VIN>VR13+VR11+ _VBEQ11MIN (2)

That is, the conventional current sensing circuit has a problem that the range of the common mode input voltage is narrow. Therefore, a technique has been proposed to widen the common-mode input range by providing an operational amplifier effective when the common-mode input range is low and an operational amplifier effective when the common-mode input range is high (Patent Document 2).

However, the technique of Patent Document 2 requires two operational amplifiers, resulting in a large circuit scale and an increased chip size.

U.S. Pat. No. 5,378,998 JP 2018-179571 A

SUMMARY OF THE INVENTION It is an object of the present invention to provide a current sensing circuit and a DC/DC converter capable of widening the common-mode input range while reducing the size of the circuit. be.

In order to achieve the above object, a current sensing circuit and a DC/DC converter according to the present invention are characterized by the following [1] to [6].
[1]
A current sense circuit that outputs a current detection signal corresponding to a voltage drop occurring in a sense resistor,
a first transistor having a collector-emitter connected between a power supply line to which a second input voltage is supplied and one end of the sense resistor;
a second transistor having a collector-emitter connected between the power supply line and the other end of the sense resistor, a base connected to the base of the first transistor, and a base-collector connected;
a first resistor connected between one end of the sense resistor and an emitter of the first transistor;
a second resistor connected between the other end of the sense resistor and the emitter of the second transistor and having the same resistance value as the first resistor;
a third transistor having an emitter connected to the emitter of the second transistor and a base connected to the collector of the first transistor;
a current detection signal generating circuit having a third resistor connected between the power supply line and the collector of the third transistor;
Fourth resistors having the same resistance value are connected in series between a connection point between the emitter of the first transistor and the first resistor and a connection point between the emitter of the second transistor and the second resistor. a resistor and a fifth resistor;
A voltage corresponding to a first input voltage input to one end of the sense resistor is compared with a predetermined voltage, and if the voltage corresponding to the first input voltage is higher than the predetermined voltage, one end of the sense resistor and and a common-mode input range expansion circuit including a current supply circuit for supplying a current from the other end of the sense resistor to a connection point between the fourth resistor and the fifth resistor.
[2]
The current sense circuit according to [1],
The current supply circuit is
a fourth transistor and a fifth transistor having sources connected together; and a first current source supplying current to the fourth transistor and the fifth transistor, the gate of the fourth transistor. a comparator circuit supplied with a voltage corresponding to the first input voltage to the gate of the fifth transistor and the predetermined voltage supplied to the gate of the fifth transistor;
A current sensing circuit comprising: a first current mirror circuit that causes a current corresponding to a current flowing through the fifth transistor to flow out from a connection point between the fourth resistor and the fifth resistor.
[3]
The current sense circuit according to [1] or [2],
A voltage corresponding to the first input voltage is a connection point voltage between the fourth resistor and the fifth resistor.
[4]
The current sensing circuit according to any one of [1] to [3],
The common-mode input range expansion circuit includes:
a plurality of sixth transistors diode-connected and connected in series with each other; and a second current source supplying current to the sixth transistors, wherein a voltage is generated across the plurality of sixth transistors. a current sense circuit including a voltage generating circuit that generates the predetermined voltage according to the current sensing circuit.
[5]
The current sensing circuit according to any one of [1] to [4],
a third current source that supplies a constant current;
a second current mirror circuit that copies the current of the third current source and supplies it to the collectors of the first transistor and the second transistor, respectively;
a third current mirror circuit that copies the current of the third current source and passes the copied current from the emitters of the first transistor and the second transistor toward ground. be a current sense circuit with
[6]
a coil;
a capacitor to which one end of the coil is connected;
a seventh transistor provided between a voltage source to which a second input voltage is supplied and the other end of the coil for turning on and off supply of the second input voltage to the coil;
a sense resistor provided between one end of the coil and the capacitor;
A DC/DC converter comprising a control circuit for controlling on/off of the seventh transistor to output an output voltage obtained by converting the second input voltage,
The control circuit is
The current sensing circuit according to any one of claims 1 to 5, which outputs a current detection signal corresponding to the voltage drop occurring in the sense resistor,
generating a signal for turning on and off the seventh transistor based on a comparison between an error signal corresponding to a difference between a voltage corresponding to the output voltage and a reference voltage and a slope signal corresponding to the current detection signal;
Must be a DC/DC converter.

According to the current sensing circuit and the DC/DC converter according to the present invention, it is possible to widen the common-mode input range while reducing the size of the circuit.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following detailed description of the invention (hereinafter referred to as "embodiment") with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing one embodiment of a DC/DC converter incorporating the current sense circuit of the present invention. FIG. 2 is a circuit diagram showing details of the current sensing circuit shown in FIG. FIG. 3 is a circuit diagram for explaining the operation of the current sensing circuit shown in FIG. 2 when the input voltage VIN is low. FIG. 4 is a circuit diagram for explaining the operation of the current sensing circuit shown in FIG. 2 when the input voltage VIN is high. FIG. 5 is a circuit diagram showing an example of a conventional current sensing circuit.

Specific embodiments relating to the present invention will be described below with reference to each drawing.

The current sense circuit 4 of the present invention is used in the DC/DC converter 1 shown in FIG. The DC/DC converter 1 steps down the input voltage V ₊ as the second DC input voltage by turning on and off the MOS transistor MP11 as the seventh transistor, and outputs the result as an output voltage Vout. The DC/DC converter 1 controls on/off of the MOS transistor MP11, the diode D, the coil Lout, the capacitor Cout, the voltage detection resistors R21 and R22, the current detection sense resistor Rs, and the MOS transistor MP11. and a control IC 2 as a control circuit.

The MOS transistor MP11 is composed of a P-channel field effect transistor. The MOS transistor MP11 has a source supplied with the input voltage V ₊ , a drain connected to the coil Lout and the cathode of the diode D, and a gate connected to the gate terminal GATE of the control IC2. The anode of diode D is connected to ground GND.

The coil Lout has one end connected to the drain of the MOS transistor MP11 and the other end connected to one end of the capacitor Cout via the sense resistor Rs. An output voltage Vout is output from one end of this capacitor Cout. Also, the capacitor Cout has the other end connected to the ground GND.

The voltage detection resistors R21 and R22 are connected in parallel to the capacitor Cout and connected in series with each other. The end of the voltage detection resistor R21 opposite to the connection point with the voltage detection resistor R22 is connected to one end of the capacitor Cout. The voltage detection resistor R22 is connected to the ground GND at the end opposite to the connection point with the voltage detection resistor R21. As a result, the detection voltage Vouts (=voltage corresponding to the output voltage Vout) obtained by dividing the output voltage Vout by the voltage detection resistors R21 and R22 is supplied to the feedback terminal FB of the control IC2.

A sense resistor Rs is connected between the coil Lout and the capacitor Cout. Both ends of the sense resistor Rs are connected to the input terminals INP and INN of the control IC2, respectively.

The control IC2 controls on/off of the MOS transistor MP11 so that the detected voltage Vouts becomes the reference voltage Vref. The control IC 2 includes an error detection circuit 3, a current sense circuit 4, an oscillator 5, an adder 6, a PWM comparator 7, a flip-flop 8, a MOS transistor MN11, a NOT circuit 9, and a driver 10. have.

The error detection circuit 3 receives the detection voltage Vouts at its inverting input and the reference voltage Vref at its non-inverting input, and outputs an error signal Verr which is the difference between the detection voltage Vouts and the reference voltage Vref. The current sense circuit 4 outputs a current detection signal Vis corresponding to the voltage drop Rs×Is (=current flowing through the sense resistor Rs) across the sense resistor Rs. The oscillator 5 outputs a clock signal CLOCK and a triangular wave Vramp synchronized with the clock signal CLOCK. The adder 6 outputs a slope signal Vslope obtained by adding the triangular wave Vramp and the current detection signal Vis. The PWM comparator 7 receives the error signal Verr at its inverting input and the slope signal Vslope at its non-inverting input, and outputs a comparison signal Vcomp obtained by comparing the error signal Verr and the slope signal Vslope.

The flip-flop 8 has a set terminal S to which the clock signal CLOCK is input, and a reset terminal R to which the comparison signal Vcomp is input. The output terminal Q of flip-flop 8 is connected to the input of NOT circuit 9 , and the output of NOT circuit 9 is input to driver 10 . The output of driver 10 is connected to the gate of MOS transistor MP11. On the other hand, the inverted output terminal QB of flip-flop 8 is connected to the gate of MOS transistor MN11. The MOS transistor MN11 is composed of an N-channel field effect transistor. The MOS transistor MN11 has a drain connected to the non-inverting input of the PWM comparator 7 and a source connected to the ground GND.

With the above configuration, when the clock signal CLOCK rises, the flip-flop 8 is set, the output terminal Q becomes H level, and the MOS transistor MP11 is turned on. After that, when Vslope>Verr, the comparison signal Vcomp is inverted, the flip-flop 8 is reset, the output terminal Q becomes L level, and the MOS transistor MP11 is turned off. Also, the inverted output terminal QB of the flip-flop 8 becomes H level, the MOS transistor MN11 is turned on, and the slope signal Vslope is reset to 0V.

Next, details of the current sensing circuit 4 described above will be described with reference to FIG. As shown in the figure, the current sense circuit 4 includes a current detection signal generation circuit 41 for outputting a current detection signal Vis corresponding to the voltage drop Rs×Is occurring in the sense resistor Rs, and a current detection signal generation circuit 41 and an input bias reduction circuit 43 for reducing the input bias current.

The current detection signal generation circuit 41 has transistors Q1 to Q3 as first to third transistors and resistors R1 to R3 as first to third resistors. The transistors Q1 to Q3 are composed of NPN type bipolar transistors. The transistor Q1 is connected between its collector and emitter between a power supply line to which the voltage V ₊ (second input voltage) is supplied and one end of the sense resistor Rs. More specifically, the transistor Q1 has a collector connected to the power supply line through the drain and source of the MOS transistor MP3, and an emitter connected to one end of the sense resistor Rs through the resistor R1 and the input terminal INP.

The transistor Q2 is connected between the collector and the emitter between the power supply line and the other end of the sense resistor Rs. More specifically, the transistor Q2 has a collector connected to the power supply line through the drain and source of the MOS transistor MP4, and an emitter connected to the other end of the sense resistor Rs through the resistor R2 and the input terminal INN.

The bases of the transistors Q1 and Q2 are connected to each other, and the base and collector of the transistor Q2 are connected. That is, the transistors Q1 and Q2 form a current mirror circuit. The resistor R1 is connected between one end of the sense resistor Rs and the emitter of the transistor Q1, and the resistor R2 is connected between the other end of the sense resistor Rs and the emitter of the transistor Q2. The resistors R1 and R2 have the same resistance value (R1=R2).

The transistor Q3 has a base connected to the collector of the transistor Q1 and the drain of the MOS transistor MP3, and an emitter connected to the emitter of the transistor Q2 and the resistor R2. The transistor Q3 has a collector connected to the power supply line via a resistor R3.

According to the above configuration, the emitter currents Ie1 and Ie2 of the transistors Q1 and Q2 are equal due to the function of the current mirror circuit composed of the transistors Q1 and Q2. When current Is does not flow through sense resistor Rs, equal emitter currents Ie1 and Ie2 flow through resistors R1 and R2, respectively, and the emitters of transistors Q1 and Q2 are at the same potential. On the other hand, when the current Is flows through the sense resistor Rs, a potential difference is generated between the emitters of the transistors Q1 and Q2 by the voltage drop Rs×Is across the sense resistor Rs. Therefore, the transistor Q3 flows an emitter current Ie3 given by the following equation (3) so that the emitters of the transistors Q1 and Q2 are equal.
Ie3=Is×Rs/R1 (3)

Therefore, a current detection signal Vis corresponding to the current Is is generated across the resistor R3 as shown in the following equation (4).
Vis=Is×Rs×R3/R1 (4)
As is clear from the equation (4), R3/R1 is the amplification factor (gain).

By the way, the base-emitter voltage V _BEQ1 of the transistor Q1 must be higher than the minimum operating voltage V _BEQ1MIN as shown in the following equation (5).
_VBEQ1 =(V ₊ -VIN)-( _VDSMP3 +VR1)> _VBEQ1MIN (5)
V _DSMP3 : Voltage between drain and source of MOS transistor MP3 VR1 : Voltage across resistor R1

Therefore, the common-mode input voltage of the input voltage VIN as the first input voltage input to the input terminal INP is expressed by the following equation (6). cannot handle.
VIN<V ₊ −(V _BEQ1MIN +V _DSMP3 +VR1) (6)

Therefore, in this embodiment, the common-mode input range expansion circuit 42 is provided. The common-mode input range expansion circuit 42 includes resistors R 4 and R 5 as fourth and fifth resistors and a current supply circuit 421 . The resistors R4 and R5 are connected in series between the connection point between the emitter of the transistor Q1 and the resistor R1 and the connection point between the emitter of the transistor Q2 and the resistor R2. Resistors R4 and R5 have the same resistance value.

The current supply circuit 421 compares _{the connection point voltage V1 of the resistors R4 and R5 with a predetermined voltage (V + -V2} ). As shown, from one end of the sense resistor Rs through the input terminal INP to the resistor R1, and from the other end of the sense resistor Rs through the input terminal INN to the resistor R2, the current flows toward the connection point of the resistors R4 and R5. A constant current M×I1/2 is applied. Here, M represents a mirror ratio set by a first current mirror circuit 424, which will be described later. Next, the configuration of this current supply circuit 421 will be described. The current supply circuit 421 includes a comparison circuit 422, a voltage generation circuit 423, a first current mirror circuit 424, a diode D1 and a resistor R6.

The comparison circuit 422 is a circuit that compares the connection point voltage V1 between the resistors R4 and R5 with a predetermined voltage (V ₊ -V2). The connection point voltage V1 is equal to the input voltage VIN and is a voltage corresponding to the input voltage VIN. The comparison circuit 422 includes MOS transistors MP5 and MP6 as fourth and fifth transistors, and a constant current source 422A as a first current source. The MOS transistors MP5 and MP6 are composed of P-channel field effect transistors.

The sources of MOS transistors MP5 and MP6 are connected to each other and to the other end of constant current source 422A. The drain of the MOS transistor MP5 is connected to the ground GND, and the drain of the MOS transistor MP6 is connected to the ground GND through the drain-source of the MOS transistor MN5, which will be described later. A connection point voltage V1 is supplied to the gate of the MOS transistor MP5. Although the drain of the MOS transistor MP5 is connected to the ground GND in this embodiment, it is not limited to this. For example, it may be connected to the ground GND via a resistor.

A predetermined voltage (V ₊ -V2) is supplied to the gate of the MOS transistor MP6 through a resistor R6. When the diode D1, which will be described later, is in a non-conducting state, the current flowing through the resistor R6 is zero. That is, a predetermined voltage (V ₊ -V2) is supplied to the gate of the MOS transistor MP6. When the diode D1, which will be described later, is in a conductive state, the gate of the MOS transistor MP6 is supplied with a voltage obtained by subtracting a voltage drop caused by a current flowing through the resistor R6 from a predetermined voltage (V ₊ -V2).

A constant current source 422A is a current source that supplies a constant current I1 to the MOS transistors MP5 and MP6. The constant current source 422A has one end connected to the power supply line and the other end connected to the sources of the MOS transistors MP5 and MP6.

With the above configuration, when the connection point voltage V1>predetermined voltage (V ₊ -V2), the constant current I1 flows through the MOS transistor MP6, and the current flowing through the MOS transistor MP5 becomes zero. On the other hand, when the connection point voltage V1<predetermined voltage (V ₊ -V2), the constant current I1 flows through the MOS transistor MP5, and the current flowing through the MOS transistor MP6 becomes zero.

The voltage generation circuit 423 is a circuit that generates a predetermined voltage (V ₊ -V2). It has transistors Q4 to Q6 as a plurality of sixth transistors and a constant current source 423A as a second current source. These transistors Q4 to Q6 are composed of NPN type bipolar transistors and are connected in series between a power supply line supplied with voltage V ₊ and a resistor R6 connected to the gate of MOS transistor MP6. The transistors Q4 to Q6 are diode-connected with their bases and collectors connected. Constant current source 423A is connected between transistors Q4-Q6 and ground GND. Constant current source 423A supplies constant current I2 to transistors Q4-Q6. When a constant current I2 is passed through the transistors Q4 to Q6, a voltage V2 is generated and a predetermined voltage (V ₊ -V2) is supplied to the gate of the MOS transistor MP6.

The voltage V2 is set as represented by the following equation (7). That is, the number of transistors Q4-Q6 is set.
V2>(V _BEQ1MIN +V _DSMP3 ) (7)

The first current mirror circuit 424 has MOS transistors MN4 and MN5. The MOS transistors MN4 and MN5 are composed of N-channel field effect transistors. The MOS transistors MN4 and MN5 have their gates connected to each other and their sources connected to the ground GND. The drain of MOS transistor MN4 is connected to the gate of MOS transistor MP5. The gate and drain of the MOS transistor MN5 are connected. The drain of MOS transistor MN5 is connected to the drain of MOS transistor MP6. The gate aspect ratio of the MOS transistors MN4 and MN5 is set to M:1. As a result, the mirror ratio of the first current mirror circuit becomes M.

With the above configuration, when the connection point voltage V1>predetermined voltage (V ₊ -V2) and the constant current I1 flows through the MOS transistor MP6, the constant current I1 is supplied to the MOS transistor MN5. A current (M×I1) corresponding to the constant current I1 flowing through the MOS transistor MN5 flows as the drain current of the MOS transistor MN4. As a result, as shown in FIG. 4, a path flowing from one end of the sense resistor Rs to the resistor R1 via the input terminal INP and a path flowing from the other end of the sense resistor Rs to the resistor R2 via the input terminal INN are connected to the resistors R4 and R5. A constant current M.times.I1/2 flows out toward the connection point of , and a constant current M.times.I1 flows from the connection point toward the MOS transistor MN4.

The diode D1 has a role of protecting the gate and source of the MOS transistor MP6 from being applied with excessive voltage, and has an anode connected to the gate of the MOS transistor MP6 and a cathode connected to the gate of the MOS transistor MP5. Specifically, when the input voltage VIN is low and the power supply line voltage V ₊ is high, a voltage higher than the source voltage of the MOS transistor MP6 may be applied to the gate of the MOS transistor MP6. Even in such a case, the diode D1 limits the gate of the MOS transistor MP6 to the voltage V1+VF, which is the sum of the forward voltage VF of the diode D1 and the voltage V1 at the connection point, so that the MOS transistor MP6 can be protected. becomes. Even when the diode is in a conductive state, the connection point voltage V1<predetermined voltage (V ₊ -V2), the constant current I1 flows through the MOS transistor MP5, and the current flowing through the MOS transistor MP6 is zero. Become.

The resistor R6 reduces the current flowing from the diode D1 to the connection point between the resistors R4 and R5 to an extremely small current value when the gate of the MOS transistor MP6 is limited to the voltage V1+VF described above and the diode D1 becomes conductive. resistance to limit. That is, resistor R6 is set to a large resistance value.

According to the common-mode input range expansion circuit 42 having the configuration described above, when the input voltage VIN is low, the connection point voltage V1<predetermined voltage (V ₊ -V2). In this case, as shown in FIG. 3, the constant current I1 flows through the MOS transistor MP5, and the currents flowing through the MOS transistors MP6, MN4, and MN5 become zero. Therefore, the currents flowing through the resistors R4 and R5 are also zero. Since the resistors R4 and R5 can be ignored, the circuit operates in the same manner as the conventional circuit, and the current detection signal Vis is expressed by the above equation (4).

On the other hand, when _the input voltage VIN increases, the voltage V2 _is set as shown in Equation (7) _. A predetermined voltage (V ₊ -V2) is obtained. In this case, as shown in FIG. 4, the constant current I1 flows through the MOS transistors MP6, MN4, and MN5, and the current flowing through the MOS transistor MP5 becomes zero. Therefore, a current of M.times.I1/2 flows through the resistors R1, R2, R4 and R5, lowering the emitter potentials of the transistors Q1 and Q2. As a result, the operating voltages of the transistors Q1 and Q2 are ensured, and the common-mode input voltage of the input voltage VIN can be input up to the voltage V ₊ . The currents flowing through the resistors R1 and R4 are equal to the currents flowing through the resistors R2 and R5. Therefore, since the difference Ie1-Ie2 between the emitter currents of the transistors Q1 and Q2 does not change, the current detection signal Vis remains unchanged as expressed by the above equation (4).

According to the current sensing circuit 4 described above, the common-mode input range expansion circuit 42 can widen the common-mode input range while reducing the circuit size.

Further, according to the current sensing circuit 4 described above, the common-mode input range expansion circuit 42 has the comparison circuit 422 including the MOS transistors MP5 and MP6 and the constant current source 422A, and the first current mirror circuit 424. ing. As a result, with a simple configuration, current M×I1/2 can flow through the resistors R4 and R5 when the connection point voltage V1>predetermined voltage (V ₊ -V2).

Further, according to the current sensing circuit 4 described above, the connection point voltage V1 is supplied to the gate of the MOS transistor MP5 as a voltage corresponding to the input voltage VIN. As a result, a voltage corresponding to the input voltage VIN can be supplied to the gate of the MOS transistor MP5 with a simple configuration.

Further, according to the current sense circuit 4 described above, the common-mode input range expansion circuit 42 has the voltage generation circuit 423 including the plurality of transistors Q4 to Q6 and the constant current source 423A. Thereby, the predetermined voltage (V ₊ -V2) can be generated with a simple configuration.

Next, the input bias reduction circuit 43 will be explained. The input bias reduction circuit 43 has a constant current source 431 as a third current source, a second current mirror circuit 432 and a third current mirror circuit 433 . A constant current source 431 is a constant current source connected between the drain of the MOS transistor MP1 and the ground GND to generate a constant current I3.

A second current mirror circuit 432 copies constant current I3 and supplies it to the collectors of transistors Q1 and Q2, respectively. The second current mirror circuit 432 has MOS transistors MP1, MP3 and MP4. MOS transistors MP1, MP3 and MP4 are of the same size. The MOS transistors MP1, MP3 and MP4 are composed of P-channel field effect transistors. The MOS transistor MP1 has a source connected to the power supply line supplied with the voltage V ₊ and a drain connected to the constant current source 431 . The drain and gate of the MOS transistor MP1 are connected.

The MOS transistor MP3 has a gate connected to the gate of the MOS transistor MP1, a source connected to the power line supplied with the voltage V ₊ , and a drain connected to the collector of the transistor Q1. The MOS transistor MP4 has a gate connected to the gate of the MOS transistor MP1, a source connected to the power line supplied with the voltage V ₊ , and a drain connected to the collector of the transistor Q2.

The third current mirror circuit 433 copies the constant current I3 by the MOS transistors MP2 and MN1, and flows the copied constant current I3 from the emitters of the transistors Q1 and Q2 toward the ground GND. The third current mirror circuit 433 has MOS transistors MP2, MN1, MN2 and MN3. The MOS transistor MP2 has the same size as the MOS transistor MP1. MOS transistors MN1, MN2 and MN3 are of the same size. The MOS transistor MP2 has a gate connected to the gate of the MOS transistor MP1, a source connected to the power line supplied with the voltage V ₊ , and a drain connected to the drain of the MOS transistor MN1. The MOS transistor MN1 has a drain connected to the drain of the MOS transistor MP2 and a source connected to the ground GND. Also, the gate and drain of the MOS transistor MN1 are connected.

The MOS transistor MN2 has a gate connected to the gate of the MOS transistor MN1, a drain connected to a connection point between the transistor Q1 and the resistor R1, and a source connected to the ground GND. The MOS transistor MN3 has a gate connected to the gates of the MOS transistors MN1 and MN2, a drain connected to a connection point between the transistor Q2 and the resistor R2, and a source connected to the ground GND.

According to the above configuration, the second current mirror circuit 432 supplies the constant current I3 to the collectors of the transistors Q1 and Q2. Also, the third current mirror circuit 433 copies the constant current I3 to the drains of the MOS transistors MN2 and MN3. When the drain currents of the MOS transistors MP3 and MP4 are equal to the drain currents of the MOS transistors MN3 and MN4, the currents flowing from the emitters of the transistors Q1 and Q2 all flow to the MOS transistors MN2 and MN3 and are output from the input terminals INP and INN. The applied input bias current can be zero.

According to the above-described embodiment, the input bias reduction circuit 43 can reduce the input bias current flowing through the input terminals INP and INN, and can reduce the increase in the output voltage Vout during no load.

According to the DC/DC converter 1 described above, the sense resistor Rs is provided between the coil Lout and the capacitor Cout. As a result, a loss occurs in the sense resistor Rs while the MOS transistor MP11 is on and off. becomes unnecessary, and the oscillation frequency of the oscillator 5 can be increased.

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary and not limited as long as the present invention can be achieved.

For example, according to the above-described embodiments, the input bias reduction circuit 43 is provided, but this is not the only option. The input bias reduction circuit 43 is not essential and may be omitted.

Further, according to the above-described embodiment, the voltage generation circuit 423 is composed of the plurality of transistors Q4 to Q6 and the constant current source 423A, but it is not limited to this. As the voltage generation circuit 423, for example, another well-known voltage generation circuit using a Zener diode or the like may be used.

1 DC/DC converter 2 Control IC (control circuit)
4 current sense circuit 41 current detection signal generation circuit 42 common-mode input range expansion circuit 43 input bias reduction circuit 421 current supply circuit 422 comparison circuit 422A constant current source (first current source)
424 first current mirror circuit 423 voltage generation circuit 423A constant current source (second current source)
431 constant current source (third current source)
432 second current mirror circuit 433 third current mirror circuit Lout coil Cout capacitor MP5 MOS transistor (fourth transistor)
MP6 MOS transistor (fifth transistor)
MP11 MOS transistor (seventh transistor)
Q1 transistor (first transistor)
Q2 transistor (second transistor)
Q3 transistor (third transistor)
Q4 to Q6 transistors (sixth transistors)
R1 resistor (first resistor)
R2 resistor (second resistor)
R3 resistor (third resistor)
R4 resistor (fourth resistor)
R5 resistor (fifth resistor)
Rs sense resistor VIN input voltage (first input voltage)
V1 node voltage V ₊ input voltage (second input voltage)
V ₊ -V2 Predetermined voltage

Claims (6)

A current sense circuit that outputs a current detection signal corresponding to a voltage drop occurring in a sense resistor,
a first transistor having a collector-emitter connected between a power supply line to which a second input voltage is supplied and one end of the sense resistor;
a second transistor having a collector-emitter connected between the power supply line and the other end of the sense resistor, a base connected to the base of the first transistor, and a base-collector connected;
a first resistor connected between one end of the sense resistor and an emitter of the first transistor;
a second resistor connected between the other end of the sense resistor and the emitter of the second transistor and having the same resistance value as the first resistor;
a third transistor having an emitter connected to the emitter of the second transistor and a base connected to the collector of the first transistor;
a current detection signal generating circuit having a third resistor connected between the power supply line and the collector of the third transistor;
Fourth resistors having the same resistance value are connected in series between a connection point between the emitter of the first transistor and the first resistor and a connection point between the emitter of the second transistor and the second resistor. a resistor and a fifth resistor;
A voltage corresponding to a first input voltage input to one end of the sense resistor is compared with a predetermined voltage, and if the voltage corresponding to the first input voltage is higher than the predetermined voltage, one end of the sense resistor and a common-mode input range expansion circuit including a current supply circuit for supplying a current from the other end of the sense resistor to a connection point between the fourth resistor and the fifth resistor. 2. The current sense circuit of claim 1, comprising:
The current supply circuit is
a fourth transistor and a fifth transistor having sources connected together; and a first current source supplying current to the fourth transistor and the fifth transistor, the gate of the fourth transistor. a comparator circuit supplied with a voltage corresponding to the first input voltage to the gate of the fifth transistor and the predetermined voltage supplied to the gate of the fifth transistor;
A current sense circuit, comprising: a first current mirror circuit that causes a current corresponding to a current flowing through the fifth transistor to flow out from a connection point between the fourth resistor and the fifth resistor. 3. The current sense circuit according to claim 1 or 2,
A voltage corresponding to the first input voltage is a connection point voltage of the fourth resistor and the fifth resistor. A current sense circuit. The current sensing circuit according to any one of claims 1 to 3,
The common-mode input range expansion circuit includes:
a plurality of sixth transistors diode-connected and connected in series with each other; and a second current source supplying current to the sixth transistors, wherein a voltage is generated across the plurality of sixth transistors. a current sense circuit, comprising a voltage generation circuit that generates the predetermined voltage according to the current sense circuit. The current sensing circuit according to any one of claims 1 to 4,
a third current source that supplies a constant current;
a second current mirror circuit that copies the current of the third current source and supplies it to the collectors of the first transistor and the second transistor, respectively;
a third current mirror circuit that copies the current of the third current source and passes the copied current from the emitters of the first transistor and the second transistor toward ground. A current sense circuit with a coil;
a capacitor to which one end of the coil is connected;
a seventh transistor provided between a voltage source to which a second input voltage is supplied and the other end of the coil for turning on and off supply of the second input voltage to the coil;
a sense resistor provided between one end of the coil and the capacitor;
A DC/DC converter comprising a control circuit for controlling on/off of the seventh transistor to output an output voltage obtained by converting the second input voltage,
The control circuit is
The current sensing circuit according to any one of claims 1 to 5, which outputs a current detection signal corresponding to the voltage drop occurring in the sense resistor,
generating a signal for turning on and off the seventh transistor based on a comparison between an error signal corresponding to a difference between a voltage corresponding to the output voltage and a reference voltage and a slope signal corresponding to the current detection signal;
DC/DC converter.

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