JP4007183B2 - Function generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a function generation circuit that generates a control signal that compensates for temperature dependence of an oscillation frequency output from a crystal oscillation device.
[0002]
[Prior art]
In recent years, the demand for portable electronic devices has increased dramatically, and a small and highly accurate crystal oscillation device for generating a reference clock signal is essential for the electronic devices.
[0003]
The oscillation frequency of the crystal oscillator in the crystal oscillation device has temperature characteristics having third-order and first-order components caused by the crystal resonator used in the crystal oscillator.
[0004]
As a method for compensating for this temperature characteristic, for example, a varactor diode (= variable capacitance diode) that is a frequency adjusting element is connected to a crystal oscillator, and the third and first order compensates the temperature characteristic of the crystal oscillator to the varactor diode. There is a method of stabilizing the temperature characteristics of the oscillation frequency by applying a control voltage having temperature characteristics.
[0005]
However, it is technically difficult to generate the control voltage Vc having an ideal temperature characteristic, and in general, a control voltage having a pseudo third-order temperature characteristic is generated by various methods.
[0006]
A function generating circuit for generating a control voltage having a third-order temperature characteristic will be described below with reference to the drawings.
[0007]
FIG. 5 shows a configuration of a conventional function generating circuit, wherein 1 is a MAX circuit that outputs an electric signal having the maximum voltage value among input electric signals, and 2 is a minimum voltage value among input electric signals. MIN circuit for outputting electrical signals, Vcc is a power supply voltage, Q1 is a first NPN transistor, Q2 is a second NPN transistor, Q3 is a third NPN transistor, Q7 is a fourth NPN transistor, and Q6 is a first NPN transistor PNP transistor, Q4 is the second PNP transistor, Q5 is the third PNP transistor, Q8 is the fourth PNP transistor, I1 is the thirteenth current source, and I2 is half of the thirteenth current source I1. A fourteenth current source having a current value, I3 is a fifteenth current source, I4 is a sixteenth current source having a current value half that of the fifteenth current source I3, and y1 is proportional to the ambient temperature. Decrease A second electric signal y2 is a tenth electric signal that maintains a predetermined value without depending on the ambient temperature, y3 is an eleventh electric signal that increases in proportion to the ambient temperature, and y4 depends on the ambient temperature. 12 is a twelfth electric signal that holds a predetermined value, y5 is a thirteenth electric signal that decreases in proportion to the ambient temperature, y6 is a ninth electric signal y1, a tenth electric signal y2, and an eleventh electric signal. The fourteenth electric signal output by selecting the electric signal having the maximum voltage value among y3 and y7 is the minimum voltage value among the twelfth electric signal y4, the thirteenth electric signal y5 and the fourteenth electric signal y6. This is a fifteenth electric signal selected and output from the electric signal. The fifteenth electric signal y7 becomes the control voltage Vc for temperature compensation.
[0008]
The MAX circuit 1 includes a first NPN transistor Q1 to which the power supply voltage Vcc is applied to the collector, the ninth electric signal y1 is applied to the base, and the emitter is connected to the input side of the thirteenth constant current source I1. The power supply voltage Vcc is applied to the collector, the tenth electric signal y2 is applied to the base, the emitter is connected to the input side of the thirteenth constant current source I1, and the power supply voltage Vcc is applied to the collector. Is applied, the eleventh electric signal y3 is applied to the base, the third NPN transistor Q3 having the emitter connected to the input side of the thirteenth constant current source I1, the collector and the base are connected to the fourteenth constant current source I1. The emitter is connected to the output side of the current source I2, the emitter is connected to the input side of the thirteenth constant current source I1, and the ninth electric signal y1, the tenth electric signal y2, and the eleventh electric current are connected to the collector. And a fourth NPN transistor Q7 and outputting a fourteenth electrical signal y6 selects the maximum voltage value of the signal y3.
[0009]
The MIN circuit 2 includes a first PNP transistor Q6 having a base connected to the collector of the fourth NPN transistor Q7, an emitter connected to the output side of the fifteenth constant current source I3, and a collector grounded. The twelfth electric signal y4 is applied, the emitter is connected to the output side of the fifteenth constant current source I3, the collector is grounded, and the thirteenth electric signal y5 is applied to the base. The emitter is connected to the output side of the fifteenth constant current source I3, the collector is grounded, the third PNP transistor Q5, the emitter is connected to the output side of the fifteenth constant current source I3, and the collector and base Is connected to the input side of the sixteenth constant current source I4, and the collector has the minimum voltage value among the twelfth electric signal y4, the thirteenth electric signal y5 and the fourteenth electric signal y6. And a fourth PNP transistor Q8 and outputting as an electric signal y7 of the 15 selected.
[0010]
The operation of the MAX circuit 1 and the MIN circuit 2 configured as described above will be described.
[0011]
In the MAX circuit 1, the first NPN transistor Q1, the second NPN transistor Q2, and the third NPN transistor Q3 share the collector and the emitter with each other, and the fourteenth constant current source I2 is the fourth NPN. Since the current flows through the transistor Q7 to the thirteenth constant current source I1 and the current value I2 is set to I1 / 2, the remaining current value I1 / 2 of the current value I1 is the first NPN transistor Q1, Of the second NPN transistor Q2 and the third NPN transistor Q3, the current flows to the transistor whose maximum voltage value is applied to the base. As a result, the potential difference between the base and the emitter of the fourth NPN transistor Q7 and the maximum voltage value is applied to the base among the first NPN transistor Q1, the second NPN transistor Q2, and the third NPN transistor Q3. Since the potential difference between the base and the emitter of the transistor becomes equal, the voltage value common to the collector and base of the fourth NPN transistor Q7 is the ninth electric signal y1, the tenth electric signal y2, and the eleventh electric signal. It becomes equal to the maximum voltage value of the electric signal y3.
[0012]
Further, in the MIN circuit 2, the first PNP transistor Q6, the second PNP transistor Q4, and the third PNP transistor Q5 have the emitters shared with each other and the collectors are all grounded, so that the fourth PNP transistor Q8 The common voltage of the collector and base of the first PNP transistor Q6, the base voltage value of the second PNP transistor Q4, and the base voltage value of the third PNP transistor Q5 are equal to the minimum voltage value.
[0013]
Thus, according to the function generation circuit that generates the control voltage Vc of the third-order temperature characteristic, the fifteenth electric signal y7 as the control voltage Vc is output as a group of five control voltages that change in a continuous linear shape. Thus, a polygonal line approximation of the temperature compensation characteristic can be performed (for example, see Patent Document 1).
[0014]
[Patent Document 1]
JP-A-11-803195
[0015]
[Problems to be solved by the invention]
However, in order to generate the fifteenth electric signal y7 as the final output, the conventional function generating circuit has a ninth electric signal y1, a tenth electric signal y2, an eleventh electric signal y3, and a twelfth electric signal. Electrical signal y4 and thirteenth electrical signal y5 are required, and variations in their characteristics become variations in the final output 15th electrical signal y7. The problem is that it is difficult to keep the design within a certain range.
[0016]
Further, the MAX circuit 1 selects the electric signal having the maximum voltage value from the ninth electric signal y1, the tenth electric signal y2, and the eleventh electric signal y3, and outputs it as the fourteenth electric signal y6. The minimum value that can be taken as the maximum value of the selected electrical signal is the base of the transistor having the maximum voltage value applied to the base among the first NPN transistor Q1, the second NPN transistor Q2, and the third NPN transistor Q3. Must be equal to or greater than the voltage value obtained by adding the minimum potential difference between the input and output of the thirteenth current source I1 at which the thirteenth current source I1 can operate.
[0017]
Select to select the electric signal having the minimum voltage value among the twelfth electric signal y4, the thirteenth electric signal y5, and the fourteenth electric signal y6 in the MIN circuit 2 and output as the fifteenth electric signal y7. The maximum value that can be taken as the minimum value of the electrical signal is the emitter and base of the first PNP transistor Q6, the second PNP transistor Q4, and the third PNP transistor Q5 that have the minimum voltage applied to the base. The voltage value obtained by adding the minimum potential difference between the input and output of the fifteenth current source I3 that can operate the fifteenth current source I3 to the potential difference between and the power supply voltage Vcc must be equal to or less than the voltage value.
[0018]
Thus, the potential difference between the average base and emitter when the NPN transistor is operating in a non-saturation state is 0.7 V, and the average emitter when the PNP transistor is operating in a non-saturation state Assuming that the potential difference from the base is 0.7 V and the minimum value of the average potential difference between the input and output of the current source that can operate the current source is 0.2 V, the voltage operation range of the control voltage Vc is zero. .9V, the maximum value is Vcc-0.9V, and the operation is within a range obtained by subtracting 1.8V from the power supply voltage Vcc.
[0019]
Therefore, when 0.4 V is required in the voltage operation range of the control voltage Vc, the power supply voltage Vcc needs to be 2.2 V or more, and the power supply voltage Vcc is operated at a low voltage of 2.0 V or less. Have the problem of not being able to.
[0020]
The present invention reduces the components of the approximate tertiary temperature characteristic voltage and reduces the variation factor of the approximate tertiary temperature characteristic voltage. At the same time, the control voltage Vc is continuously applied even when the power supply voltage Vcc is a low voltage of 2.0 V or less. It is an object of the present invention to perform the approximation of the polygonal line of the temperature compensation characteristic by reducing the variation factor and performing the low voltage operation by synthesizing and converting the currents to the three control current groups changing linearly.
[0021]
[Means for Solving the Problems]
To achieve this object, the function generating circuit of claim 1 of the present invention uses a first current that increases in proportion to the ambient temperature as a reference current for differential amplification, and a first current is supplied to one input thereof. A first electrical signal proportional to the first electrical signal is input to the other input, and a second electrical signal proportional to a second current that decreases in proportion to the ambient temperature is input to the other input. And a PchMOS transistor in which a second electric current is used as a reference current for differential amplification, a first electric signal is input to one input, and a second electric signal is input to the other. The configured second differential current comparator, the drain of the PchMOS transistor to which the second electrical signal of the first differential current comparator is input, and the second differential current comparator Is connected to the drain of the PchMOS transistor, and a fourth current having a current value equivalent to the third current flowing through the common node is used as a reference current for differential amplification. A third differential signal composed of a PchMOS transistor to which a second electrical signal is input and a third electrical signal proportional to a fifth current that increases in proportion to the ambient temperature is input to the other input. It is composed of a current comparator and a PchMOS transistor in which a fifth electric current is used as a reference current for differential amplification, a second electric signal is input to one input, and a third electric signal is input to the other. The fourth differential current comparator, the drain of the PchMOS transistor to which the second electrical signal of the third differential current comparator is input, and the fourth differential A drain of the PchMOS transistor to which the third electric signal of the current comparator is input is connected, and a first current-voltage conversion circuit for converting a sixth current flowing through the common node into a current-voltage is provided; And the current having the maximum current value selected from the first current and the second current flows and the sixth current is the minimum of the fourth current and the fifth current. A current having a voltage value is selected and flows, and the first current-voltage conversion circuit converts the sixth current into a voltage and outputs it as a fourth electric signal.
[0022]
With the above-described configuration, the fourth electric signal output as the approximate third-order temperature characteristic voltage Vc has three controls that change in three continuous straight lines of the first current, the second current, and the fifth current. First, the current having the maximum current value is selected from the first current and the second current to create the third current and the fourth current, and then the fourth current and the fifth current are selected. Since a current having the minimum current value is selected and synthesized as a sixth current, and the sixth current is converted into a voltage by the first current-voltage conversion circuit, the approximate third-order temperature characteristic voltage The characteristic variation factor is only the variation of the three components of the first current, the second current, and the fifth current, and the conventional function generation circuit converts the approximate tertiary temperature characteristic voltage Vc into five control voltage groups. As a result of synthesizing the product, there are five components Compared to that a variation, it is possible to reduce variation factors of about 40%.
[0023]
In addition, with the above configuration, the approximation accuracy of the fourth electric signal output as the approximate third-order temperature characteristic voltage Vc changes in three continuous straight lines of the first current, the second current, and the fifth current. Even when the control current group is made up of three control current groups, the first current and the second current are selectively combined to produce the third current and the fourth current, and the fourth current and the fifth current. Adjusting the rounding characteristic of the selective synthesis portion when the sixth current is selectively synthesized by adjusting the characteristics of the first electric signal, the second electric signal, and the third electric signal with respect to the temperature. Since it can be adjusted by changing the selectivity of the differential current comparator, the second differential current comparator, the third differential current comparator, and the fourth differential current comparator, the five control voltage groups are synthesized. A conventional function generating circuit for producing an approximate third-order temperature characteristic voltage Vc It is possible to accuracy.
[0024]
Next, when the current having the maximum current value is selected from the first current and the second current to generate the third current by the above configuration, the minimum voltage value of the power supply voltage Vcc at which this circuit operates is The minimum potential difference between the input and output of the current source that supplies the first current that can operate the current source that supplies the first current and the gate and the source of the PchMOS transistor that constitutes the first differential current comparator Or a second current that can operate the current source that supplies the second current is greater than or equal to a voltage value obtained by adding the voltage value at which the first electric signal and the second electric signal have the same potential. The minimum potential difference between the input and output of the current source, the potential difference between the gate and source of the PchMOS transistor constituting the second differential current comparator, and the voltage value at which the first and second electrical signals have the same potential. More than the voltage value plus A. Here, the minimum value of the potential difference between the average current input and output at which the current source can operate is 0.2 V, and the average between the gate and the source where the PchMOS transistor can pass the current between the source and the drain Assuming that the threshold voltage is 0.8 V and the voltage value at which the first electric signal and the second electric signal are at the same potential is 0.4 V, the minimum value of the power supply voltage Vcc at which this circuit can operate is 1. 4V.
[0025]
Further, when the sixth current is generated by selectively combining the fourth current and the fifth current, the minimum voltage value of the power supply voltage Vcc at which this circuit operates is determined by the current source that supplies the fourth current. The minimum potential difference between the input and output of the current source that supplies the fourth current that can be generated, the potential difference between the gate and the source of the PchMOS transistor constituting the third differential current comparator, the second electrical signal, and the third More than the voltage value obtained by adding the voltage value at which the electric signal becomes the same potential, or the minimum potential difference between the input and output of the current source that supplies the fifth current that can operate the current source that supplies the fifth current and the fourth The voltage difference between the gate and source of the PchMOS transistor constituting the differential current comparator is equal to or greater than the voltage value obtained by adding the voltage value at which the second electric signal and the third electric signal have the same potential. Here, the minimum value of the potential difference between the average current input and output at which the current source can operate is 0.2 V, and the average between the gate and the source where the PchMOS transistor can pass the current between the source and the drain Assuming that the threshold voltage is 0.8 V and the voltage value at which the second electric signal and the third electric signal have the same potential is 0.8 V, the minimum value of the power supply voltage Vcc at which this circuit can operate is 1. 8V.
[0026]
Accordingly, in the function generation circuit according to claim 1 of the present invention, the minimum value of the power supply voltage Vcc is regulated by the voltage value at which the second electric signal and the third electric signal have the same potential, It has no relation to the current values of the three control current groups that change in the form of three continuous straight lines of the first current, the second current, and the fifth current, which are components of the approximate tertiary temperature characteristic voltage Vc. Since the first electric signal, the second electric signal, and the third electric signal can be designed arbitrarily to some extent, the function generation circuit of the present invention can reduce the power supply voltage Vcc to a low voltage of 2.0 V or less. It can be operated.
[0027]
The function generating circuit according to claim 2 of the present invention uses the seventh current that decreases in proportion to the ambient temperature as a reference current for differential amplification, and increases in proportion to the seventh current at one of its inputs. A fifth electrical signal is input, and a fifth electrical signal is formed of an NchMOS transistor in which a sixth electrical signal that decreases in proportion to an eighth current that increases in proportion to the ambient temperature is input to the other input. And an NchMOS transistor in which an eighth current is used as a reference current for differential amplification, a fifth electrical signal is input to one input, and a sixth electrical signal is input to the other. The constructed sixth differential current comparator, the drain of the NchMOS transistor to which the sixth electrical signal of the fifth differential current comparator is inputted, and the fifth differential current comparator of the fifth differential current comparator A drain of an NchMOS transistor to which an air signal is input is connected, a tenth current having a current value equivalent to a ninth current flowing through the common node is set as a differential amplification reference current, and the first input is connected to the first input. The seventh electric signal is inputted to the other input, and the seventh electric signal which is increased in proportion to the eleventh electric current which decreases in proportion to the ambient temperature is inputted to the other input. A differential current comparator and an NchMOS transistor in which an eleventh current is used as a reference current for differential amplification, a sixth electric signal is input to one input thereof, and a seventh electric signal is input to the other input. And the drain of the NchMOS transistor to which the sixth electric signal of the seventh differential current comparator is input, A first current-voltage conversion circuit for connecting a drain of an NchMOS transistor to which a seventh electrical signal of the differential current comparator of 8 is input and converting a twelfth current flowing in the common node into a current voltage; The ninth current and the tenth current are selected from the seventh current and the eighth current, and the current having the maximum current value is selected and flows. The twelfth current is the sixth electric signal and the seventh current. When the value of the sixth electric signal is large, the tenth current is selected. When the value of the seventh electric signal is large, the eleventh current is selected. In the first current-voltage conversion circuit, the twelfth current is converted into a voltage and output as an eighth electric signal, but the polarity of the characteristics of each current and voltage is reversed. Except for the above, the same characteristics and characteristics as those of the function generation circuit of claim 1 of the present invention Has an effect.
[0028]
A function generation circuit according to claim 3 of the present invention is the function generation circuit according to claim 1 of the present invention, wherein the first differential current comparator, the second differential current comparator, the third differential current comparator, The fourth differential current comparator is configured with a PNP transistor. In the element for calculating the minimum voltage value of the power supply voltage Vcc, the PchMOS transistor allows a current to flow between the source and the drain. Except that the average gate-source threshold voltage of 0.8V can be changed to an average base-emitter potential difference of 0.7V when the PNP transistor is operating in a non-saturated state. The function generating circuit according to the first aspect of the present invention has the same characteristics and effects.
[0029]
According to a fourth aspect of the present invention, there is provided a function generating circuit according to the second aspect of the present invention, wherein the fifth differential current comparator, the sixth differential current comparator, the seventh differential current comparator, The eighth differential current comparator is configured by an NPN transistor, except that the polarity of the characteristics of each current and voltage is reversed. Has similar characteristics and effects.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings.
[0031]
FIG. 1 shows in detail the configuration of a function generation circuit according to an embodiment of the present invention. 3 is a MAX circuit that selects and outputs the current having the maximum current value among the input currents, 4 is a MIN circuit that selects and outputs the current having the minimum current value among the input currents, and 5 is a circuit of the MAX circuit 3. A first differential current comparator, which is a component, 6 is a second differential current comparator, which is a component of the MAX circuit 3, 7 is a third differential current comparator, which is a component of the MIN circuit 4, and 8 is A fourth differential current comparator, which is a component of the MIN circuit 4, is a first current mirror circuit that outputs the output current of the MAX circuit 3 in an equivalent manner, and 10 is an output current of the first current mirror circuit 9. Is a second current mirror circuit that folds and outputs the current equivalently, 11 is a current-voltage conversion circuit that inverts and amplifies the output current of the MIN circuit 4 and converts it into a voltage, Vcc is the power supply voltage, Vref is the reference Voltage, M1 is a first PchMOS transistor, M2 is a second PchMOS transistor, M3 is a third PchMOS transistor, M4 is a fourth PchMOS transistor, M5 is a fifth PchMOS transistor, M6 is a sixth PchMOS transistor, M7 is a seventh PchMOS transistor, M8 is an eighth PchMOS transistor, Q9 is a fifth NPN transistor, Q10 is a sixth NPN transistor, Q11 is a fifth PNP transistor, Q12 is a sixth PNP transistor, and R1 is The first resistor, R2 is a second resistor having a resistance value equivalent to the first resistor R1, R3 is a third resistor having a resistance value equivalent to the first resistor R1, and R4 is a fourth resistor, Amp1 is a first operational amplifier, IT1 is a first current that increases in proportion to the ambient temperature, IT2 The second current that decreases in proportion to the ambient temperature, IT3 is the third current that is the output current of the MAX circuit 3, IT4 is the output current of the second current mirror circuit 10, and is equivalent to the third current IT3 A fourth current having a current value, IT5 is a fifth current that increases in proportion to the ambient temperature, IT6 is a sixth current that is an output current of the MIN circuit 4, and IT101 is a first current that is proportional to the first current IT1. 17, IT201 is the 18th current proportional to the current ratio of the first current IT1 and the 17th current IT101 to the second current IT2, and IT501 is the first current IT1 to the fifth current IT5. A nineteenth current that is proportionally proportional to the current ratio of the seventeenth current IT101, V1 is an electric signal obtained by converting the seventeenth current IT101 into a current voltage by the first resistor R1, and is proportional to the first current IT1. 1 electrical signal , V2 is an electric signal obtained by current-voltage conversion of the eighteenth current IT201 by the second resistor R2, and is a second electric signal proportional to the second current IT2. V3 is the nineteenth current IT501 by the third resistor. A third electric signal that is current-voltage converted by R3 and proportional to the fifth current IT5, and Vc1 is a fourth electric signal that is the output of the current-voltage conversion circuit 11. The fourth electric signal Vc1 is a control voltage Vc having an approximate third-order temperature characteristic for temperature compensation.
[0032]
In the MAX circuit 3, the second electric signal V2 is applied to the gate, the first PchMOS transistor M1 whose source is connected to the output side of the first current IT1, and the first electric signal V1 to the gate. The first electrical signal V1 is applied to the first differential current comparator 5 and the gate, which is composed of the second PchMOS transistor M2 whose source is connected to the output side of the first current IT1, and whose drain is grounded, The second electric signal V2 is applied to the third PchMOS transistor M3 whose source is connected to the output side of the second current IT2 and the gate, the source is connected to the output side of the second current IT2, and the drain is grounded And a second differential current comparator 6 composed of the fourth PchMOS transistor M4, which receives the first current IT1 and the second current IT2. The first electric signal V1 and the second electric signal V2 are set as current comparison control voltages, the drain of the first PchMOS transistor M1 and the drain of the third PchMOS transistor M3 are connected, and the common node Is output as a third current IT3.
[0033]
In the MIN circuit 4, the second electrical signal V2 is applied to the gate, the fifth PchMOS transistor M5 to which the fourth current IT4 is applied to the source, the third electrical signal V3 is applied to the gate, and the source is the first. The third electric signal V3 is applied to the third differential current comparator 7 and the gate connected to the output side of the fourth current IT4 and the drain is grounded, and the source is the first. The second electric signal V2 is applied to the seventh PchMOS transistor M7 connected to the output side of the fifth current IT5 and the gate, the source is connected to the output side of the fifth current IT5, and the drain is grounded. And a fourth differential current comparator 8 composed of eight PchMOS transistors M8, with the fourth current IT4 and the fifth current IT5 as input currents. The second electric signal V2 and the third electric signal V3 are used as a current comparison control voltage, and the drain of the fifth PchMOS transistor M5 and the drain of the seventh PchMOS transistor M7 are connected, and the current flows to the common node. Is output as the sixth current IT6.
[0034]
In the first current mirror circuit 9, the emitter is grounded, the collector and base are connected, the fifth NPN transistor Q9 to which the third current IT3 is applied, the emitter is grounded, and the base is the fifth NPN transistor Q9. The sixth NPN transistor Q10 is connected to the collector and the base, and the collector is connected to the input of the second current mirror circuit 10. The third current IT3 is used as the input current, and the sixth NPN transistor Q10 A current equivalent to the third current IT3 is folded and output to the collector. Note that the same characteristics and effects can be obtained by replacing the fifth NPN transistor Q9 and the sixth NPN transistor Q10 with NchMOS transistors.
[0035]
The second current mirror circuit 10 has an emitter connected to the power supply Vcc, a collector connected to the base, a fifth PNP transistor Q11 to which the output current of the first current mirror circuit 9 is applied, and an emitter connected to the power supply Vcc. The base is connected to the collector of the fifth PNP transistor Q11 and the base, and the collector is configured by the sixth PNP transistor Q12 connected to the input of the MIN circuit 4, and the output of the first current mirror circuit 9 Using the current as an input current, a current equivalent to the output current of the first current mirror circuit 9 is turned back to the collector of the sixth PNP transistor Q12 and output as a fourth current IT4. Here, since the output current of the first current mirror circuit 9 is equivalent to the third current IT3, the fourth current IT4 is also equivalent to the third current IT3. It should be noted that the same characteristics and effects can be obtained by replacing the fifth PNP transistor Q11 and the sixth PNP transistor Q12 with PchMOS transistors.
[0036]
In the current-voltage conversion circuit 11, the reference voltage Vref is applied to the positive input, the anode of the fourth resistor R4 is connected to the negative input, the sixth current IT6 is applied, and the cathode of the fourth resistor R4 is connected to the output. The first operational amplifier Amp1 is configured to output the sixth current IT6 as an input current and the electric signal output to the first operational amplifier Amp1 as the fourth electric signal Vc1.
[0037]
The operations of the MAX circuit 3, the MIN circuit 4, the first current mirror circuit 9, the second current mirror circuit 10, and the current-voltage conversion circuit 11 configured as described above will be described.
[0038]
The first differential current comparator 5 in the MAX circuit 3 is configured so that the first PchMOS transistor M1 and the second PchMOS transistor M2 have a differential amplification configuration. When the first electric signal V1 is large, the first current IT1 is output to the drain of the first PchMOS transistor M1, and the second node is shared with the drain of the third PchMOS transistor M3. When the second electric signal V2 is large, the first current IT1 is output to the drain of the second PchMOS transistor M2, and the first current IT1 is supplied to the ground. Next, in the second differential current comparator 6, since the third PchMOS transistor M3 and the fourth PchMOS transistor M4 have a differential amplification configuration, the first electric signal V1 and the second electric current comparator 6 are connected to each other. When the signal V2 is compared, and the first electric signal V1 is large, the second current IT2 is output to the drain of the fourth PchMOS transistor M4, the second current IT2 is supplied to the ground, and the second electric signal V2 Is large, the second current IT2 is output to the drain of the third PchMOS transistor M3, and the second current IT2 is supplied to the node common with the drain of the first PchMOS transistor M1.
[0039]
6A shows the first current IT1, the second current IT2, the fifth current IT5, the seventeenth current IT101, the eighteenth current IT201, and the nineteenth current IT501 with respect to the temperature. FIG. 6B is a diagram illustrating the characteristics, and FIG. 6B is a diagram illustrating the characteristics with respect to the temperature for each of the first electric signal V1, the second electric signal V2, and the third electric signal V3. The first electric signal V1 and the second electric signal V2 can be expressed by the following equations (1) and (2), respectively.
[0040]
V1 = IT101 × R1 (1)
V2 = IT201 × R2 (2)
In the equations (1) and (2), the seventeenth current IT101 is proportional to the first current IT1, and the eighteenth current IT201 is the second current IT2 and the seventeenth current IT101 and the first current. Since the first resistor R1 and the second resistor R2 are equally proportional to the current ratio of IT1, the first electric signal V1 is proportional to the first current IT1 and the second electric signal. V2 is proportional to the ratio of the first electric signal V1 and the first current IT1 to the second current IT2. Therefore, as shown in FIGS. 6A and 6B, the magnitude relationship of the first current IT1 and the second current IT2 with respect to the temperature, and the temperature T1 at which the first current IT1 and the second current IT2 have the same value. The first electric signal V1 and the second electric signal V2 have the same magnitude relationship with respect to the temperature, and the temperature T1 at which the first electric signal V1 and the second electric signal V2 have the same value.
[0041]
As a result, the current having the maximum current value among the first current IT1 and the second current IT2 is selected as the current output of the MAX circuit 3 and is output as the third current IT3. The characteristics are as shown in FIG. In FIG. 6 (c), the third current IT3 is not connected in a polygonal line near the temperature T1 where the first current IT1 and the second current IT2 have the same value. This is due to the rounding effect of current selectivity due to the differential characteristics of the fifth and second differential current comparators 6. Note that this rounding effect is achieved by adjusting the change ratio of the first electric signal V1 with respect to the temperature and the change ratio of the second electric signal V2 with respect to the temperature. And by adjusting the current selectivity of the differential characteristic of the second differential current comparator 6, it can be arbitrarily adjusted.
[0042]
The first current mirror circuit 9 and the second current mirror circuit 10 fold back and output a current equivalent to the third current IT3, and apply the fourth current IT4 to the input of the MIN circuit 4.
[0043]
The third differential current comparator 7 in the MIN circuit 4 has a fifth PchMOS transistor M5 and a sixth PchMOS transistor M6 configured to perform differential amplification. When the second electric signal V2 is small, the fourth current IT4 is output to the drain of the fifth PchMOS transistor M5, and the drain of the seventh PchMOS transistor M7 is connected to the common node. When the third electric signal V3 is small, the fourth current IT4 is output to the drain of the sixth PchMOS transistor M6 and the fourth current IT4 is supplied to the ground. Next, in the fourth differential current comparator 8, since the seventh Pch MOS transistor M7 and the eighth Pch MOS transistor M8 have a differential amplification configuration, the second electric signal V2 and the third electric current comparator 8 are the same. When the second electric signal V2 is small, the fifth current IT5 is output to the drain of the eighth PchMOS transistor M8, the fifth current IT5 is supplied to the ground, and the third electric signal V3 is compared. Is small, the fifth current IT5 is output to the drain of the seventh PchMOS transistor M7, and the fifth current IT5 is supplied to the node common with the drain of the fifth PchMOS transistor M5.
[0044]
Here, the third electric signal V3 can be expressed by the following equation (3).
[0045]
V3 = IT501 × R3 (3)
In the expression (3), the nineteenth current IT501 is equivalent to the fifth current IT5 in proportion to the current ratio between the eighteenth current IT201 and the second current IT2, and the third resistor R3 and the second resistor Since R2 has the same resistance value, the third electrical signal V3 is equivalently proportional to the ratio of the second electrical signal V2 and the second current IT2 to the fifth current IT5. Therefore, as shown in FIGS. 6A and 6B, the magnitude relationship of the second current IT2 and the fifth current IT5 with respect to the temperature, and the temperature T2 at which the second current IT2 and the fifth current IT5 have the same value. The second electric signal V2 and the third electric signal V3 have the same magnitude relationship with respect to the temperature and the temperature T2 at which the second electric signal V2 and the third electric signal V3 have the same value. Furthermore, as shown in FIG. 6C, the fourth current IT4 is equivalent to the second current IT2 in the vicinity of the temperature T2, so that the fourth current IT4 and the fifth current IT5 are large or small with respect to the temperature. And the relationship between the temperature T2, the second electric signal V2, and the third electric signal V3 at which the fourth current IT4 and the fifth current IT5 have the same value, and the second electric signal V2 and the third electric signal V3. The temperature T2 at which the electric signal V3 becomes the same value is the same.
[0046]
As a result, the current having the minimum current value among the fourth current IT4 and the fifth current IT5 is selected as the current output of the MIN circuit 4 and is output as the sixth current IT6. The characteristics are as shown in FIG. In FIG. 6 (d), the sixth current IT6 is not connected in a polygonal line near the temperature T2 at which the fourth current IT4 and the fifth current IT5 have the same value. This is due to the rounding effect of current selectivity due to the differential characteristics of the seventh and fourth differential current comparators 8. This rounding effect is achieved by adjusting the change ratio of the second electric signal V2 with respect to the temperature and the change ratio of the third electric signal V3 with respect to the temperature, and the current selectivity based on the differential characteristics of the third differential current comparator 7. And by adjusting the current selectivity of the differential characteristic of the fourth differential current comparator 8, it can be arbitrarily adjusted.
[0047]
Thus far, the temperature characteristics of the first current IT1, the second current IT2, the fifth current IT5, the first electric signal V1, the second electric signal V2, and the third electric signal V3 are adjusted. Thus, the sixth current IT6 can be output as a current that changes with an approximate third-order characteristic with respect to the temperature as shown in FIG.
[0048]
The current-voltage conversion circuit 11 is a typical inverting amplification current-voltage conversion amplifier with the above configuration. The conversion gain is determined by the fourth resistor R4, and the sixth current IT6 applied to the negative input of the first operational amplifier Amp1 is converted into a voltage by the relationship of the following expression (4), and the fourth electric current is calculated. Output as signal Vc1.
[0049]
Vc1 = −R4 × IT6 + Vref (4)
FIG. 6E shows the temperature characteristic of the fourth electric signal Vc1, which is an approximate third-order temperature characteristic that is the inverse of the temperature characteristic of the sixth current IT6. The fourth electric signal Vc1 is used as a control voltage Vc having an approximate tertiary temperature characteristic for temperature compensation.
[0050]
As described above, according to the present embodiment, the fourth electric signal Vc1 output as the approximate third-order temperature characteristic voltage Vc includes the three currents of the first current IT1, the second current IT2, and the fifth current IT5. Of the three control current groups changing in a straight line, first, the current having the maximum current value is selected from the first current IT1 and the second current IT2, and the third current IT3 and the fourth current IT4 are selected. Is synthesized as a sixth current IT6 produced by selecting the current having the minimum current value from the fourth current IT4 and the fifth current IT5, and this sixth current IT6 is synthesized as a current-voltage conversion circuit. 11, the characteristic variation factor of the approximate third-order temperature characteristic voltage is only the variation of the three components of the first current IT1, the second current IT2, and the fifth current IT5. The function generator circuit of By creating a similar tertiary temperature characteristic voltage Vc by synthesizing five control voltage groups, the variation factor is reduced by about 40% compared to the variation factor of the five components. Can do.
[0051]
According to the present embodiment, the approximate accuracy of the fourth electric signal Vc1 output as the approximate third-order temperature characteristic voltage Vc is 3 of the first current IT1, the second current IT2, and the fifth current IT5. Even if the control current group is made up of three continuous linearly changing control current groups, the first current IT1 and the second current IT2 are selectively synthesized to generate the third current IT3 and the fourth current IT4. The rounding effect of the selective synthesis portion when the sixth current IT6 is generated by selectively synthesizing the fourth current IT4 and the fifth current IT5, the first electrical signal V1, the second electrical signal V2, and the second electrical signal V2 3 with respect to the temperature of the electric signal V3, and the first differential current comparator 5, the second differential current comparator 6, the third differential current comparator 7, and the fourth differential current comparator 8 are adjusted. Can be adjusted by changing the selectivity Because, it can be a conventional function generator with the same accuracy by combining the five control voltage group are making approximate cubic temperature characteristic voltage Vc.
[0052]
Next, according to the present embodiment, when the current having the maximum current value is selected from the first current IT1 and the second current IT2 to generate the third current IT3, the power supply voltage at which this circuit operates The minimum voltage value of Vcc constitutes the first differential current comparator 5 and the minimum potential difference between the input and output of the current source that supplies the first current IT1 that can operate the current source that supplies the first current IT1. More than the voltage value obtained by adding the potential difference between the gate and source of the first PchMOS transistor M1 or the second PchMOS transistor M2 and the voltage value at which the first electric signal V1 and the second electric signal V2 have the same potential, Alternatively, the minimum potential difference between the input and output of the current source that supplies the second current IT2 that can operate the current source that supplies the second current IT2 and the third differential current comparator 6 are configured. Pch OS transistor M3 or is fourth and the potential difference between the gate and the source of the PchMOS transistor and a first electric signal V1 second electrical signal V2 is a voltage value greater than or equal to the sum of the voltage value at the same potential. Here, the minimum value of the potential difference between the average current input and output at which the current source can operate is 0.2 V, and the average between the gate and the source where the PchMOS transistor can pass the current between the source and the drain Assuming that the threshold voltage is 0.8 V and the voltage value at which the first electric signal V1 and the second electric signal V2 are at the same potential is 0.4 V, the minimum value of the power supply voltage Vcc at which this circuit can operate is 1.4V.
[0053]
Further, when the sixth current IT6 is generated by selectively synthesizing the fourth current IT4 and the fifth current IT5, the minimum voltage value of the power supply voltage Vcc at which this circuit operates supplies the fourth current IT4. The fifth Pch MOS transistor M5 or the sixth Pch MOS transistor M6 constituting the third differential current comparator 7 and the minimum potential difference between the input and output of the current source that supplies the fourth current IT4 that can operate the current source A current source that supplies the fifth current IT5 can operate, or the voltage difference between the gate and the source of the first and second electric signals V2 and V3 is equal to or higher than the voltage value of the same electric potential. The minimum potential difference between the input and output of the current source that supplies the fifth current IT5 and the seventh PchMOS transistor M7 or the eighth PchM constituting the fourth differential current comparator 8 S potential difference and the second electrical signal V2 and the third electrical signal V3 between the gate and source of the transistor M8 is equal to or greater than a voltage value obtained by adding a voltage value at the same potential. Here, the minimum value of the potential difference between the average current input and output at which the current source can operate is 0.2 V, and the average between the gate and the source where the PchMOS transistor can pass the current between the source and the drain Assuming that the threshold voltage is 0.8 V and the voltage value at which the second electric signal V2 and the third electric signal V3 are at the same potential is 0.8 V, the minimum value of the power supply voltage Vcc at which this circuit can operate is 1.8V.
[0054]
From these facts, in the function generation circuit of this embodiment, the minimum value of the power supply voltage Vcc is regulated by the voltage value at which the second electric signal V2 and the third electric signal V3 are at the same potential, and is approximated. It is related to the current values of three control current groups that change in three continuous straight lines of the first current IT1, the second current IT2, and the fifth current IT5, which are components of the tertiary temperature characteristic voltage Vc. Since the first electric signal V1, the second electric signal V2, and the third electric signal V3 can be arbitrarily designed to some extent, the function generation circuit of this embodiment sets the power supply voltage Vcc to 2. It can be operated at a low voltage of 0V or less.
[0055]
(First Modification of Embodiment)
Hereinafter, the 1st modification of one Embodiment of this invention is demonstrated based on drawing.
[0056]
FIG. 2 shows in detail the configuration of a function generation circuit according to a first modification of the embodiment. In FIG. 2, the components shown in FIG. Reference numeral 12 denotes a MAX circuit that selects and outputs a current having the maximum current value from among the input currents. Reference numeral 13 denotes a MIN circuit that selects and outputs a current having the minimum current value from among the input currents. Reference numeral 14 denotes a MAX circuit 12. A fifth differential current comparator, which is a component, 15 is a sixth differential current comparator, which is a component of the MAX circuit 12, 16 is a seventh differential current comparator, which is a component of the MIN circuit 13, and 17 is An eighth differential current comparator, which is a component of the MIN circuit 13, M9 is a first NchMOS transistor, M10 is a second NchMOS transistor, M11 is a third NchMOS transistor, M12 is a fourth NchMOS transistor, and M13 is The fifth NchMOS transistor, M14 is the sixth NchMOS transistor, and M15 is the seventh NchMO transistor. Transistor, M16 is an eighth Nch MOS transistor, R5 is a fifth resistor, R6 is a sixth resistor having a resistance value equivalent to the fifth resistor R5, and R7 has a resistance value equivalent to the fifth resistor R5 The seventh resistor, IT7 is a seventh current that decreases in proportion to the ambient temperature, IT8 is an eighth current that increases in proportion to the ambient temperature, IT9 is a ninth current that is the output current of the MAX circuit 12, IT10 is an output current of the first current mirror circuit 9 and has a current value equivalent to the ninth current IT9, IT11 is an eleventh current that decreases in proportion to the ambient temperature, and IT12 is a MIN circuit. 13 is the twelfth current, IT701 is the twentieth current proportional to the seventh current IT7, IT801 is the eighth current IT8 equivalent to the current ratio of the seventh current IT7 and the twentieth current IT701. Compared to The twenty-first current, IT1101 is the twenty-second current that is proportional to the eleventh current IT11 and the current ratio of the seventh current IT7 and the twentieth current IT701, and V4 is the twenty-first current IT701 and the fifth resistance. R5 is an electric signal converted into a current voltage and is a fifth electric signal proportional to the reverse polarity of the seventh current IT7. V5 is an electric signal obtained by converting the twenty-first current IT801 into a sixth resistor R6. There is a sixth electric signal proportional to the reverse polarity of the eighth current IT8, and V6 is an electric signal obtained by converting the twenty-second current IT1101 into a current and voltage by the seventh resistor R7 and has a reverse polarity to the eleventh current IT11. A proportional seventh electric signal, Vc2, is an eighth electric signal which is the output of the current-voltage conversion circuit 11. The eighth electric signal Vc2 is a control voltage Vc having an approximate third-order temperature characteristic for temperature compensation.
[0057]
In the MAX circuit 12, the sixth electric signal V5 is applied to the gate, the first NchMOS transistor M9 whose source is connected to the input side of the seventh current IT7, and the fifth electric signal V4 is applied to the gate. A fifth electrical signal V4 is connected to the gate of a fifth differential current comparator 14 composed of a second NchMOS transistor M10 having a source connected to the input side of the seventh current IT7 and a drain connected to the power supply Vcc. A sixth electrical signal V5 is applied to the gate of the third NchMOS transistor M11, the gate of which is applied and connected to the input side of the eighth current IT8, and the source is connected to the input side of the eighth current IT8; And a sixth differential current comparator 15 including a fourth NchMOS transistor M12 having a drain connected to the power supply Vcc. The current IT7 and the eighth current IT8 are input currents, the fifth electric signal V4 and the sixth electric signal V5 are current comparison control voltages, the drain of the first NchMOS transistor M9 and the third NchMOS transistor The drain of M11 is connected, and the current flowing through the common node is output as the ninth current IT9.
[0058]
In the MIN circuit 13, the sixth electrical signal V5 is applied to the gate, the fifth NchMOS transistor M13 to which the tenth current IT10 is applied to the source, the seventh electrical signal V6 is applied to the gate, and the source is the first. The seventh electric signal V6 is applied to the gate and the seventh differential current comparator 16 composed of the sixth NchMOS transistor M14 having the drain connected to the power supply Vcc and the drain connected to the input side of the current IT10. A sixth electric signal V5 is applied to the gate of the seventh NchMOS transistor M15 whose source is connected to the input side of the eleventh current IT11 and the gate, the source is connected to the input side of the eleventh current IT11, and the drain is the power supply And an eighth differential current comparator 17 composed of an eighth NchMOS transistor M16 connected to Vcc. Thus, the tenth current IT10 and the eleventh current IT11 are input currents, the sixth electric signal V5 and the seventh electric signal V6 are current comparison control voltages, and the drain of the fifth NchMOS transistor M13 The drain of the seventh NchMOS transistor M15 is connected, and the current flowing through the common node is output as the twelfth current IT12.
[0059]
The first current mirror circuit 9 and the second current mirror circuit 10 are connected to the function generation circuit of the embodiment of FIG. A current equivalent to the ninth current IT9 input to the input is output to the output of the first current mirror circuit 9 as a tenth current IT10. Even if the fifth NPN transistor Q9 and the sixth NPN transistor Q10 are replaced with NchMOS transistors, and the fifth PNP transistor Q11 and the sixth PNP transistor Q12 are replaced with PchMOS transistors, the same characteristics and effects are obtained. There is.
[0060]
The current-voltage conversion circuit 11 outputs the electric signal output to the first operational amplifier Amp1 as the eighth electric signal Vc2 using the twelfth current IT12 as an input current.
[0061]
With this configuration, the seventh current IT7 corresponds to the fifth current IT5, the eighth current IT8 corresponds to the second current IT2, the eleventh current IT11 corresponds to the first current IT1, and the polarity is inverted. By using the above-described characteristics, the function generation circuit according to the first modification of the embodiment of the present invention is the same as the function generation circuit according to the embodiment except that the polarities of the characteristics of the currents are reversed. Has properties and effects.
[0062]
(Second Modification of Embodiment)
Hereinafter, the 2nd modification of one Embodiment of this invention is demonstrated based on drawing.
[0063]
FIG. 3 shows in detail the configuration of a function generation circuit according to a second modification of the embodiment. In FIG. 3, the description of the components shown in FIG.
[0064]
Q13 is the seventh PNP transistor, Q14 is the eighth PNP transistor, Q15 is the ninth PNP transistor, Q16 is the tenth PNP transistor, Q17 is the eleventh PNP transistor, Q18 is the twelfth PNP transistor, and Q19 is The thirteenth PNP transistor, Q20, is a fourteenth PNP transistor.
[0065]
Here, the function generation circuit of the second modified example of the present embodiment includes the first PchMOS transistor M1 of FIG. 1 as the seventh PNP transistor Q13, the second PchMOS transistor M2 as the eighth PNP transistor Q14, The third PchMOS transistor M3 is the ninth PNP transistor Q15, the fourth PchMOS transistor M4 is the tenth PNP transistor Q16, the fifth PchMOS transistor M5 is the eleventh PNP transistor Q17, and the sixth PchMOS transistor. M6 is replaced with the twelfth PNP transistor Q18, the seventh PchMOS transistor M7 is replaced with the thirteenth PNP transistor Q19, and the eighth PchMOS transistor M8 is replaced with the fourteenth PNP transistor Q20. Form It has the same properties and advantages as the number generator.
[0066]
(Third Modification of Embodiment)
Hereinafter, the 3rd modification of one embodiment of the present invention is explained based on a drawing.
[0067]
FIG. 4 shows in detail the configuration of a function generation circuit according to a third modification of the embodiment. In FIG. 4, the components shown in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted.
[0068]
Q21 is the seventh NPN transistor, Q22 is the eighth NPN transistor, Q23 is the ninth NPN transistor, Q24 is the tenth NPN transistor, Q25 is the eleventh NPN transistor, Q26 is the twelfth NPN transistor, and Q27 is A thirteenth NPN transistor, Q28, is a fourteenth NPN transistor.
[0069]
Here, the function generation circuit of the third modification example of the present embodiment includes the first NchMOS transistor M9 of FIG. 2 as the seventh NPN transistor Q21 and the second NchMOS transistor M10 as the eighth NPN transistor Q22. The third NchMOS transistor M11 is the ninth NPN transistor Q23, the fourth NchMOS transistor M12 is the tenth NPN transistor Q24, the fifth NchMOS transistor M13 is the eleventh NPN transistor Q25, and the sixth NchMOS transistor. M14 is replaced with the twelfth NPN transistor Q26, the seventh NchMOS transistor M15 is replaced with the thirteenth NPN transistor Q27, and the eighth NchMOS transistor M16 is replaced with the fourteenth NPN transistor Q28. It has the same properties and advantages as the function generation circuit of the first modification of the embodiment.
[0070]
【The invention's effect】
As described above, in the present invention, the three control current groups that change the approximate third-order temperature characteristic voltage Vc into three continuous straight lines of the first current, the second current, and the fifth current, First, the current having the maximum current value is selected from the first current and the second current to generate the third current and the fourth current, and then the minimum current value of the fourth current and the fifth current is selected. As a sixth current generated by selecting a current having the following characteristics, and the sixth current is converted into a voltage by the first current-voltage conversion circuit, the characteristic variation factor of the approximate third-order temperature characteristic voltage is , The first current, the second current, and the fifth current are only the variations of the three components, and the conventional function generation circuit synthesizes the approximate third-order temperature characteristic voltage Vc into five control voltage groups. By making it, the variation factor is the variation of the five components. Then, a function generating circuit capable of reducing the variation factor of about 40%,
Further, the approximate third-order temperature characteristic voltage Vc is a voltage obtained by synthesizing three control current groups that change in three continuous straight lines of the first current, the second current, and the fifth current, and performing current-voltage conversion. Even if it is made, it is a function generation circuit that can make a third order approximation with the same accuracy as a conventional function generation circuit that synthesizes five control voltage groups to create an approximate third temperature characteristic voltage Vc.
In addition, the minimum value of the power supply voltage Vcc is regulated by the voltage value at which the second electric signal and the third electric signal have the same potential, and is the first element that is a component of the approximate third-order temperature characteristic voltage Vc. The first electric signal, the second electric signal, and the third electric current are not related to the current values of the three control current groups that change in three continuous straight lines of the current, the second current, and the fifth current. Since the electrical signal can be designed arbitrarily to some extent, it is a function generating circuit capable of operating at a power supply voltage Vcc as low as 2.0 V or less.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a function generation circuit according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a function generation circuit according to a first modification of the embodiment of the present invention.
FIG. 3 is a configuration diagram of a function generation circuit according to a second modification of the embodiment of the present invention.
FIG. 4 is a configuration diagram of a function generation circuit according to a third modification of the embodiment of the present invention.
FIG. 5 is a configuration diagram of a conventional function generation circuit.
FIG. 6 is a characteristic diagram with respect to temperature of voltage and current of each part of the function generation circuit in one embodiment of the present invention
[Explanation of symbols]
1, 3, 12 MAX circuit
2, 4, 13 MIN circuit
5 First differential current comparator
6 Second differential current comparator
7 Third differential current comparator
8 Fourth differential current comparator
9 First current mirror circuit
10 Second current mirror circuit
11 Current-voltage conversion circuit
14 Fifth differential current comparator
15 Sixth differential current comparator
16 Seventh differential current comparator
17 Eighth differential current comparator
Vcc supply voltage
Vref reference voltage
Amp1 first operational amplifier
IT1 First current
IT2 Second current
IT3 Third current
IT4 Fourth current
IT5 Fifth current
IT6 6th current
IT7 7th current
IT8 8th current
IT9 9th current
IT10 10th current
IT11 Eleventh current
IT12 12th current
IT101 17th current
IT201 18th current
IT501 19th current
IT701 20th current
IT801 21st current
IT1101 22nd current
V1 first electrical signal
V2 second electrical signal
V3 Third electrical signal
Vc1 Fourth electric signal (= control voltage Vc)
V4 fifth electrical signal
V5 6th electrical signal
V6 7th electrical signal
Vc2 Eighth electric signal (= control voltage Vc)
R1 first resistor
R2 second resistance
R3 Third resistance
R4 4th resistor
R5 5th resistor
R6 6th resistor
R7 7th resistor
M1 first PchMOS transistor
M2 Second PchMOS transistor
M3 Third PchMOS transistor
M4 Fourth PchMOS transistor
M5 Fifth PchMOS transistor
M6 Sixth PchMOS transistor
M7 Seventh PchMOS transistor
M8 Eighth PchMOS transistor
M9 First NchMOS transistor
M10 Second NchMOS transistor
M11 Third NchMOS transistor
M12 Fourth NchMOS transistor
M13 Fifth NchMOS transistor
M14 Sixth NchMOS transistor
M15 Seventh NchMOS transistor
M16 Eighth Nch MOS transistor
Q9 Fifth NPN transistor
Q10 Sixth NPN transistor
Q11 Fifth PNP transistor
Q12 Sixth PNP transistor
Q13 Seventh PNP transistor
Q14 Eighth PNP transistor
Q15 Ninth PNP transistor
Q16 Tenth PNP transistor
Q17 Eleventh PNP transistor
Q18 12th PNP transistor
Q19 13th PNP transistor
Q20 14th PNP transistor
Q21 7th NPN transistor
Q22 Eighth NPN transistor
Q23 9th NPN transistor
Q24 10th NPN transistor
Q25 Eleventh NPN transistor
Q26 12th NPN transistor
Q27 13th NPN transistor
Q28 14th NPN transistor
y1 9th electrical signal
y2 10th electrical signal
y3 eleventh electrical signal
y4 12th electrical signal
y5 thirteenth electrical signal
y6 14th electrical signal
y7 15th electric signal (= control voltage Vc)
Q1 first NPN transistor
Q2 Second NPN transistor
Q3 Third NPN transistor
Q4 Second PNP transistor
Q5 Third PNP transistor
Q6 First PNP transistor
Q7 Fourth NPN transistor
Q8 Fourth PNP transistor
I1 13th constant current source
I2 14th constant current source
I3 15th constant current source
I4 16th constant current source
I8 Fifth constant current source
I9 Sixth constant current source
T0 Center temperature of tertiary temperature characteristics
T1 Temperature at which the first current and the second current have the same value
T2 Temperature at which the fourth and fifth currents have the same value

Claims (4)

A first current that increases in proportion to the ambient temperature is used as a reference current for differential amplification, a first electrical signal proportional to the first current is input to one input thereof, and an ambient temperature is input to the other input. A first differential current comparator composed of a PchMOS transistor to which a second electric signal proportional to a second current that decreases in proportion to the first current is input, and the second current as a reference current for differential amplification A second differential current comparator composed of a PchMOS transistor having the first electric signal input to one input and the second electric signal input to the other input; The drain of the PchMOS transistor to which the second electric signal of the differential current comparator is input and the first electric signal of the second differential current comparator are input. A fourth current having a current value equivalent to the third current flowing in the common node is connected to the drain of the chMOS transistor as a reference current for differential amplification, and the second electric signal is input to one input thereof. A third differential current comparator composed of a PchMOS transistor, to which a third electric signal proportional to a fifth current increasing in proportion to the ambient temperature is input to the other input; Is a reference current for differential amplification, and the fourth difference is configured by a PchMOS transistor in which the second electric signal is input to one input and the third electric signal is input to the other input. A dynamic current comparator; a drain of the PchMOS transistor to which the second electrical signal of the third differential current comparator is input; and the fourth differential. Flow the third electrical signal of the comparator is connected to the drain of the PchMOS transistor is input, having a first current-voltage conversion circuit for current-voltage converting a sixth current flowing through the common node,
As the third current and the fourth current, a current having a maximum current value is selected and flows among the first current and the second current, and the fourth current includes the fourth current. A current having a minimum current value is selected and flows among the fifth currents, and the first current-voltage conversion circuit converts the sixth current into a voltage and outputs the voltage as a fourth electric signal. Characteristic function generator. The seventh current that decreases in proportion to the ambient temperature is used as a reference current for differential amplification, and a fifth electrical signal that increases in proportion to the seventh current is input to one input thereof, and the other input. A fifth differential current comparator composed of an Nch MOS transistor to which a sixth electrical signal that decreases in proportion to an eighth current that increases in proportion to the ambient temperature is input, and the eighth current A sixth differential current comparator composed of an Nch MOS transistor which is used as a reference current for differential amplification, the fifth electric signal being input to one input thereof, and the sixth electric signal being input to the other input. And a drain of an NchMOS transistor to which the sixth electric signal of the fifth differential current comparator is input and the fifth electric signal of the sixth differential current comparator The tenth current having a current value equivalent to the ninth current flowing in the common node is connected to the drain of the input NchMOS transistor, and the sixth current is used as a reference current for differential amplification. A seventh differential signal composed of an Nch MOS transistor, to which an electric signal is input and a seventh electric signal that increases in proportion to an eleventh current that decreases in proportion to the ambient temperature is input to the other input. A current comparator and an NchMOS transistor in which the eleventh current is used as a reference current for differential amplification, the sixth electric signal is input to one input, and the seventh electric signal is input to the other. An eighth differential current comparator configured and an NchMOS transistor to which the sixth electrical signal of the seventh differential current comparator is input; And the drain of the NchMOS transistor to which the seventh electric signal of the eighth differential current comparator is input is connected, and the twelfth current flowing through the common node is converted into a current voltage. A current-voltage conversion circuit;
The ninth current and the tenth current are selected from the seventh current and the eighth current and have a maximum current value, and the twelfth current includes the tenth current. Current having the minimum current value is selected and flows, and the twelfth current is converted into a voltage by the first current-voltage conversion circuit and output as an eighth electric signal. A function generation circuit characterized by that. The first differential current comparator, the second differential current comparator, the third differential current comparator, and the fourth differential current comparator are configured by PNP transistors. Item 4. The function generator circuit according to Item 1. The fifth differential current comparator, the sixth differential current comparator, the seventh differential current comparator, and the eighth differential current comparator are configured by NPN transistors. Item 3. The function generating circuit according to Item 2.

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