JPH08162744A - Land shape for surface mount pt plate - Google Patents

Land shape for surface mount pt plate

Info

Publication number
JPH08162744A
JPH08162744A JP6304547A JP30454794A JPH08162744A JP H08162744 A JPH08162744 A JP H08162744A JP 6304547 A JP6304547 A JP 6304547A JP 30454794 A JP30454794 A JP 30454794A JP H08162744 A JPH08162744 A JP H08162744A
Authority
JP
Japan
Prior art keywords
land
surface mounting
soldering
dip
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6304547A
Other languages
Japanese (ja)
Inventor
Tatsuhisa Nakajo
辰久 中條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP6304547A priority Critical patent/JPH08162744A/en
Publication of JPH08162744A publication Critical patent/JPH08162744A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3468—Applying molten solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Abstract

PURPOSE: To obtain a land shape for surface mount PT plates in which the quality is enhanced by improving the space factor and decreasing the number of times of thermal history. CONSTITUTION: In a multilayer printed wiring board 3 laminated through insulation layers, a land 31a for soldering the connection terminal 1a of an element 1 surface mounted together with a DIP device 2 or the like is connected through a copper plated hole (through hole) 36 with a wiring pattern 35a provided on a surface for soldering the DIP device. The surface mount element is dip soldered simultaneously with other DIP devices after the body part, other than the connection terminal, is bonded through adhesive 4 to the device mounting surface of the multilayer printed wiring board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、表面実装用素子（以下
ＳＭＤと略す）を実装する多層プリント配線基板のラン
ド形態に係わり、特に、ディップ部品等と混在して実装
する多層プリント配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a land form of a multilayer printed wiring board on which a surface mounting device (hereinafter abbreviated as SMD) is mounted, and more particularly to a multilayer printed wiring board mounted in a mixed manner with dip parts and the like. .

【０００２】[0002]

【従来の技術】従来、絶縁層を介して層状に積層してな
る多層プリント配線基板において、各配線パターン間の
接続は、通常、図３に示すように、表面実装用素子１の
端子部分１ａを半田付けするランド３１ａ以外の配線パ
ターン部分に接続用のランド３１ｄを設け、そのランド
３１ｄ内にスルーホール３６を設けて接続していた。ま
た、表面実装用素子の部品面への取付は、図４に示すよ
うに、部品取付面の表面実装用素子１の端子部分１ａを
半田付けするランド３１ａに、ソルダーペースト６を印
刷し、このソルダーペースト６上に表面実装用素子１を
乗せ、リフローして半田付けした後、ディップ部品２を
挿着してディップすることによりディップ部品を半田付
けして固定していた。このため、表面実装用素子１の配
線端子１ａを半田付けするランド３１ａ以外にスルーホ
ール用のランド３１ｄを設けなければならず、スペース
ファクターを悪化しているばかりか、リフロー，ディッ
プといった、熱履歴回数が多いため、部品や配線基板の
品質の劣化が問題となっていた。2. Description of the Related Art Conventionally, in a multilayer printed wiring board laminated in layers with an insulating layer in between, wiring patterns are usually connected to each other by a terminal portion 1a of a surface mounting element 1 as shown in FIG. The land 31d for connection is provided in the wiring pattern portion other than the land 31a for soldering, and the through hole 36 is provided in the land 31d for connection. Further, as shown in FIG. 4, the mounting of the surface mounting element on the component surface is performed by printing the solder paste 6 on the land 31a for soldering the terminal portion 1a of the surface mounting element 1 on the component mounting surface. The surface mounting element 1 is placed on the solder paste 6, reflowed and soldered, and then the dip component 2 is inserted and dipped to fix the dip component by soldering. Therefore, in addition to the land 31a to which the wiring terminal 1a of the surface mounting element 1 is soldered, the through hole land 31d must be provided, which not only deteriorates the space factor but also causes heat history such as reflow and dip. Due to the large number of times, deterioration of the quality of parts and wiring boards has been a problem.

【０００３】[0003]

【発明が解決しようとする課題】本発明は以上述べた問
題点を解決し、スペースファクターを良好にし、熱履歴
回数を減らして、品質を向上した表面実装用ＰＴ板のラ
ンド形態を提供することを目的としている。DISCLOSURE OF THE INVENTION The present invention solves the above-mentioned problems, provides a land form of a surface mounting PT plate having an improved space factor, a reduced number of heat history cycles and an improved quality. It is an object.

【０００４】[0004]

【課題を解決するための手段】本発明は上述の課題を解
決するため、絶縁層を介して層状に積層してなる多層プ
リント配線基板において、ディップ部品等を搭載する部
品面に設ける表面実装用素子の接続端子を半田付けする
ためのランドと、ディップ部品を半田付けする半田面に
設ける配線パターンとの間を銅等をメッキした孔、いわ
ゆるスルーホールを設けて接続している。また、前記表
面実装用素子は、該表面実装用素子の接続端子以外の本
体部分を前記多層プリント配線基板の部品面に接着剤で
固定した後、その他のディップ部品等と同時にディップ
して半田付けしている。In order to solve the above-mentioned problems, the present invention provides a surface mount for a multi-layer printed wiring board which is laminated in layers with an insulating layer interposed between the dip parts and the like. A land for soldering the connection terminal of the element and a wiring pattern provided on the solder surface for soldering the dip component are connected by providing a hole plated with copper or the like, a so-called through hole. In addition, the surface mount element is fixed to the component surface of the multilayer printed wiring board with an adhesive agent for the main body portion other than the connection terminals of the surface mount element, and then is dipped and soldered at the same time as other dip parts and the like. are doing.

【０００５】[0005]

【作用】以上のように構成したので、本発明の表面実装
用ＰＴ板のランド形態によれば、表面実装用素子の接続
端子を半田付けするためのランドと、ディップ部品を半
田付けする半田面に設ける配線パターンとの間を銅等で
形成するスルーホールにて接続しているので、表面実装
用素子をディップ部品等と同時にディップすることによ
り、スルーホール内に半田が浸透し、部品面のランド上
に達し、該ランド上に配置する表面実装用素子の配線端
子を半田付けしている。With the above configuration, according to the land form of the surface mounting PT plate of the present invention, the land for soldering the connection terminals of the surface mounting element and the solder surface for soldering the dip component Since it is connected to the wiring pattern provided in the through hole through a hole made of copper, etc., by dipping the surface mounting element at the same time as the dip component etc., the solder penetrates into the through hole and the component surface The wiring terminals of the surface-mounting element which reach the land and are arranged on the land are soldered.

【０００６】[0006]

【実施例】以下、図面に基づいて本発明による表面実装
用ＰＴ板のランド形態を詳細に説明する。図１は本発明
による表面実装用ＰＴ板のランド形態の一実施例を示す
平断面図である。図において、１はチップ部品やパッケ
イジＩＣ等の表面実装用素子である。２はディップ部
品、３は多層プリント配線基板、４は接着剤、そして５
は半田である。多層プリント配線基板３の部品面には、
表面実装用素子１の配線端子１ａを半田付けするランド
３１ａ，ディップ部品２の配線用リード２ａを挿着する
ランド３１ｂ，前記ランド３１ａ，３１ｂ間を接続する
パターン３１ｃ等を形成している。また、多層プリント
配線基板３の半田面には、配線用パターン３５ａ，ディ
ップ部品２の配線用リード２ａの半田付け用ランド３５
ｂ等を形成している。また、多層プリント配線基板３の
内部は、第一の絶縁板３２．内層パターン３３、第二の
絶縁板３４等を形成し、前記部品面に形成するランド３
１ａと部品面に形成する配線用パターン３５ａとをスル
ーホール３６で接続している。DESCRIPTION OF THE PREFERRED EMBODIMENTS The land form of the surface mounting PT plate according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a plan sectional view showing an embodiment of a land form of a surface mounting PT plate according to the present invention. In the figure, reference numeral 1 is a surface mounting element such as a chip component or a package IC. 2 is a dip component, 3 is a multilayer printed wiring board, 4 is an adhesive, and 5
Is solder. On the component side of the multilayer printed wiring board 3,
A land 31a for soldering the wiring terminal 1a of the surface mounting element 1, a land 31b for inserting the wiring lead 2a of the dip component 2, a pattern 31c for connecting the lands 31a and 31b, and the like are formed. Further, on the solder surface of the multilayer printed wiring board 3, a wiring pattern 35a and a solder land 35 for the wiring lead 2a of the dip component 2 are formed.
b, etc. are formed. In addition, inside the multilayer printed wiring board 3, the first insulating plate 32. Land 3 formed on the component surface by forming the inner layer pattern 33, the second insulating plate 34, and the like.
1a and a wiring pattern 35a formed on the component surface are connected by a through hole 36.

【０００７】図２は、上記多層プリント配線基板３に表
面実装用素子１やディップ部品２を半田付けする工程の
概略フローである。以下に、部品の半田付け工程につい
て説明する。工程Ｓ１で、表面実装用素子１の本体部１
ｂに接着剤４を塗布し、Ｓ２で表面実装用素子１をその
接続端子１ａが対応するランド３１ａに合うように多層
プリント配線基板３の部品面に装着する。次ぎに、Ｓ３
で、ディップ部品２の配線リード２ａをランド３１ｂに
設けるスルーホールメッキされた孔に挿着し、Ｓ４で半
田ディップすることにより、ディップ部品および、表面
実装用素子を半田付けしている。尚、本例ではＳ１で、
表面実装用素子１の本体部１ｂに接着剤４を塗布した
が、表面実装用素子１に対応する多層プリント配線板３
の部品装着部に接着剤を塗布してもよい。また、半田面
に配線パターンを必要としない場合でも、半田付け用の
パターンを設け、スルーホールで接続することにより、
表面実装用素子への半田付けが実現できる。FIG. 2 is a schematic flow chart of a process of soldering the surface mounting element 1 and the dip component 2 to the multilayer printed wiring board 3. The soldering process of components will be described below. In step S1, the main body 1 of the surface mounting element 1
The adhesive 4 is applied to the surface b, and the surface mounting element 1 is mounted on the component surface of the multilayer printed wiring board 3 in step S2 so that the connection terminals 1a thereof match the corresponding lands 31a. Next, S3
Then, the wiring lead 2a of the dip component 2 is inserted into the through-hole plated hole provided on the land 31b, and the dip component and the surface mounting element are soldered by solder dipping in S4. In this example, S1
Although the adhesive 4 is applied to the main body 1b of the surface mounting element 1, the multilayer printed wiring board 3 corresponding to the surface mounting element 1 is used.
An adhesive may be applied to the component mounting portion. Also, even if you do not need a wiring pattern on the solder side, by providing a pattern for soldering and connecting with a through hole,
Soldering to the surface mount device can be realized.

【０００８】[0008]

【発明の効果】以上説明したように、本発明による表面
実装用ＰＴ板のランド形態によれば、表面実装用素子の
接続端子を半田付けするためのランドと、ディップ部品
を半田付けする半田面に設ける配線パターンとの間を銅
等で形成するスルーホールにて接続しているので、表面
実装用素子をディップ部品等と同時にディップすること
により、スルーホール内に半田が浸透し、部品面のラン
ド上に達し、該ランド上に配置する表面実装用素子の配
線端子を半田付けしているので、スペースファクターを
良好にし、熱履歴回数を減らして、品質を向上すること
ができる。As described above, according to the land form of the PT plate for surface mounting according to the present invention, the land for soldering the connection terminal of the surface mounting element and the soldering surface for soldering the dip component. Since it is connected to the wiring pattern provided in the through hole through a hole made of copper, etc., by dipping the surface mounting element at the same time as the dip component etc., the solder penetrates into the through hole and the component surface Since the wiring terminal of the surface mounting element which reaches the land and is arranged on the land is soldered, the space factor can be improved, the number of heat history can be reduced, and the quality can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による表面実装用ＰＴ板のランド形態の
一実施例を示す平断面図である。FIG. 1 is a plan sectional view showing an example of land configurations of a surface mounting PT plate according to the present invention.

【図２】本発明による表面実装用ＰＴ板のランド形態に
おける半田付け工程の概略フローである。FIG. 2 is a schematic flow of a soldering process in a land form of a surface mounting PT plate according to the present invention.

【図３】従来の表面実装用ＰＴ板のランド形態を示す平
断面図である。FIG. 3 is a plan sectional view showing a land form of a conventional surface mounting PT plate.

【図４】従来の表面実装用ＰＴ板のランド形態における
半田付け工程の概略フローである。FIG. 4 is a schematic flow of a soldering process in a land form of a conventional surface mounting PT plate.

【符号の説明】[Explanation of symbols]

１ 表面実装用素子 １ａ接続端子 ２ ディップ部品 ２ａ配線リード ３ 多層プリント配線基板 ４ 接着剤 ５ 半田 ３１ａランド ３１ｂランド ３１ｃパターン ３２第一の絶縁層 ３３内層パターン ３４第二の絶縁層 ３５ａ配線パターン ３５ｂランド ３６スルーホール 1 Surface Mount Element 1a Connection Terminal 2 Dip Component 2a Wiring Lead 3 Multilayer Printed Wiring Board 4 Adhesive 5 Solder 31a Land 31b Land 31c Pattern 32 First Insulating Layer 33 Inner Layer Pattern 34 Second Insulating Layer 35a Wiring Pattern 35b Land 36 through holes

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 絶縁層を介して層状に積層してなる多層
プリント配線基板において、ディップ部品等を搭載する
部品面に設ける表面実装用素子の接続端子を半田付けす
るためのランドと、ディップ部品を半田付けする半田面
に設ける配線パターンとの間を銅等をメッキした孔（ス
ルーホール）を設けて接続していることを特徴とする表
面実装用ＰＴ板のランド形態。1. A multi-layer printed wiring board formed by stacking layers with an insulating layer in between, a land for soldering a connection terminal of a surface mounting element provided on a component surface on which a dip component or the like is mounted, and a dip component. A land form of a PT plate for surface mounting, characterized in that a hole (through hole) plated with copper or the like is provided and connected to a wiring pattern provided on a solder surface for soldering. 【請求項２】 前記表面実装用素子は、該表面実装用素
子の接続端子以外の本体部分を前記多層プリント配線基
板の部品面に接着剤で固定した後、その他のディップ部
品等と同時にディップして半田付けしていることを特徴
とする請求項１記載の表面実装用ＰＴ板のランド形態。2. The surface mounting element is fixed to the component surface of the multi-layer printed wiring board by an adhesive agent on the main body portion other than the connection terminals of the surface mounting element, and then diped at the same time as other dip components and the like. The land form of the PT plate for surface mounting according to claim 1, wherein the land form is soldered by soldering. 【請求項３】 スルーホールで接続する前記部品面に設
ける表面実装用素子の接続端子を半田付けするためのラ
ンドと半田面に設ける配線パターンの少なくともスルー
ホールの周辺は銅メッキしていることを特徴とする請求
項１記載の表面実装用ＰＴ板のランド形態。3. A land for soldering a connection terminal of a surface mounting element provided on the surface of the component to be connected by a through hole and a wiring pattern provided on the solder surface, at least the periphery of the through hole is copper-plated. The land form of the PT plate for surface mounting according to claim 1.
JP6304547A 1994-12-08 1994-12-08 Land shape for surface mount pt plate Pending JPH08162744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6304547A JPH08162744A (en) 1994-12-08 1994-12-08 Land shape for surface mount pt plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6304547A JPH08162744A (en) 1994-12-08 1994-12-08 Land shape for surface mount pt plate

Publications (1)

Publication Number Publication Date
JPH08162744A true JPH08162744A (en) 1996-06-21

Family

ID=17934316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6304547A Pending JPH08162744A (en) 1994-12-08 1994-12-08 Land shape for surface mount pt plate

Country Status (1)

Country Link
JP (1) JPH08162744A (en)

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