JPH08162491A - Formation of bump on ic chip - Google Patents
Formation of bump on ic chipInfo
- Publication number
- JPH08162491A JPH08162491A JP6303429A JP30342994A JPH08162491A JP H08162491 A JPH08162491 A JP H08162491A JP 6303429 A JP6303429 A JP 6303429A JP 30342994 A JP30342994 A JP 30342994A JP H08162491 A JPH08162491 A JP H08162491A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- chip
- bumps
- bump
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣチップをＴＡＢテ
ープや実装基板等の外部電極とを接続する為の接続部分
に係わり、特にＩＣチップ上に設けられるバンプの形成
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connecting portion for connecting an IC chip to an external electrode such as a TAB tape or a mounting substrate, and more particularly to a method for forming bumps provided on the IC chip.
【０００２】[0002]
【従来の技術】図５〜図８は従来例の説明図である。１
はＩＣチップ、２はパッド、３はめっきバンプ、４はボ
ンディングバンプ、５はＴＡＢテープ、６はＴＡＢリー
ド、７はボンディングツール、14はキャピラリ、15はワ
イヤ、16はトーチ電極、17は金ボール、18はレジストで
ある。2. Description of the Related Art FIGS. 5 to 8 are explanatory views of a conventional example. 1
Is an IC chip, 2 is a pad, 3 is a plating bump, 4 is a bonding bump, 5 is a TAB tape, 6 is a TAB lead, 7 is a bonding tool, 14 is a capillary, 15 is a wire, 16 is a torch electrode, and 17 is a gold ball. , 18 are resists.
【０００３】従来のＩＣチップ上のバンプの形成方法に
は、先ず、図５に示すような、ワイヤーボンディング技
術を応用してＩＣチップのパッド電極上にバンプ（以下
ボンディングバンプと呼ぶ）を形成する方法（特開昭６
０−１９４５４３）がある。In the conventional method of forming bumps on an IC chip, first, as shown in FIG. 5, a wire bonding technique is applied to form bumps (hereinafter referred to as bonding bumps) on pad electrodes of the IC chip. Method (JP-A-6
0-194543).
【０００４】即ち、図５（ａ）に示すように、ＩＣチッ
プ１上に形成されたAl等のパッド２の上に金のワイヤ15
を繰り出すキャピラリ14を位置決めし、ワイヤ15をトー
チ電極16で加熱する。That is, as shown in FIG. 5A, a gold wire 15 is formed on a pad 2 such as Al formed on the IC chip 1.
The capillary 14 for feeding the wire is positioned, and the wire 15 is heated by the torch electrode 16.
【０００５】すると、図５（ｂ）に示すように、ワイヤ
15の先端が融解して、金ボール17となる。続いて、図５
（ｃ）に示すように、この金ボール17をキャピラリ14の
先端でパッド２上に熱圧着により押し付ける。Then, as shown in FIG.
The tip of 15 melts and becomes a gold ball 17. Then, FIG.
As shown in (c), the gold ball 17 is pressed against the pad 2 by thermocompression bonding with the tip of the capillary 14.
【０００６】そして、図５（ｄ）に示すように、キャピ
ラリ14によりワイヤ15を引っ張り上げると、ワイヤ15が
切れて、パッド２上には金ボール17がややつぶれた形の
ボンディングバンプ４が形成される。Then, as shown in FIG. 5 (d), when the wire 15 is pulled up by the capillary 14, the wire 15 is broken, and the bonding bump 4 in which the gold ball 17 is slightly crushed is formed on the pad 2. To be done.
【０００７】次に、図６に示すような、ＩＣチップのパ
ッド電極上に、電解めっきでバンプ（以下めっきバンプ
と呼ぶ。）を形成する場合には、図６（ａ）に示すよう
に、ＩＣチップ１を構成するウェーハの上にレジスト18
を塗布し、図６（ｂ）に示すように、フォトリソグラフ
ィによりめっきをつけるパッド２の上のみレジスト18を
除去する。Next, when a bump (hereinafter referred to as a plating bump) is formed by electrolytic plating on a pad electrode of an IC chip as shown in FIG. 6, as shown in FIG. Resist 18 on the wafer that constitutes IC chip 1
Is applied, and as shown in FIG. 6B, the resist 18 is removed only on the pad 2 to be plated by photolithography.
【０００８】次に、図６（ｃ）に示すように、レジスト
18が除去された所のみ、めっきを行い、めっきバンプ３
を形成する。そして、めっき終了後にレジスト18を全面
除去すると、図６（ｄ）に示すように、ＩＣチップ１の
パッド２上には、めっきバンプ３のみが残る。Next, as shown in FIG. 6C, the resist
Plating is performed only on the place where 18 is removed, and the plating bump 3
To form. When the entire surface of the resist 18 is removed after the plating is completed, only the plating bumps 3 remain on the pads 2 of the IC chip 1 as shown in FIG.
【０００９】[0009]
【発明が解決しようとする課題】図５に示すような従来
の方法では、高純度の金のワイヤ15からボンディングバ
ンプ４を形成するために、ボンディングバンプ４が軟ら
かく、図７（ａ）に示すように、ボンディングバンプ４
上にＴＡＢテープ５上のＴＡＢリード６を位置合わせ
し、ボンディングツール７によりＴＡＢリード６をボン
ディングバンプ４に加圧により接合すると、ボンディン
グバンプ４が図７（ｂ）に示すように潰れてしまいやす
い。In the conventional method as shown in FIG. 5, since the bonding bumps 4 are formed from the high-purity gold wire 15, the bonding bumps 4 are soft, and the bonding bumps 4 are shown in FIG. 7 (a). So that the bonding bump 4
When the TAB leads 6 on the TAB tape 5 are aligned on the upper side and the TAB leads 6 are bonded to the bonding bumps 4 by pressure with the bonding tool 7, the bonding bumps 4 are easily crushed as shown in FIG. 7B. .
【００１０】即ち、このボンディングバンプはＴＡＢテ
ープ５や実装基板等の外部電極と接続しようとすると、
接続した時のボンディング圧力でボンディングバンプが
潰れてしまい、図７（ｂ）に示すように、ＩＣチップ１
が少しでも傾いていると、片側のボンディングバンプ４
が潰れすぎてしまうため、ＩＣチップ１のトップエッジ
がＴＡＢテープ５のＴＡＢリード６や実装基板のフット
パターンと接触してしまい、電気的にショート（接触）
を起こしてしまうという問題があった。That is, when the bonding bumps are to be connected to external electrodes such as the TAB tape 5 and the mounting substrate,
The bonding bump is crushed by the bonding pressure at the time of connection, and as shown in FIG.
Is slightly tilted, the bonding bumps 4 on one side
Becomes excessively crushed, the top edge of the IC chip 1 comes into contact with the TAB lead 6 of the TAB tape 5 and the foot pattern of the mounting board, and electrically shorts (contacts).
There was a problem of causing.
【００１１】又、これを防止しようとして、金のワイヤ
15に種々の金属ドーパントを入れて硬くすると、パッド
２上にボンディングバンプ４を付ける時、パッド２下に
ダメージが入り、パッド２下からリーク電流が流れてし
まうといった問題が発生していた。In an attempt to prevent this, gold wire
If various metal dopants are added to 15 to make them hard, when the bonding bumps 4 are attached on the pads 2, there is a problem in that damage occurs under the pads 2 and a leak current flows from under the pads 2.
【００１２】更に、めっきバンプ３の場合には、図８
（ａ）に示すように、めっきバンプ３に高さのバラツキ
がある場合には、図８（ｂ）に示すように、低いバンプ
３とＴＡＢリード６は接触出来ず、加圧されないため
に、隙間が出来て接合ができなくなるという問題があ
る。Further, in the case of the plated bump 3, FIG.
As shown in FIG. 8A, when the plating bumps 3 have variations in height, as shown in FIG. 8B, the low bumps 3 and the TAB leads 6 cannot contact each other and are not pressed, There is a problem that a gap is created and joining cannot be performed.
【００１３】以上の問題点に鑑み、本発明は、ＩＣチッ
プのパッドとバンプの高い信頼性のあるボンディング方
法を得ることを目的とする。In view of the above problems, it is an object of the present invention to obtain a highly reliable bonding method for pads and bumps of an IC chip.
【００１４】[0014]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において、１はＩＣチップ、２はパッド、
３はめっきバンプ、４はボンディングバンプ、５はＴＡ
Ｂテープ、６はＴＡＢリード、７はボンディングツー
ル、８は実装基板、９は外部電極である。FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is an IC chip, 2 is a pad,
3 is a plating bump, 4 is a bonding bump, 5 is a TA
B tape, 6 is a TAB lead, 7 is a bonding tool, 8 is a mounting substrate, and 9 is an external electrode.
【００１５】上記の問題点を解決する手段として、図１
（ａ）に示すように、ＩＣチップ１のパッド２の部分に
チップエッジでの電気的ショートを防止出来る程度の厚
さのめっきバンプ３を最初に施し、その上にボンディン
グバンプ４を付ける。As a means for solving the above problems, FIG.
As shown in (a), the pad 2 of the IC chip 1 is first provided with a plating bump 3 having a thickness sufficient to prevent an electrical short at the chip edge, and a bonding bump 4 is attached thereon.
【００１６】すなわち、本発明の目的は、図１に示すよ
うに、ＴＡＢテープ５、或いは実装基板８上にＩＣチッ
プ１を接合するバンプの形成方法であって、ＩＣチップ
１のパッド２上に選択的にめっきバンプ３を形成し、続
いて該めっきバンプ３上にボンディングワイヤのボール
からなるボンディングバンプ４を形成することにより、
また、ＩＣチップ１のパッド２上に、ボンディングワイ
ヤのボールからなる二個以上のボンディングバンプ４を
形成することにより、更に、実装基板８上に形成された
ボンディングワイヤのボールからなるボンディングバン
プ４に向かい合って、ＩＣチップ１のパッド２上に、ボ
ンディングワイヤを用いてボンディングバンプ４を形成
することにより達成される。That is, as shown in FIG. 1, an object of the present invention is a method of forming bumps for bonding the IC chip 1 on the TAB tape 5 or the mounting substrate 8, and on the pad 2 of the IC chip 1. By selectively forming the plating bumps 3 and subsequently forming the bonding bumps 4 formed of balls of bonding wires on the plating bumps 3,
Further, by forming two or more bonding bumps 4 made of balls of bonding wires on the pads 2 of the IC chip 1, the bonding bumps 4 made of balls of bonding wires formed on the mounting substrate 8 are further formed. This is achieved by forming bonding bumps 4 on the pads 2 of the IC chip 1 facing each other using bonding wires.
【００１７】[0017]
【作用】本発明においては、図１（ｂ）に示すような、
バンプを形成した時の高さのバラツキや、ＩＣチップ自
体の反りや、厚さのバラツキによるバンプ上面の高さの
不揃いをボンディングバンプ部分が軟らかい為、図１
（ｃ）に示すように、ボンディング圧力でボンディング
バンプが潰れる事で、バンプ上面の高さが均一になり、
安定したボンディングが可能となる。又、ボンディング
バンプの下に施されためっきバンプは、ボンディング圧
力にはほとんど潰れる事がない為、ＩＣチップのエッジ
とＴＡＢテープのリードとの隙間を確保して、電気的シ
ョートの発生を防止する。In the present invention, as shown in FIG.
The height of the bumps when they are formed, the warp of the IC chip itself, and the unevenness of the height of the bumps due to the variation of the thickness make the bonding bumps soft.
As shown in (c), since the bonding bumps are crushed by the bonding pressure, the heights of the upper surfaces of the bumps become uniform,
Stable bonding is possible. Further, since the plated bumps provided under the bonding bumps are hardly crushed by the bonding pressure, a gap between the edge of the IC chip and the lead of the TAB tape is secured to prevent occurrence of electrical short circuit. .
【００１８】そして、実装基板等の外部電極と接続しよ
うとする時も、図１（ｄ）に示すように同様の効果が得
られる。又、ＴＡＢテープや実装基板の熱膨張や外部圧
力等により、ＩＣチップとの間に歪が生じた場合、ＩＣ
チップとの接続部分に変形しやすい金のボンディングバ
ンプを使用する事により、ＩＣチップとＴＡＢテープ及
びＩＣチップと実装基板等の間に発生した歪を金のボン
ディングバンプが変形して吸収する事が可能になる。こ
の事により、高い信頼性のあるボンディングを行える。Also, when connecting to an external electrode such as a mounting board, the same effect can be obtained as shown in FIG. 1 (d). In addition, when strain occurs between the IC chip and the TAB tape or the mounting substrate due to thermal expansion or external pressure, the IC
By using the gold bonding bumps that are easily deformed at the connecting portion with the chip, the gold bonding bumps may be deformed and absorb the strain generated between the IC chip and the TAB tape and between the IC chip and the mounting substrate. It will be possible. This enables highly reliable bonding.
【００１９】[0019]
【実施例】図２〜図４は本発明の三つの実施例の説明図
である。図において、１はＩＣチップ、２はパッド、３
はめっきバンプ、４はボンディングバンプ、８は実装基
板、９は外部電極、10はカメラ、11はボンディング機構
部、12はチップ搬送ツール、13は基板固定台である。2 to 4 are explanatory views of three embodiments of the present invention. In the figure, 1 is an IC chip, 2 is a pad, 3
Is a plating bump, 4 is a bonding bump, 8 is a mounting substrate, 9 is an external electrode, 10 is a camera, 11 is a bonding mechanism section, 12 is a chip transfer tool, and 13 is a substrate fixing base.
【００２０】第１の実施例では、図２（ａ）に示すよう
に、ＩＣチップ１上に形成されたAl電極からなるパッド
２上にレジストピーリング法によりめっきバンプ３を最
初に施した後、ボンディングバンプ４を付けて、ＴＡＢ
テープのリードや実装基板等に接続する場合である。In the first embodiment, as shown in FIG. 2A, after the plating bumps 3 are first applied by the resist peeling method on the pads 2 made of Al electrodes formed on the IC chip 1, Attach the bonding bump 4 and TAB
This is a case where the tape is connected to a lead or a mounting board.
【００２１】本発明に用いたボンディングバンプ４の大
きさは３０μｍ径の金線を用い、厚さ２５μｍで１００
μｍ径である。形成方法は、図２（ｂ）に示すように、
通常のワイヤボンディングと同じ様に相対する２カ所の
ＩＣチップ１のコーナーをテレビ用のカメラ10で認識さ
せ、続いて、図２（ｃ）に示すように、ＩＣチップ１の
位置を確認し、あらかじめボンディング機構部11に入力
しておいたパッド座標を用いてボンディングバンプ４を
形成する。The size of the bonding bump 4 used in the present invention is 100 μm when a gold wire having a diameter of 30 μm is used and a thickness of 25 μm.
μm diameter. The forming method is as shown in FIG.
The TV camera 10 recognizes the two corners of the IC chip 1 facing each other as in the case of normal wire bonding, and then confirms the position of the IC chip 1 as shown in FIG. 2 (c). The bonding bumps 4 are formed using the pad coordinates that have been input to the bonding mechanism unit 11 in advance.
【００２２】通常めっきバンプ３は金メッキでできてお
り、ＩＣチップ１のパッド２はAlで出来ているため、め
っきバンプ３にボンディングバンプ４を付ける時は、Al
のパッド２に付けるよりも温度や超音波の出力が低くて
すみ、ＩＣチップ１にダメージを与えることが少ない。
すなわち、Alパッド２上にボンディングバンプ４を付け
る時は２５０℃で超音波を掛けるが、めっきバンプ３上
にボンディングバンプ４を付ける時には２００℃で超音
波の出力も２割減ですむ。Since the plating bumps 3 are usually made of gold and the pads 2 of the IC chip 1 are made of Al, when the bonding bumps 4 are attached to the plating bumps 3, Al is used.
Since the temperature and the output of ultrasonic waves are lower than those applied to the pad 2, the IC chip 1 is less likely to be damaged.
That is, ultrasonic waves are applied at 250 ° C. when the bonding bumps 4 are attached on the Al pads 2, but ultrasonic wave output can be reduced by 20% at 200 ° C. when the bonding bumps 4 are attached on the plating bumps 3.
【００２３】第２の実施例では、図３に示すように、ボ
ンディングバンプ４を２個以上重ねて、ＴＡＢテープの
リードや実装基板等に接続する場合である。この場合
は、ボンディングバンプ４の高さが２個以上の分まで高
くする事で、ＩＣチップ１のエッジとＴＡＢテープのリ
ードとの隙間を確保し、電気的ショートの発生を防止す
る事が可能になっている。バンプの潰れる量も２倍にな
る事から、ボンディングの安定性も更に向上することい
うまでもない。In the second embodiment, as shown in FIG. 3, two or more bonding bumps 4 are piled up and connected to a lead of a TAB tape, a mounting board or the like. In this case, by increasing the height of the bonding bumps 4 to 2 or more, it is possible to secure a gap between the edge of the IC chip 1 and the lead of the TAB tape and prevent the occurrence of an electrical short. It has become. Since the amount of bumps crushed is doubled, it goes without saying that the stability of bonding is further improved.
【００２４】またボンディングバンプ４の積み重ねは図
３（ａ）に示すように２個とは限らず、図３（ｂ）に示
すように３個以上を積み重ねて形成することも出来る。
ボンディングバンプ４自体は軟らかいため、下側のボン
ディングバンプ４の表面に若干の凹凸があっても、その
上側にボンディングバンプ４を重ねて形成した場合、表
面の凹凸が変形してボンディングバンプ４同士の接合が
確実に行える。The number of the bonding bumps 4 stacked is not limited to two as shown in FIG. 3A, and three or more bonding bumps 4 can be stacked as shown in FIG. 3B.
Since the bonding bumps 4 themselves are soft, even if the bonding bumps 4 on the lower side have some irregularities, when the bonding bumps 4 are formed on the upper side of the bonding bumps 4, the irregularities on the surface deform and the bonding bumps 4 are separated from each other. Can be reliably joined.
【００２５】本発明の第３の実施例であるボンディング
バンプの付いた実装基板とボンディングバンプの付いた
ＩＣチップを接合させる方法は、第１の実施例と同様に
実装基板上にボンディングバンプを形成した後、従来か
ら用いられているフリップチップボンダーと同じ機構で
接合を行う。A third embodiment of the present invention, which is a method for joining a mounting substrate having bonding bumps and an IC chip having bonding bumps, is to form bonding bumps on the mounting substrate as in the first embodiment. After that, the bonding is performed by the same mechanism as the flip chip bonder that has been used conventionally.
【００２６】すなわち、図４（ａ）に示すように、ＩＣ
チップ１のパッド部に金の第１のボンディングバンプ４
ａを形成し、又、実装基板８の外部電極９にはんだの第
２のボンディングバンプ４ｂを形成して、接続を行う。That is, as shown in FIG.
First bonding bump 4 of gold on the pad portion of chip 1
a is formed, and the second bonding bumps 4b of solder are formed on the external electrodes 9 of the mounting substrate 8 for connection.
【００２７】ＩＣチップ１上の金の第１のボンディング
バンプ４ａと実装基板８上のはんだの第２のボンディン
グバンプ４ｂを接合する時、図４（ｂ）に示すように、
ＩＣチップ１を実装基板８の外部電極９上まで運ぶチッ
プ搬送ツール12を、約３００℃まで温度を上げて、図４
（ｃ）に示すように、位置決めしたボンディングバンプ
バンプ同士を接触させると、チップ搬送ツール12の熱で
実装基板８上のはんだが溶融して、ＩＣチップ１の金バ
ンプを合金化し、安定したボンディングが可能となる。When the gold first bonding bumps 4a on the IC chip 1 and the solder second bonding bumps 4b on the mounting substrate 8 are joined, as shown in FIG.
The temperature of the chip transfer tool 12 that carries the IC chip 1 onto the external electrodes 9 of the mounting substrate 8 is raised to about 300 ° C.
As shown in (c), when the positioned bonding bump bumps are brought into contact with each other, the solder on the mounting substrate 8 is melted by the heat of the chip transfer tool 12, and the gold bumps of the IC chip 1 are alloyed for stable bonding. Is possible.
【００２８】ＩＣチップ１と実装基板８との位置合わせ
方法は、図４（ｂ）に示すように、テレビカメラ10で実
装基板８とＩＣチップ１の位置を確認し、続いて、図４
（ｃ）に示すように、ＩＣチップ１と実装基板８とをボ
ンディング機構部11の下に移動させ、ボンディング機構
部11で圧力と温度を掛けて接合する。As shown in FIG. 4 (b), the method of aligning the IC chip 1 and the mounting substrate 8 is as follows.
As shown in (c), the IC chip 1 and the mounting substrate 8 are moved below the bonding mechanism section 11 and bonded by applying pressure and temperature to the bonding mechanism section 11.
【００２９】この第３の実施例の場合でも、図３（ｂ）
の場合と同様に、ボンディングバンプ４を２個分以上に
高くする事により、ＩＣチップ１のエッジと実装基板８
との接触による電気的ショートの発生を防止する事が可
能になっている。Even in the case of this third embodiment, FIG.
In the same manner as in the above case, the edges of the IC chip 1 and the mounting substrate 8 are increased by raising the bonding bumps 4 by two or more.
It is possible to prevent the occurrence of an electrical short circuit due to contact with.
【００３０】又、バンプの潰れる量も２倍またはそれ以
上になる事から、ボンディングの安定性も更に向上す
る。Further, since the amount of crushed bumps is doubled or more, the stability of bonding is further improved.
【００３１】[0031]
【発明の効果】以上説明したように、本発明を用いる事
で、ＩＣチップを一括して安定してＴＡＢテープや実装
基板にボンディングする事が可能になり、歩留りが向上
する。As described above, by using the present invention, it becomes possible to collectively and stably bond the IC chips to the TAB tape or the mounting substrate, and the yield is improved.
【００３２】又、熱膨張等のストレスに対しても強くな
る為に、接続部分の信頼性も向上するため、低コストで
信頼性の高いＩＣチップの高密度実装が可能になる。更
に、めっきバンプ上にバンプを重ねてインナーリードボ
ンディングを行う場合、通常のめっきバンプの厚さ２５
μｍを１５μｍ程度まで低くすることが出来、この事に
よりめっきバンプをチップのパッド上に形成する時間を
減らす事が可能となり、生産能力の増大に結びつく。
又、使用する金の量を減らせるため、製造コストの減少
にも寄与する。Further, since it is also resistant to stress such as thermal expansion, the reliability of the connecting portion is also improved, so that high-density mounting of IC chips can be achieved at low cost and with high reliability. Further, when the inner lead bonding is performed by stacking the bumps on the plated bumps, the thickness of the ordinary plated bumps is 25
The μm can be lowered to about 15 μm, which makes it possible to reduce the time for forming the plating bumps on the chip pads, which leads to an increase in production capacity.
Further, since the amount of gold used can be reduced, it contributes to the reduction of manufacturing cost.
【図１】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】 本発明の第１の実施例の説明図FIG. 2 is an explanatory diagram of a first embodiment of the present invention.
【図３】 本発明の第２の実施例の説明図FIG. 3 is an explanatory diagram of a second embodiment of the present invention.
【図４】 本発明の第３の実施例の説明図FIG. 4 is an explanatory diagram of a third embodiment of the present invention.
【図５】 従来例の説明図（その１）FIG. 5 is an explanatory diagram of a conventional example (No. 1)
【図６】 従来例の説明図（その２）FIG. 6 is an explanatory diagram of a conventional example (No. 2)
【図７】 従来例の説明図（その３）FIG. 7 is an explanatory diagram of a conventional example (No. 3)
【図８】 従来例の説明図（その４）FIG. 8 is an explanatory diagram of a conventional example (No. 4)
図において １ ＩＣチップ ２ パッド ３ めっきバンプ ４ ボンディングバンプ ５ ＴＡＢテープ ６ ＴＡＢリード ７ ボンディングツール ８ 実装基板 ９ 外部電極 10 カメラ 11 ボンディング機構部 12 チップ搬送ツール 13 基板固定台 In the figure 1 IC chip 2 pad 3 plating bump 4 bonding bump 5 TAB tape 6 TAB lead 7 bonding tool 8 mounting board 9 external electrode 10 camera 11 bonding mechanism section 12 chip transfer tool 13 board fixing base
Claims (3)
を接合するバンプの形成方法であって、 該ＩＣチップのパッド上に選択的にめっきバンプを形成
し、続いて該めっきバンプ上にボンディングワイヤのボ
ールからなるボンディングバンプを形成することを特徴
とするＩＣチップのバンプ形成方法。1. A method of forming a bump for bonding an IC chip on a TAB tape or a substrate, wherein a plating bump is selectively formed on a pad of the IC chip, and subsequently a bonding wire is formed on the plating bump. A method of forming bumps of an IC chip, which comprises forming bonding bumps made of balls.
を接合するバンプの形成方法であって、 該ＩＣチップのパッド上に、ボンディングワイヤのボー
ルからなる二個以上のボンディングバンプを形成するこ
とを特徴とするＩＣチップのバンプ形成方法。2. A method of forming a bump for bonding an IC chip on a TAB tape or a substrate, wherein two or more bonding bumps made of balls of a bonding wire are formed on a pad of the IC chip. Method for forming bumps on IC chip.
プの形成方法であって、 該実装基板上に形成されたボンディングワイヤのボール
からなるボンディングバンプに向かい合って、該ＩＣチ
ップのパッド上に、ボンディングワイヤのボールからな
るボンディングバンプを形成することを特徴とするＩＣ
チップのバンプ形成方法。3. A method of forming a bump for bonding an IC chip onto a mounting substrate, comprising: facing a bonding bump formed of balls of a bonding wire formed on the mounting substrate, onto a pad of the IC chip, An IC characterized by forming a bonding bump composed of a ball of a bonding wire
Chip bump formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30342994A JP3389712B2 (en) | 1994-12-07 | 1994-12-07 | IC chip bump forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30342994A JP3389712B2 (en) | 1994-12-07 | 1994-12-07 | IC chip bump forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08162491A true JPH08162491A (en) | 1996-06-21 |
| JP3389712B2 JP3389712B2 (en) | 2003-03-24 |
Family
ID=17920908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30342994A Ceased JP3389712B2 (en) | 1994-12-07 | 1994-12-07 | IC chip bump forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3389712B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7019405B2 (en) | 2002-06-03 | 2006-03-28 | Shinko Electric Industries Co., Ltd. | Terminal, semiconductor device, terminal forming method and flip chip semiconductor device manufacturing method |
-
1994
- 1994-12-07 JP JP30342994A patent/JP3389712B2/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7019405B2 (en) | 2002-06-03 | 2006-03-28 | Shinko Electric Industries Co., Ltd. | Terminal, semiconductor device, terminal forming method and flip chip semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3389712B2 (en) | 2003-03-24 |
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