JPH08162482A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08162482A
JPH08162482A JP6330065A JP33006594A JPH08162482A JP H08162482 A JPH08162482 A JP H08162482A JP 6330065 A JP6330065 A JP 6330065A JP 33006594 A JP33006594 A JP 33006594A JP H08162482 A JPH08162482 A JP H08162482A
Authority
JP
Japan
Prior art keywords
thin plate
alloy
bare chip
board
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6330065A
Other languages
Japanese (ja)
Inventor
Masao Funada
雅夫 舟田
Masaaki Araki
雅昭 荒木
Yasuo Takayama
康夫 高山
Seiya Omori
誠也 大森
Shimizu Sagawa
清水 佐川
Takehiro Niitsu
岳洋 新津
Yasushi Miyajima
靖 宮島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP6330065A priority Critical patent/JPH08162482A/en
Publication of JPH08162482A publication Critical patent/JPH08162482A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/799—Apparatus for disconnecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To obtain a semiconductor device which is easy both in manufacture and in repair by a method wherein a bare chip is mounted on a thin plate member soldered on a die bonding pad on a printed-wiring board. CONSTITUTION: A thin plate 6 is soldered on a die bonding pad 18 on a printed board 1. A bare chip 4 is bonded on this thin plate 6 using an Au-Si or Au-Sn alloy or a bonding agent 8, such as high heat conductivity epoxy region bonding agent. As this thin plate 6, a flat plate-shaped thin plate consisting of Cu alloy, such as Cu-Cr-Zr (CCZ) alloy and Cu-Sn-Ni (TAMAC-15) alloy, or a flat thin plate consisting of Fe alloy, such as Fe-Ni (42 alloy) alloy and Fe-Ni-Co-Mn-Si (Kovar) alloy, is used. As these thin plates 6 are made of alloy material, the plates 6 and can be made thin in the ranges of 0.1 to 0.15mm, the distance between the bare chip 4 on the thin plate 6 and the board 1 is never increased and the wire bonding of the bare chip 4 to the board 1 is facilitated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明はベアチップをプリント
板上にワイアボンディングし実装した半導体装置に関
し、とくにリペア容易な半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bare chip mounted on a printed board by wire bonding, and more particularly to a semiconductor device which can be easily repaired.

【０００２】[0002]

【従来の技術】従来ベアチップをリペア可能なようにプ
リント板上に実装した半導体装置には次のようなものが
ある。特開平３−２４０２５１号公報では不良半導体チ
ップ上に良品の半導体チップを重畳してダイボンディン
グすることでリペアしている。また、特開平６−９７２
２３号公報は半導体チップとプリント基板との間に薄型
基板を介してフェースダウンボンディングしたものであ
る。この薄型基板の一方の面には半導体チップのリード
端子とプリント基板の接続パッドとを接続する接続パタ
ーンを形成してある。この接続パターンに半導体チップ
をフェースダウンボンディングする。この後薄型基板の
接続パターンの形成部をＵ字状に曲折し、接続パターン
の先端の半田接合部とプリント基板とを接合する。リペ
ア時には半田接合部を溶融し、半導体チップを薄板基板
ごと取り換える。2. Description of the Related Art Conventionally, the following semiconductor devices are mounted on a printed board so that bare chips can be repaired. In JP-A-3-240251, repair is performed by superposing a good semiconductor chip on a defective semiconductor chip and die-bonding the same. In addition, JP-A-6-972
In Japanese Patent No. 23, the face down bonding is performed between a semiconductor chip and a printed board via a thin board. A connection pattern for connecting the lead terminals of the semiconductor chip and the connection pads of the printed board is formed on one surface of the thin board. A semiconductor chip is face-down bonded to this connection pattern. After that, the formation portion of the connection pattern of the thin board is bent into a U shape, and the solder joint portion at the tip of the connection pattern and the printed board are joined. During repair, the solder joint is melted and the semiconductor chip is replaced with the thin plate substrate.

【０００３】[0003]

【発明が解決しようとする課題】しかし従来の半導体装
置ではリペアを容易に行うには次のような問題があっ
た。 （１）特開平３−２４０２５１号公報のものでは、リペ
ア時に良品の半導体チップを不良品の半導体チップの上
に重畳してからワイアボンディングしているため、良品
の半導体チップのボンディングパッドと回路基板のボン
ディングパッドとの距離が大きくなってしまいワイアボ
ンディングが困難である。 （２）特開平６−９７２２３号公報のものでは、薄型基
板をＵ字状に曲げて位置合わせしてプリント基板と接続
する工程が必要となる。 本発明は上記したような問題に鑑み、製造もリペアも容
易な半導体装置を提供することを目的とする。However, the conventional semiconductor device has the following problems to facilitate the repair. (1) In Japanese Patent Laid-Open No. 3-240251, a good semiconductor chip is superposed on a defective semiconductor chip before wire-bonding at the time of repair. Therefore, the bonding pad of the good semiconductor chip and the circuit board. Therefore, the wire bonding becomes difficult because the distance from the bonding pad becomes large. (2) In the method disclosed in Japanese Patent Laid-Open No. 6-97223, a step of bending the thin substrate into a U shape, aligning it, and connecting it to the printed circuit board is required. In view of the above problems, it is an object of the present invention to provide a semiconductor device that is easy to manufacture and repair.

【０００４】[0004]

【課題を解決するための手段】そこで本発明は印刷配線
基板上のダイボンディングパッド上にベアチップを設
け、前記印刷配線基板上の配線と前記ベアチップとをワ
イアボンディングして実装した半導体装置において、印
刷配線基板上のダイボンディングパッド上に薄板状部材
をはんだ付けして設け、ベアチップを前記薄板状部材上
に実装することにより課題を解決する。Therefore, the present invention provides a semiconductor device in which a bare chip is provided on a die bonding pad on a printed wiring board, and wiring on the printed wiring board and the bare chip are mounted by wire bonding. A thin plate member is provided by soldering on a die bonding pad on a wiring board, and a bare chip is mounted on the thin plate member to solve the problem.

【０００５】[0005]

【作用】本発明によれば、印刷配線基板上のダイボンデ
ィングパッド上に薄板状部材をはんだ付けして設け、ベ
アチップを前記薄板状部材上に実装する構造としたこと
により、ベアチップを薄板状部材ごとはんだ溶融温度で
印刷配線基板から取り外すことができる。また一旦取り
外した箇所に再びベアチップを薄板状部材ごとはんだ溶
融温度で実装することができるため製造及びリペアが容
易に行える。According to the present invention, a thin plate member is provided by soldering on a die bonding pad on a printed wiring board, and a bare chip is mounted on the thin plate member. Can be removed from the printed wiring board at the solder melting temperature. In addition, since the bare chip can be mounted together with the thin plate member at the solder melting temperature once again at the location where it is once removed, manufacturing and repair can be easily performed.

【０００６】[0006]

【実施例】本発明における第１の実施例の半導体装置を
図１に示す。第１の実施例においては、プリント板
（１）上のダイボンディングパッド（１８）上に薄板
（６）がはんだ付けされ、この薄板（６）上にベアチッ
プ（４）がＡｕ−Ｓｉ，Ａｕ−Ｓｕ合金や高熱伝導性エ
ポキシ樹脂接着剤等の接着剤（８）を用いて接着され
る。この薄板（６）にはＣｕ−Ｃｒ−Ｚｒ（ＣＣＺ）や
Ｃｕ−Ｓｎ−Ｎｉ（ＴＡＭＡＣ−１５）等のＣｕ合金か
らなる平板状の薄板、Ｆｅ−Ｎｉ（４２アロイ）やＦｅ
−Ｎｉ−Ｃｏ−Ｍｎ−Ｓｉ（Ｋｏｖａｒ）等のＦｅ合金
からなる平板状の薄板が用いられる。本実施例の薄板
（６）は合金材料で作られているため、厚さを０．１〜
０．１５ｍｍと薄くでき、薄板（６）上のベアチップ
（４）とプリント板（１）との距離が大きくなることが
なくワイアボンディングが容易である。また、薄膜の大
きさはベアチップ（４）にほぼ等しく作られている。1 shows a semiconductor device according to a first embodiment of the present invention. In the first embodiment, the thin plate (6) is soldered on the die bonding pad (18) on the printed board (1), and the bare chip (4) is Au-Si, Au- on the thin plate (6). Adhesion is performed using an adhesive (8) such as a Su alloy or a high thermal conductivity epoxy resin adhesive. The thin plate (6) is a flat thin plate made of Cu alloy such as Cu-Cr-Zr (CCZ) or Cu-Sn-Ni (TAMAC-15), Fe-Ni (42 alloy) or Fe.
A flat thin plate made of an Fe alloy such as -Ni-Co-Mn-Si (Kovar) is used. Since the thin plate (6) of this embodiment is made of an alloy material, it has a thickness of 0.1 to 10.
It can be made as thin as 0.15 mm, and wire bonding is easy without increasing the distance between the bare chip (4) on the thin plate (6) and the printed board (1). The size of the thin film is made almost equal to that of the bare chip (4).

【０００７】以下、第１の実施例の製造方法を順に説明
する（図２）。まずベアチップの取付け方法を説明す
る。薄板（６）の大きさはベアチップ（４）とほぼ等し
いため、ベアチップと同じダイボンダーを用いて薄板
（６）をダイボンドステージ（１６）上に置き、その上
にディスペンサー（２０）を用いてエポキシ樹脂接着剤
（８）を塗布する（図２（ａ））。次いで、接着剤
（８）が塗布された薄板（６）上にベアチップ（４）を
位置決めし押しつけ接着する（図２（ｂ）（ｃ））。こ
の時の接着剤の厚さは２０μｍ〜５０μｍである。次い
で１２０°Ｃ〜１８０°Ｃのオーブンあるいはヒーター
ステージにより接着剤の硬化を行う。The manufacturing method of the first embodiment will be described below in sequence (FIG. 2). First, a method of mounting the bare chip will be described. Since the size of the thin plate (6) is almost the same as that of the bare chip (4), the thin plate (6) is placed on the die bond stage (16) using the same die bonder as the bare chip, and a dispenser (20) is used on the thin plate (6). An adhesive (8) is applied (FIG. 2 (a)). Then, the bare chip (4) is positioned and pressed onto the thin plate (6) coated with the adhesive (8) to be bonded (FIGS. 2B and 2C). The thickness of the adhesive at this time is 20 μm to 50 μm. Next, the adhesive is cured in an oven or a heater stage at 120 ° C to 180 ° C.

【０００８】プリント板（１）にははんだクリーム（１
７）のスクリーン印刷法やフラッシュめっき法によって
ダイボンデイングパッド（１８）上にはんだ（例えば、
３７Ｐｂ−６３Ｓｎ（溶融温度１８３°Ｃあるいは１８
Ｐｂ−７０Ｓｎ−１２Ｉｎであれば溶融温度１６２°
Ｃ、４２Ｓｎ−５８Ｂｉであれば溶融温度１３８°Ｃと
することができる。））を厚さ５０μｍないし１００μ
ｍに塗布しておく（図２（ｄ））。このあと、ベアチッ
プ（４）が固着された薄板（６）をこのはんだクリーム
（１７）の上にダイボンダーを用いて位置合わせして載
せた（図２（ｅ））。このままリフロー炉（数秒間から
１０数秒間２３０°Ｃ〜２５０°Ｃに維持される）を通
して、薄板（６）をプリント板（１）に合金接着する。
このときのはんだ（７）の厚さは３０μｍないし８０μ
ｍとなった。次にベアチップとプリント板とをワイアボ
ンデイングする。このようにしてベアチップをプリント
板に実装することができる。図２ではベアチップ（４）
を薄板（６）上に接着してからプリント基板（１）上に
はんだ付けしたが、プリント基板（１）上に薄板（６）
をはんだ付けし、この薄板（６）上にベアチップ（４）
を接着してもよい。On the printed board (1), solder cream (1
Solder (eg, by soldering) on the die bonding pad (18) by the screen printing method or flash plating method of 7)
37Pb-63Sn (melting temperature 183 ° C or 18
If it is Pb-70Sn-12In, the melting temperature is 162 °.
With C and 42Sn-58Bi, the melting temperature can be set to 138 ° C. )) With a thickness of 50 μm to 100 μ
m (Fig. 2 (d)). Then, the thin plate (6) to which the bare chip (4) was fixed was positioned and mounted on the solder cream (17) using a die bonder (FIG. 2 (e)). The thin plate (6) is alloy-bonded to the printed board (1) through a reflow furnace (maintained at 230 ° C to 250 ° C for several seconds to ten and several seconds) as it is.
At this time, the thickness of the solder (7) is 30 μm to 80 μ
It became m. Next, the bare chip and the printed board are wire bonded. In this way, the bare chip can be mounted on the printed board. Bare chip (4) in Figure 2
Was adhered onto the thin plate (6) and then soldered onto the printed circuit board (1), but the thin plate (6) was attached onto the printed circuit board (1).
Solder and bare chip (4) on this thin plate (6)
May be adhered.

【０００９】次にプリント板（１）から不良ベアチップ
（４）を取り外す場合を図３を用いて説明する。ベアチ
ップ（４）を交換するに際し、ピンセットや針でボンデ
ィングワイアをプリント板（１）基板から切断し、少し
持ち上げる（図３（ａ））。次に、ヒーターステージ１
０上で加熱すると１８３°Ｃ程度ではんだが溶融する
（図３（ｂ））。そして真空取り外し治具（１２）や普
通のピンセットで薄板（６）とそれに接着されたベアチ
ップ（４）を一緒に取り外す（図３（ｃ）（ｄ））。こ
の後良品のベアチップに交換するには前記取付け方法と
同じである。Next, the case of removing the defective bare chip (4) from the printed board (1) will be described with reference to FIG. When replacing the bare chip (4), the bonding wire is cut from the substrate of the printed board (1) with tweezers or a needle and slightly lifted (FIG. 3 (a)). Next, heater stage 1
When heated at 0 ° C., the solder melts at about 183 ° C. (FIG. 3 (b)). Then, the thin plate (6) and the bare chip (4) adhered to the thin plate (6) are removed together with a vacuum removal jig (12) or ordinary tweezers (FIGS. 3C and 3D). After that, the method of replacing with a non-defective bare chip is the same as the above-mentioned mounting method.

【００１０】本発明の第２の実施例の半導体装置の斜視
図を図４に示す。第１の実施例と同様な合金材料を用い
両端を上方へ折り曲げた薄板（４９）として放熱効果を
上げるものである。薄板（４９）はワイアボンディング
の際に障害とならない範囲で曲げる長さを適当に選択す
ればよい。またベアチップ（４４）と薄板（４９）の両
端の折り曲げ部分間での距離は、ベアチップ（４４）を
真空吸着する治具が当たらない距離だけ離してある。本
実施例の場合は０．１５ｍｍ以上あければ十分である。FIG. 4 is a perspective view of the semiconductor device according to the second embodiment of the present invention. A thin plate (49) made of an alloy material similar to that of the first embodiment and having both ends bent upward is used to enhance the heat dissipation effect. The thin plate (49) may have a bending length appropriately selected within a range that does not hinder the wire bonding. Further, the distance between the bent portions at both ends of the bare chip (44) and the thin plate (49) is set such that the jig for vacuum-adsorbing the bare chip (44) does not hit. In the case of the present embodiment, it is sufficient to open it by 0.15 mm or more.

【００１１】本発明の第１および、第２の実施例は薄板
の材料に合金材料を用いたが、一方の面にはんだ付け可
能な金属膜を形成した液晶ポリマーやセラミック等の絶
縁材料からなる平板状の薄板を用いてもよい。この場合
裏面での導通を必要としないベアチップを用いれば、他
方の面は絶縁性のままでもよい。また、イメージセンサ
やサーマルヘッドの様にプリント板上にベアチップを一
次元に複数個配列し、配列方向の両側でワイアボンディ
ングしたものにも適用可能である。In the first and second embodiments of the present invention, an alloy material is used as the material of the thin plate, but it is made of an insulating material such as liquid crystal polymer or ceramic having a solderable metal film formed on one surface. A flat thin plate may be used. In this case, if a bare chip that does not require conduction on the back surface is used, the other surface may remain insulating. Further, it is also applicable to an image sensor or a thermal head in which a plurality of bare chips are one-dimensionally arranged on a printed board and wire-bonded on both sides in the arrangement direction.

【００１２】[0012]

【発明の効果】本発明によれば、通常のボンディング工
程のまま製造もリペアも容易となる。According to the present invention, manufacturing and repairing can be facilitated with the normal bonding process.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の半導体装置の正面図で
ある。FIG. 1 is a front view of a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施例のベアチップ取り付け工
程図である。FIG. 2 is a bare-chip mounting process diagram of the first embodiment of the present invention.

【図３】本発明の第１の実施例のベアチップ取り外し工
程図である。FIG. 3 is a bare-chip removing process diagram of the first embodiment of the present invention.

【図４】本発明の第２の実施例の半導体装置の斜視図で
ある。FIG. 4 is a perspective view of a semiconductor device according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１，４１…プリント板、４，４４…ベアチップ、３…支
持基板、５…ボンディングワイア、６…薄板、７，４７
…はんだ、８…接着剤、４９…放熱フィンを兼ねた薄
板、１０…ヒーターステージ、１２…ダイ取り外し治
具、１３…真空、１４…この方向に押す、１６…ダイボ
ンディングステージ、１７…半田クリーム、１８，５８
…ダイボンドパッド、１９，５９…配線（ワイアボンデ
ィングパッド）1, 41 ... Printed board, 4, 44 ... Bare chip, 3 ... Support substrate, 5 ... Bonding wire, 6 ... Thin plate, 7, 47
... Solder, 8 ... Adhesive agent, 49 ... Sheet plate also serving as a radiation fin, 10 ... Heater stage, 12 ... Die removal jig, 13 ... Vacuum, 14 ... Press in this direction, 16 ... Die bonding stage, 17 ... Solder cream , 18, 58
… Die bond pads, 19, 59… Wiring (wire bonding pads)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大森 誠也 神奈川県海老名市本郷2274番地 富士ゼロ ックス株式会社内 (72)発明者 佐川 清水 神奈川県海老名市本郷2274番地 富士ゼロ ックス株式会社内 (72)発明者 新津 岳洋 神奈川県海老名市本郷2274番地 富士ゼロ ックス株式会社内 (72)発明者 宮島 靖 神奈川県海老名市本郷2274番地 富士ゼロ ックス株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiya Omori 2274 Hongo, Ebina City, Kanagawa Prefecture, Fuji Xerox Co., Ltd. (72) Inventor Sagawa Shimizu, 2274 Hongo, Ebina City, Kanagawa Prefecture, Fuji Xerox Co., Ltd. (72) Inventor Takehiro Niitsu 2274 Hongo, Ebina City, Kanagawa Prefecture, Fuji Xerox Co., Ltd. (72) Inventor, Yasushi Miyajima 2274, Hongo, Ebina City, Kanagawa Prefecture, Fuji Xerox Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 印刷配線基板上のダイボンディングパッ
ド上にベアチップを設け、前記印刷配線基板上の配線と
前記ベアチップとをワイアボンディングして実装した半
導体装置において、 前記印刷配線基板上のダイボンディングパッド上に薄板
状部材をはんだ付けして設け、前記ベアチップを前記薄
板状部材上に実装することを特徴とする半導体装置。1. A semiconductor device in which a bare chip is provided on a die bonding pad on a printed wiring board, and the wiring on the printed wiring board and the bare chip are mounted by wire bonding, and the die bonding pad on the printed wiring board is provided. A semiconductor device, wherein a thin plate member is provided on the thin plate member by soldering, and the bare chip is mounted on the thin plate member.
JP6330065A 1994-12-06 1994-12-06 Semiconductor device Pending JPH08162482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6330065A JPH08162482A (en) 1994-12-06 1994-12-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6330065A JPH08162482A (en) 1994-12-06 1994-12-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08162482A true JPH08162482A (en) 1996-06-21

Family

ID=18228393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6330065A Pending JPH08162482A (en) 1994-12-06 1994-12-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08162482A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100684240B1 (en) * 2005-01-07 2007-02-22 가부시끼가이샤 르네사스 테크놀로지 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100684240B1 (en) * 2005-01-07 2007-02-22 가부시끼가이샤 르네사스 테크놀로지 Semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP3880775B2 (en) Mounting electronic components on a circuit board
JPH06103703B2 (en) Soldering method
JPS63119552A (en) Lsi chip
JP2004193334A (en) Bump-forming sheet, and its manufacturing method
EP0998175A1 (en) Method for soldering Dpak-type electronic components to circuit boards
JP3269390B2 (en) Semiconductor device
JPH07106334A (en) Method for bonding optical semiconductor device to optical substrate
JPH08236578A (en) Flip chip mounting method of semiconductor element and bonding agent used for this method
JPH08162482A (en) Semiconductor device
JP3385943B2 (en) How to mount electronic components with gold bumps
JP2570626B2 (en) Board connection structure and connection method
JP2003197681A (en) Electronic apparatus
JPH1187906A (en) Semiconductor device and packaging method therefor
JP2001210676A (en) Semiconductor device and manufacturing method
JPH0974149A (en) Small package and manufacture
JPH0236556A (en) Pin grid array and mounting of semiconductor element
JPH08111437A (en) Mounting method of semiconductor device
JP2526666B2 (en) How to attach the film to the lead frame
JP2000100863A (en) Forming method for solder bump
JPH08264910A (en) Manufacture of printed wiring board with heat sink and method for mounting high-power component on the board
JPH06244522A (en) Package module board
JPH07201894A (en) Manufacture of electronic parts mounting device
JP3445687B2 (en) Mounting method of semiconductor chip
JP3598058B2 (en) Circuit board
JP3548671B2 (en) Semiconductor device and manufacturing method thereof