JPH08161190A - Emulation processor and emulator mounting the processor - Google Patents

Abstract

PURPOSE: To provide an emulation processor constituting an emulator capable of quickly and easily controlling the emulation processor and attaining emulation without increasing the number of signal line between the emulation processor and the emulator and without increasing excess load to an external circuit and to provide also the emulator mounting the emulation processor. CONSTITUTION: The emulation processor capable of emulating a microprocessor is provided with a single chip microcomputer part constituted of a CPU, a DTC, a ROM, a RAM, a timer, an SCI, an A/D IOPs 1 to 11, an interruption controller, a BSC, a CPG, etc., as function blocks, and an emulation processor exclusive block having an emulation-only control register for executing brake control, bus control, module selecting control, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulator, which is a developing device for a microcomputer and a microcomputer application system, and is effective when applied to, for example, a microcomputer emulation processor and an emulator equipped with this emulation processor. Related technology.

[0002]

2. Description of the Related Art For example, a microcomputer development device called a so-called in-circuit emulator is used to develop an application system using a single-chip microcomputer. This microcomputer development device is connected between a system development device such as a so-called personal computer and an application system (user system) under development, and is a single-chip microcomputer (target microcomputer) to be installed in the application system. It has a function as a debugger while substituting for the function, and supports the development of software or an application system.

In this microcomputer development device,
A function that includes a single-chip microcomputer in an evaluation emulation processor called an evaluation chip that corresponds to the single-chip microcomputer, and that outputs the internal state of the microcomputer and controls the operation of the microcomputer. By adding the function of, the development of the microcomputer development device is facilitated.

For such a microcomputer development device or in-circuit emulator, for example, "LSI" issued by Ohmsha, Ltd. on November 30, 1984 is issued.
Handbook ”P562 and P563,
Further, the emulation processor is well known from, for example, Japanese Patent Laid-Open No. 63-106840, so detailed description thereof will be omitted.

As a function dedicated to the emulation processor, there is a function to stop the CPU when the CPU accesses a predetermined address and transfer control to the emulator side (break), and a program dedicated to the emulation at the time of the break. And to monitor and change the user's memory. What to do at break is, for example, Japanese Patent Application No. 4-10.
No. 5779.

[0006]

In the emulation processor as described above, however, it is difficult to design an external circuit for controlling the emulation processor due to the speeding up of the microcomputer. For example, when resetting the emulation processor, the emulation processor executes or changes the user program depending on whether the reset request is due to a factor on the user side or a factor on the emulator side.

Although not a publicly known technique, such a change is performed by changing a vector (start address) read by the emulation processor by an external circuit outside the emulation processor. When the access time is shortened by the speedup of the microcomputer, the time allowed for such vector change is also shortened.

An emulation memory is arranged in the address space of the CPU, which overlaps the user memory. It is necessary to determine whether to access the emulation memory or the user memory with respect to the address output from the CPU, and if either the emulation bus or the user bus is provided, either bus must be enabled. If the access time is shortened by the speedup of the microcomputer, the time allowed for such address determination and bus control will be shortened.

In addition, C depending on the access state of the CPU
A break interrupt is requested to interrupt the execution of the PU program and transfer control to the emulation side (break). However, it is judged that the access status of the CPU is judged outside the emulation processor and the break interrupt is requested. It is difficult to break the CPU in a desired instruction execution state. For example, a break occurs when several instructions are executed in excess of the desired instruction execution state. It becomes difficult to make a break immediately after executing a desired instruction such as a single step operation.

Further, the number of signals that can be input / output between the emulation processor and the emulator is limited by the number of terminals of the emulation processor as the semiconductor integrated circuit device. For this reason, it is not always possible to sufficiently output, for example, a signal indicating the instruction execution state of the CPU inside the emulation processor to the emulator. Further, it is not always possible to input a sufficient number of control signals to the emulation processor of the emulator.

Further, the increase in the emulation signal causes an increase in the package size of the emulation processor. Further, it becomes difficult to increase the size of the emulator itself and evaluate the application system in an actual operating state, for example.

Therefore, an object of the present invention is to reduce the load on the external circuit without increasing the number of signals between the emulation processor and the emulator (without increasing the size of the emulator and enabling evaluation even in the mounted state). An object of the present invention is to provide an emulation processor which constitutes an emulator capable of controlling the emulation processor at high speed and easily without increasing the number and emulating it, and an emulator equipped with the emulation processor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the emulation processor of the present invention is applied to a processor capable of emulating a microcomputer. The emulation program operates in a break mode which is the first mode and a user to be emulated. It has a second mode in which the program operates, that is, a user mode, and has a break reset and a user reset corresponding to each mode, and inputs whether to immediately transit to the break mode or to be in the user mode after the reset. It is selectable by the state of the terminal.

The address space of the microcomputer to be emulated is divided, and in the break mode, a memory selection register (MEMCR) is used as a means for designating whether to access the emulation memory or the user memory for each area. Is to have.

Further, if a break condition is set inside the emulation, and especially if a control bit (SSTP) for requesting single step processing is provided, each instruction of the user program when the bit is in a predetermined state. To automatically request a break interrupt, and when it has a break interrupt control bit (BIEA, B), it enables a PC break, and when it has a multiple break interrupt control bit (BMBE), it can multiplex. It is designed to prohibit interrupts.

The emulator of the present invention is equipped with the emulation processor. When the reset signal of the user system is active, user reset is selected, and the reset signal of the emulator is active. In this case, it has a break reset control circuit as a means to bring the break reset into a selected state, and further reads or writes the memory of the user system in a bus cycle specified by the microcomputer, and emulates it in a bus cycle for emulation. It is possible to read or write the rental memory of the system.

[0019]

According to the emulation processor and the emulator equipped with the emulation processor described above, it is possible to use a wealth of information inside the emulation processor by incorporating into the emulation processor what was controlled outside the emulation processor. In addition, it is not affected by the delay of the signal from the emulation processor to the emulator and the delay of the signal from the emulator to the emulation processor. The emulation processor can be controlled at high speed.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a microcomputer as an emulation target of an emulation processor according to an embodiment of the present invention, FIG. 2 is a block diagram showing an emulation processor according to the present embodiment, and FIGS. FIG. 20 is a detailed block diagram, timing diagram, or operation flowchart of the emulation processor. FIG. 21 is a block diagram of an emulator equipped with the emulation processor according to the present embodiment.
Is an operation flowchart of the emulator.

First, the configuration of a microcomputer to be emulated by the emulation processor of this embodiment will be described with reference to FIG.

The microcomputer in this embodiment is, for example, a single-chip microcomputer, and has a central processing unit CPU, a data transfer controller DTC, a read only memory ROM, a random access memory RAM, a timer, a serial communication interface SCI, and an A / D conversion. A / D, input / output ports IOP1 to IOP1, an interrupt controller, a bus controller BSC, and a clock oscillator CPG, which are functional blocks (or modules), and these functional blocks are interconnected by an internal bus.

The bus controller includes a module select unit MS that determines the contents of the address. Although not shown, the timer includes blocks for 5 channels and the SCI includes blocks for 3 channels.

The internal bus includes a read signal / write signal in addition to an address bus / data bus, and may further include a bus size signal or a system clock. The internal address bus has IAB and PAB. The internal data bus has IDB and PDB. IAB and PA
B, IDB and PDB are interfaced by a bus controller.

The internal data buses IDB and PDB have a 16-bit structure. The CPU instruction is in 16-bit units. The CPU address space is 16 MB. P
AB and PDB are bus controller, timer, SCI,
It is connected to the A / D converter, interrupt controller, and IOP1-11. The interrupt controller inputs the interrupt signals output from the timer, SCI, and the input / output port, and the CPU and D
An interrupt request signal and a vector number are output to TC.

The input / output port is also used as an external bus signal and an input / output signal of the input / output circuit. IOP1-3 are address bus outputs, IOP4, 5 are data bus input / output, IOP
OP6 and 7 are also used as bus control signal input / output signals. External addresses and external data are transferred to IAB and IAB via buffer circuits included in these input / output ports, respectively.
It is connected to DB.

PAB and PDB are used to read / write the registers of the input / output ports and have no direct relationship with the external bus. Bus control signal output is chip select,
There are address strobe, high / low data strobe, read strobe, write strobe, column address strobe, bus acknowledge signal and the like. Bus control input signals include wait signals and bus request signals. These input / output signals are not shown. The expansion of the external bus is selected depending on the operation mode and the functions of these input / output ports are also selected.

IOP8 is a timer input / output and IOP9
Is SCI input / output, IOP10 is analog input, IOP1
1 is also used as an external interrupt request IRQ input. Input / output signals of the timer, SCI, A / D converter and IOP8 to IOP10 are not shown. Besides, power supply terminal Vc
c, Vss, analog power supply terminals AVcc, AVss, reset input terminal RES, standby input terminal STBY,
Interrupt input terminal NMI, clock input terminals EXTAL, X
There are input terminals such as TAL and operation mode input terminals MD0, MD1, MD2.

Next, the configuration of the emulation processor will be described with reference to the block diagram of FIG.

The emulation processor comprises the emulation processor dedicated block including the microcomputer portion and a buffer circuit (not shown).
Formed on one semiconductor substrate. Signals and the like which are not directly related to the present invention in the microcomputer portion are omitted. The I / O includes a timer, SCI, A / D and IOP. The BUF is a buffer portion of the address bus / data bus / bus control signals included in the IOPs 1 to 7.

The emulation processor has a user interface for transmitting and receiving signals to and from the application system, and an emulation interface for transmitting and receiving signals to and from the microcomputer development device.

The emulation interface has a break interrupt signal BRK, an emulator interrupt signal EMLIRQ, and an emulator wait signal EML as input signals.
WAIT is present, and break acknowledge signal BRKAK and trigger output signals TOA and TOB are present as output signals. In addition, an address bus, a data bus, a read signal, a write signal, etc. are included.

The emulation processor dedicated block has an emulation dedicated control register and performs break control, bus control, module selection control and the like. For example, as described in Japanese Patent Application Laid-Open No. 3-271843 or Japanese Patent Application No. 4-316068, one emulation processor is used to specify prohibition of a function built in the emulation processor or change of operation. It is possible to emulate multiple microcomputers.

The module selection control is designated by the module selection register MSELR, the microcomputer to be emulated is selected by the setting of the module selection register, and prohibition of the function built in the emulation processor and change of the operation are designated. The control signal to be supplied is supplied to the module select circuit included in the bus controller BSC and other microcomputer parts.

For example, the number of usable channels of a timer or SCI is designated, or the number of valid IOPs is designated. Also, the capacity of the built-in ROM and RAM is designated. For the prohibited module, operations such as read / write are suppressed by fixing the module selection signal to the inactive state.

The bus control is performed by the memory control register MEMC.
R, wait control register EWTCR, window control bits WD1, 0, and break acknowledge signal BRK
Designated by AK, the bus controller is instructed to control the user bus and the emulation bus and to enable / disable the wait request from the emulation side.
The bus controller performs bus control according to the address determination result of the module select circuit.

Break control is performed by a BRK interrupt signal, a break control register BRKCR, a break address register BAR, and a break address mask register BAMR. A break request and a single step break request are made according to information such as the register and address. To the CPU.

The EMLWAIT signal is provided to the bus controller and reset control circuit. Although the reset control circuit is not particularly limited, it outputs a user reset RST signal and a break reset BRST signal, the microcomputer reset section is supplied with the user reset RST, and the emulation processor dedicated block is supplied with the user reset RST and break reset BRST signals. Is supplied.

The emulator-only interrupt control is EMLIR
Q signal and emulator interrupt control register IRQCR
Controlled by the CPU and requests the CPU to interrupt through the interrupt controller of the microcomputer part.

Next, the configuration of the emulator dedicated register included in the emulator dedicated block will be described with reference to the register configuration diagrams of FIGS.

The initial reset value differs between user reset and break reset. It is not initialized by the user reset and is held at the previous value. At break reset, all the dedicated emulation registers are initialized.

(1). Module selection register MSELR is an 8-bit register, and specifies DTC permission / prohibition, timer channel count, SCI channel count, package (number of input / output ports), ROM capacity, RAM capacity. I do.

Read / write is possible only in break mode. Such designation method and control method are described in the above-mentioned Japanese Patent Laid-Open No.
Since it is described in Japanese Patent No. 271834 or Japanese Patent Application No. 4-316068, detailed description will be omitted.

The module selection register is initialized by the BRES signal. Since it is retained by the user reset, once the emulator is started to operate, once it is set, it is not necessary to reset it unless the target microcomputer is changed.

(2). The memory selection register MEMCR is 16
A register having a bit configuration corresponds to a 16-divided address space, and specifies whether to allocate a user memory or an emulation memory (rental memory) to each area.

(3). Wait control register EWTCR is 1
This is a 6-bit register that corresponds to the address space divided into 16 in the same manner as above, and the EMLW is set in each area.
Specify whether to allow or prohibit AIT. Generally, the area to which the emulation memory (rental memory) is allocated permits EMLWAIT so that a sufficient access time can be secured.

The bus control register and wait control register are initialized by the BRES signal. Since it is retained at user reset, once it is set after the emulator starts operating, there is no need to reset it unless the target memory allocation is changed. Read / write is possible only in break mode.

(4). Emulator dedicated interrupt control register I
The RQCR is an 8-bit register. The emulator interrupt request flag IRQF is an emulator exclusive interrupt E.
It is set to "1" when a predetermined input occurs at the IRQ terminal, for example, when a rising edge occurs.
After reading the state of "1" and writing "0", "0"
Will be cleared.

The emulator interrupt permission bit IRQE is
Allow emulator-only interrupts. IRQF and IR
When both QEs are set to "1", an emulator dedicated interrupt is requested. Emulator-specific interrupts are different from user interrupts, and do not enter break mode even if they are accepted. It is treated the same as an interrupt request from the user side. Such a register can be read / written regardless of the user mode or the break mode.

The emulator interrupt control register is
Read / write is possible regardless of the user mode / break mode. It is suitable for the interrupt handler to check the task status and the like by inserting this emulator-dedicated interrupt while the OS debugger installed in the emulator is executing the user program. Since the OS operates in the user mode, it is convenient to read / write the emulator interrupt control register in the user mode. Therefore, the resources of the microcomputer are not used.

Corresponding to the fact that the OS is also initialized by the user reset, the emulator interrupt control register is also set to U.
Initialized by RES. The OS is described in "HI8-3X" issued by Hitachi, Ltd. in August 1991.

(5). Break control register BRKCR is 1
This is a 6-bit register. Window control bits WD0,1 allow access to the user bus during break mode. When the WD0 bit is set to "1", the WD1 bit is "1" during read data access.
When set to, the user bus is accessed during write data access. Ignored in user mode.

In the break mode, the access state is set to 3 regardless of the user's designation, and address multiplexing for the DRAM interface is not performed. At this time, if the WD0 and WD1 bits are set to "1", the access is performed as specified by the user. It is suitable to read and display the user memory in the break mode by a memory command of the emulator or the like, or to write the specified value to the user memory.

The address multiplex for accessing the DRAM is "H8 / 3" issued by Hitachi, Ltd. in March, 1993.
003 Hardware Manual ”p155-p194
Etc. For memory commands, please refer to “H8 / 300” issued by Hitachi, Ltd. in March 1994.
H series emulator E7000 user's manual ”p12-56 to p12-57.

The window control bits are initialized with URES. The single step bit SSTP internally requests a BRK interrupt after executing one instruction of the user program. That is, a single step BRK interrupt is required when the SSTP bit is set to "1" and BRKAK is inactive. However, after executing the RTB instruction, the single step BRK interrupt request is ignored.

The SSTP bit is suitable for debugging because it does not affect the internal state of the CPU and is treated as a resource dedicated to the emulator. For single step, published by Hitachi, Ltd. in March 1994, “H8 / 300
H series emulator E7000 user's manual ”p12-76 to p12-78.

The break interrupt enable bit BMBE is always initialized to the disabled state in the user mode. As a result, it is possible to prohibit the multiple exception handling of the break at the transition from the user mode to the break mode. In the multiple exception processing, there is a conflict between a BRK instruction and a BRK interrupt, for example. The BRK instruction is arranged, for example, next to the last instruction of the user program.

When the execution of the BRK instruction after the end of the user program and the break condition are satisfied and the BRK interrupt is requested, if the BRK interrupt is executed after the execution of the BRK instruction, that is, after the break mode transition, If the dedicated stack memory is built-in, the contents that were once stacked may be destroyed by the second exception handling. This can be avoided by disabling the multiple exception handling of the break at the transition from the user mode to the break mode by the break interrupt enable bit.

Since the BRK instruction is not used after the break mode transition, the BRK interrupt can be used even in the break mode by setting the break interrupt enable bit thereafter.

The trigger output permission bit TOE permits the trigger output to the trigger output terminals BTOA and B when the break condition is satisfied. Break condition A
When the break condition B is satisfied, a 1-state high-level pulse is output when the break condition B is satisfied.

By observing such a terminal, the time from the first desired step to the second desired step of the program can be easily measured. Set the address of the first desired step of the program to BARA and the address of the second desired step to BARB, and set BIEA, B
Clear the IEB bit to "0", select the instruction execution, execute the program with the TOE bit set to "1", and output one high level from the BTOA pin to the BTOB pin for one state. The time until the high level of is output can be measured. Alternatively, the number of times the program is executed can be measured. Based on this result, a break can be requested by the BRK terminal.

Break interrupt A, B enable bit BIEA,
B permits the break request according to break conditions A and B. The break condition is judged even in the disabled state, and the BTO
Pulse output from the A and B terminals can be performed.

Condition selection bits CSA1,0 and CSB
1 and 0 set break conditions. You can select from instruction execution, read access, write access, read or write access. For example, when the execution of an instruction is selected, the CPU fetches the instruction at the address specified by BAR and BAMR, and when the instruction is executed, a break is requested and the break is made after the execution of the instruction. Regarding the break, published by Hitachi, Ltd. in March 1994, "H
8 / 300H series emulator E7000 user's manual "p12-56 to p12-57. Such a register can be read / written only in break mode.

(6). Address Register BAR / Address Mask Register BAMR is a 24-bit register corresponding to the address space of the CPU. There are two channels, A and B.

The address register specifies an address.
Of these bits, the bit whose corresponding bit in the address mask register is set to "1" is ignored. The designated address is compared with the address output by the CPU to determine whether or not they match. The determination is (CA23 · AR23 + ¬CA23 · ¬AR23 +
AMR23) ···· (CAn · ARn + ¬CAn · ¬A
Rn + AMRn) ... (CA0 ・ AR0 + ¬CA0 ・
AR0 + AMR0). ¬ indicates logical inversion. Note that CA23-0 is the bit 23 output by the CPU.
It is −0.

(7). The emulator stack memory register EMLSTKR is used as a stack area at break. A capacity corresponding to one exception processing stack of the CPU, for example, 4 bytes is provided. For example, C
One byte of the condition code register CCR of the PU and three bytes of the program counter PC. For such a stack, see "H8 / 3003 Hardware Manual" p79, published by Hitachi, Ltd. in March 1993.
~ P88 and the like.

At the time of a break, the stack pointer SP of the CPU is ignored and stacking is always performed in the emulator stack memory. The break interrupt enable bit prevents multiple breaks from destroying the emulation stack memory. The initial reset value is not specified, but is indefinite.

Next, the address space will be described with reference to the address map of FIG.

The address space of the CPU is 16 Mbytes, which is divided into 128 kbytes 8 areas, 1 Mbytes 1 area, and 2 Mbytes 7 areas, and the attribute of each area is designated by each bit of MEMCR and EWTCR. . The area that overlaps with the internal ROM, internal RAM, and internal I / O register is the internal ROM, internal RAM,
And the specification of the internal I / O register has priority, and the above control bits are ignored.

The bus control designation register controls the bus controller. Specify the area of emulation memory. This is valid in user mode. It is convenient to be able to subdivide an area that is continuous with the built-in ROM and often becomes a program area and set up a rental memory for the program.

It is convenient if the other area is set to 2 Mbytes each and can be shared with the bus control setting on the user side.
Such bus control on the user side is described in "H8 / 3003 Hardware Manual" p121 to p154 issued by Hitachi, Ltd. in March 1993.

In the break mode, access is basically made using the emulation bus. The window bits can be used to access the user memory when the emulator monitors or modifies the user memory. This applies only to data access for the purpose of monitoring or changing the user memory.

Next, the access method will be described with reference to the state diagrams of FIGS.

In the user mode, when the corresponding MEMCR is cleared to "0", the bus cycle is designated by the bus controller of the microcomputer, for example. When accessing the external memory, the strobe signal on the user side becomes valid. The sequence output indicates that the strobe signal according to the designation of the microcomputer is output. The WAIT terminal on the user side is also enabled according to the designation of the microcomputer. Furthermore, EW
The TCR specifies whether EMLWAIT is allowed or prohibited.

When the external memory is accessed in the user mode, the bus cycle designated by the microcomputer is invalid and becomes the emulation bus cycle when the corresponding MEMCR is set to "1". Read / write is performed via the emulation bus. The number of basic bus states is three. Strobe signal on user side is inactive (fixed to high level)
And the WAIT terminal on the user side is ignored. The strobe signals on the user side are the read signal RD and the write signal H.
WR, LWR, column address strobe CAS, etc. are included. Same as above by EWTCR by EMLWAI
It is specified whether T is allowed or prohibited.

That is, even in the user mode, for the area in which the corresponding MEMCR is set to "1",
Memory on the emulator side can be read / written. Among the memories on the emulator side, the corresponding MEMCR may be set to “1” in advance for the address where the memory (rental memory) which the user is permitted to use exists. If access is not possible without inserting a weight, EWTCR will be used for EMLW.
Allow AIT.

In the break mode, the bus cycle designated by the microcomputer is basically invalid and becomes a bus cycle for emulation. Read / write is performed via the emulation bus. The number of basic bus states is three. EMLWAIT is allowed. The strobe signal on the user side is deactivated, and the WAIT terminal on the user side is ignored.

In the break mode, when the data access designated by the WD1,0 bits occurs, the bus cycle designated by the microcomputer is started. If the external address is accessed, the strobe signal on the user side becomes valid. The WAIT terminal on the user side is also enabled according to the designation of the microcomputer.

For example, the conditions for a bus cycle for emulation are: (ROM + RAM + IO). (BR
KAK ・ (PF + DRD ・ ¬WD0 + DWR ・ ¬WD
1) + ·· BRKAK · MCi). MCi
Indicates the bit of MEMCR corresponding to the selected address. PF for instruction read, DRD for data read, DW
R indicates a data write. ¬ indicates logical inversion.

Next, the bus configuration of the emulation processor will be described with reference to the block diagram of FIG.

The bus controller includes a P-BUF for controlling the bus composed of PAB / PDB and a bus control register. The bus control register is, for example, Japanese Patent Application No. 4-1379.
56. When the emulation bus cycle is selected, the contents of the bus control register are ignored. The emulation interface includes EMLBUF that controls the emulation bus.

The MS inputs the start signal and IAB output from the CPU or DTC, and the bus control register, MEMC
The access destination and access method are determined by the R / EWTCR registers and the WD1,0 bits, and the P-BU
One of the F, user BUF, and EMLBUF buffers is activated.

Even if the P-BUF and the user BUF are activated, the EMLBUF is activated for output. P-BUF,
When the user BUF and EMLBUF are activated, the address bus and various strobe signals are output at a predetermined timing to input / output the data bus. When each buffer finishes the bus cycle, it outputs a termination signal to the MS. MS is CPU
Alternatively, an end signal is output to DTC. CPU or DT
C starts the next bus cycle.

The bus control of each buffer and the bus control register are described in, for example, Japanese Patent Application No. 4-13795.
No. 6 is described.

Next, an example of bus timing will be described with reference to the timing chart of FIG. This is an example of reading an external address specified in the 2-state access space by the bus control register in the user mode.

If the MC bit is cleared to "0" and the bus cycle specified by the microcomputer is valid, access is made in two states and the strobe signal A on the user side is accessed.
S, RD, etc. output predetermined data to read data from the user data bus. The emulator strobe signal is valid, and the read data of the user data bus is output to the emulation data bus.

When the MC bit is set to "1" and the emulation bus cycle is performed, the basic bus cycle is set to 3 states. If the WC bit is set to "1", a wait is requested by EMLWAIT, and, for example, a 1-state wait state is inserted to make 4-state access. The strobe signal on the user side is fixed to the inactive state, and the user data bus is set to the high impedance state. The emulator strobe signal is valid and reads data from the emulation data bus.

Next, the break reset timing will be described with reference to the timing chart of FIG.

When the EMLWAIT signal is active, R
When the ES signal becomes active, a break reset is performed,
BRK before the CPU executes the reset exception handling
The AK signal is activated. When the BRKAK signal is in the active state, the CPU reads the vector (start address) and then fetches the instruction. Since the BRKAK signal is active, the emulation memory is selected for vector and instruction fetch. Therefore, an arbitrary program on the emulator side can be executed.

All memory accesses are 3-state accesses, and wait including EMLWAIT is permitted. The BRKAK signal is activated and the user side strobe signal is fixed to the inactive state.

Next, the user reset timing will be described with reference to the timing chart of FIG.

When the EMLWAIT signal is inactive,
When the RES signal becomes active, the user is reset,
The CPU executes the reset exception processing while the BRKAK signal is in the inactive state. When the BRKAK signal is inactive, the CPU reads a vector (start address) and then fetches an instruction. BRKA
Since the K signal is inactive, the user memory is selected for vector and instruction fetch.

The memory access is an access according to the designation of the user, and although it is not particularly limited, in FIG.
It is assumed that the vector and the first instruction exist in the built-in ROM, and access is made in one state, and the wait including EMLWAIT is prohibited. When the vector or the first instruction exists in the external memory, the user side strobe signal becomes a predetermined output state.

An emulation processor having two types of reset is described in Japanese Patent Application No. 4-316068. This is only considered for the initialization of the emulation dedicated register and the change of the number of bus states. In this example, the emulation processor has a common user bus and emulation bus. As the emulation dedicated register, only a register designating a microcomputer to be emulated is being studied.

In the present invention, the BRKAK signal is activated or deactivated in response to two types of resets to facilitate control even if the user bus and the emulation bus are independent. it can. It is possible to save the trouble of transitioning to the break mode after reset.

Further, not only the register designating the microcomputer, but also the registers relating to the entire emulator system, such as MEMCR and EWTCR, are held by the user reset, so that the time and effort of re-setting by software can be omitted. .

Next, the break reset control circuit will be described with reference to the block diagram of FIG.

EMLWAIT is requested by the bus controller as a wait request signal and used for reset control via three stages of clocked buffers or flip-flops.

Further, the reset signal RES generates an internal reset signal RST via a clocked buffer or three stages of flip-flops. In addition, the internal reset signal R
ST and clocked buffer or flip-flop 3
The EMLWAIT signal through the stage is input to the AND circuit, and the inversion of this output and the signal through the clocked buffer or two stages of flip-flops are input to the AND circuit, and the output is BRST. Signaled.

Therefore, depending on the state of the EMLWAIT # signal when the RES # terminal transits to the inactive state, the BRS
It is set whether or not the T signal is activated. B
The RST signal is also used as a transition signal of the break acknowledge signal BRKAK. The portion initialized by the user reset is initialized by the RST signal. The portion initialized by the break reset is initialized by the BRST signal.

By referring to the state of the EMLWAIT # signal when the RES # terminal transits to the inactive state, break reset will not be mistakenly performed even if RES # is activated in any state. When the RES signal becomes active, the emulator starts EMLWAI.
If the T # signal is deactivated, the user is reset.
Most of the emulator dedicated registers are retained. #
Indicates a negative logic signal.

Next, the break acknowledge BRKAK signal control circuit will be described with reference to the block diagram of FIG.

The BRKAK signal is controlled by the flip-flop circuit. The output of the flip-flop circuit is BR
It is a KAK signal. The output of the AND circuit is given as the set signal of the flip-flop. One input of the logical product circuit is the clock φ2, the other input is the output of the logical sum circuit, and the input of the logical sum circuit is B
The RST signal and the SETBRKAK signal output at a predetermined timing when the CPU executes the break exception processing.

The break exception handling is BRKCR.B when the break instruction BRK is executed, when a break interrupt is executed by a break request from the BRK terminal.
This is performed when a break interrupt is executed by a break request due to the condition being satisfied by AR / BAMR and when a single step break is executed.

Further, the output of the AND circuit is given as the set signal of the flip-flop. One input of the AND circuit is the clock φ2, and the other input is the CPU
Is a RESBRKAK signal to be output at a predetermined timing when the return instruction RTB from the break is executed.

Therefore, at the time of break reset or when the CPU starts break exception handling, BRKAK
The signal becomes active. The BRKAK signal becomes inactive when the CPU executes break exception handling.

Next, an example of the emulation dedicated control register will be described with reference to the block diagram of FIG.

The control register is mainly composed of flip-flops. The output Q of such a flip-flop is used as a control signal. The output is also connected to the data bus via the clocked buffer. The clock of the clocked buffer is a logical product signal of the logical product signal of the address decode signal and the break mode signal and the read signal.

The input D of the flip-flop is the data bus, and the clock C is the logical product signal of the logical product signal of the address decode signal and the break mode signal and the write signal. Such an address decode signal is C
It is activated when the address output from PU reaches the address where the control register exists. That is, the read / write is possible only in the break mode. IRQC
With respect to R, the break mode signal is excluded because the read / write is possible even in the user mode.

The reset input R of the flip-flop is used as a break reset signal. Cleared to "0" at break reset. For the control register that should be set to "1" at break reset, the break reset signal is input to the set input of the flip-flop.

Since the IRQCR is initialized by the user reset, the reset input R becomes the user reset signal. In addition, the reset input is excluded from EMLSTKR, and it is not initialized by user reset or break reset.

Next, the break interrupt control circuit will be described with reference to the block diagram of FIG.

There are three factors for the break request to the CPU. The first is a request by the BRK terminal. The second is a request by the address comparison A, which is B in BRKCR.
Permitted by the IEA bit. The third is a request by address compare B, which is granted by the BIEB bit in BRKCR.

The address comparison is as described above.
(CA23 ・ AR23 + ¬CA23 ・ ¬AR23 + AM
R23) ···· (CAn · ARn + ¬CAn · ¬ARn
+ AMRn) ... (CA0 ・ AR0 + ¬CA0 ・ ¬A
It is expressed as R0 + AMR0). These OR signals are given to the CPU as a break request.

In the break mode, permission or prohibition of the break request by the BRK terminal is selected depending on the state of the BMBE bit. That is, the break request is suppressed when the BMBE bit is cleared to "0" in the break mode. Break requests due to address comparison are prohibited in break mode.

The BMBE bit is composed of a flip-flop, which is cleared to "0" by an inverted signal of the BMBEK signal. The input of such a flip-flop is a bit of a predetermined data bus, and the clock is a logical product signal of a break mode signal, an address decode signal and a write signal. The address decode signal is activated when the address output by the CPU becomes the address where the BRKCR exists. That is, writing is possible only in break mode. That is, immediately after the transition to the break mode, the break request is in the disabled state, and the multiple exception handling of the undesired break is prohibited.

Also, the SSTP bit of BRKCR and B
The logical product of the RKAK signal and the inverted signal is given to the CPU as a single step break request. The single-step break request, the logical product signal of the RTB instruction execution signal, and the break request are recognized inside the CPU as a CPU break exception handling request. The contents of these exception processes are common. The CPU ignores the single step break request when executing the RTB instruction.

Next, the outline of the emulator will be described with reference to the block diagram of FIG.

The connector part is an application system (user system) instead of the single-chip microcomputer.
Be attached to. The emulation processor inputs and outputs signals to and from the application system using the target system interface via the connector section and the interface cable.

Although not particularly limited, the user system has a user bus and a user memory is connected to the user system. The user memory is read / written according to the user strobe signal output from the emulation processor and supplied via the interface cable. The reset signal is supplied from the user system via the interface cable.

An OR signal with the emulator reset signal is supplied to the RES terminal of the emulation processor. As the emulator reset signal, a logical sum signal of the delay circuit and the emulator memory wait signal is supplied to the EMLWAIT terminal of the emulation processor. The emulator reset signal is generated when the entire emulator is reset, such as when the emulator is powered on. Further, as the command of the emulator, user reset can be given based on the information input from the system development device.

On the other hand, the emulation processor is connected to the emulation bus using the emulation interface. The emulation bus includes status signals, control signals, etc., which are not shown. Using the emulation bus, the emulation processor outputs information according to the internal states of the application system and the emulation processor, and various control signals for emulation are input to the emulation processor. An emulation mode terminal (not shown) of the emulation processor is fixed to the power supply level, and the emulation mode is set inside the emulation processor.

Further, the emulation bus has
Although not particularly limited, there is an emulation memory such as a RAM for substituting the memory built into the application system or the target microcomputer.
As the emulation memory, there are a high-speed memory that should act as a substitute for the built-in ROM and a rental memory that is released to the user.

When a user's program is created, it is often designed with a sufficient capacity, and it may not fit in the built-in ROM. Even in such a case, the user can use the rented memory of the emulator to substantially expand the program memory and start debugging. As the debugging progresses, the program can be optimized so that it fits in a predetermined capacity. The rental memory does not necessarily need high speed because of its characteristics.

Further, the emulation processor monitors the control state and the state of the emulation bus, and when the state reaches a preset state, the emulator dedicated interrupt is input to stop the execution of the user program by the CPU. A break control circuit for making a transition (break) to a program execution state for emulation, a signal indicating a read operation or a write operation of the CPU, an address or data given to the emulation bus based on a signal indicating an instruction read operation, and Is connected to a real-time trace circuit for sequentially storing control information. The emulation bus is connected to an emulation memory, a break control circuit, a real-time trace circuit, etc., respectively.

The break control circuit supplies the BRK signal to the emulation processor.

The emulation memory, break control circuit, and real-time trace circuit are connected to the control bus and are controlled by the control processor via the control bus. The control bus is connected to an emulation processor control circuit, and via an interface circuit,
Although not particularly limited, it is connected to a system development device such as a personal computer.

For example, when the program input from the system development apparatus is transferred to the emulation memory and the CPU reads the program to be arranged on the built-in ROM, the program on the emulation memory is read. Also, break conditions and real-time trace conditions can be given from the system development device.

The control processor is EMLIRQ.
The signal is supplied to the emulation processor. The EMLIRQ can be requested at a desired timing to cause the emulation processor to execute a predetermined EMLIRQ interrupt processing routine.

Next, the operation of the emulator will be described with reference to the operation flowchart of FIG.

After the power is turned on, a break reset is first performed, the break mode is immediately entered, and the emulation program is executed. Which microcomputer to operate as an emulation processor is input from the system development device, the host interface,
It is set in the module control register via the control processor and emulation memory (S1 to S
3).

A desired emulator process is performed, and based on a command input from the system development device,
If the execution of the user program is requested, the emulation processor executes the return instruction RTB instruction to transit to the user mode and execute the user program (S
4 to S6).

In this state, if reset is requested from the user system, reset processing of the user program is performed. At this time, the emulation dedicated register is held. When the user program to be executed ends or the condition set by the user is satisfied, the execution of the user program is interrupted (break) and the emulation program is executed (S7, S8, S6 to S9).

As shown in FIG. 4, during the break mode, 3-state access except for windows and EMLWAIT permission are permitted regardless of the user's designation. Since all emulation programs are allowed to wait, the access speed of the emulation memory and the location on the emulator are not restricted. This facilitates emulator design.

According to the emulation processor and emulator configured and operated as described above, the following operational effects can be obtained.

(1) After the reset, by designating the break mode or the user mode with the control terminal, it is possible to execute a desired program after the reset without controlling the emulator. Further, by setting the control terminal to the EMLWAIT signal, it is not necessary to increase the number of input / output terminals of the emulation processor.

Further, the emulator control register is initialized at the time of break reset and not initialized at the time of user reset, so that the operation after power-on can be confirmed and the time and effort of software for initialization can be saved.

(2). Dividing the address space, providing a bus control register corresponding thereto, and designating whether to access using the user bus or the emulation bus by this bus control register As a result, a user memory and an emulation memory can be mixed in the address space of the CPU without the need for an address determination circuit or a bus control circuit on the emulator side. The control terminal can be omitted.

Also, the division of the address space is made asymmetric,
By setting the size of the minimum area to 128 kB or the like, it is possible to correspond to the capacity of the memory that can be connected to the outside, and the flexibility in arranging the lending memory (emulation memory) and the user memory can be improved.

(3) By incorporating the PC break function, a break can be requested without the need for an address judgment circuit or instruction execution judgment circuit on the emulator side. Further, since an external circuit is not required, the time required for judgment and control can be shortened, it becomes easy to break in the desired instruction execution state, and it is possible to prevent the execution of several extra instructions. it can.

Further, by outputting the coincidence detection function, it is possible to easily realize the time from the predetermined execution state to the predetermined execution state. It is possible to easily measure the number of executions of a predetermined program. By requesting the break interrupt based on the measurement result, the user program can be easily stopped when the user program is executed a desired number of times.

Further, by providing the single step designation bit, the break can be requested without the need for the address judging circuit and the instruction execution judging circuit on the emulator side. In addition, the time required for judgment and control can be shortened, and it becomes easy to break each time an instruction is executed.

(4). Provide a stack area for the emulator,
It is possible to specify whether or not to allow break multiple interrupts, and by setting such an initial value in a disabled state, the address to be returned will not be lost.

Further, by allowing multiple interrupts for a break with such a control bit, a break interrupt can be requested in the break mode, and flexibility is improved.

(5) By providing a general interrupt that can be requested from the emulator side in addition to the break interrupt, the monitor software can be activated without using the resources on the user side.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the size of the address space, the number of divisions, the number / type of function blocks or modules incorporated, the number of pins, etc. are not limited. The arrangement of the control registers, the specific configuration of the emulation processor dedicated block, the specific configuration of the emulator, etc. are not limited to those in the above embodiment, and various changes can be made.

The bus cycle designated by the microcomputer includes the bus width, the number of bus states, the address multiplex, the number of valid address bits, the output of the address decode signal, the multiplex of the data and the address, and the like. be able to. Some of these can be shared in the emulation bus cycle. The bus width may be common. It suffices not to destroy the contents of the memory on the user side. The address decode signal may be output.

Further, the basic external bus cycle and the bus cycle of the built-in ROM / built-in RAM / internal I / O register can be arbitrary. The registers initialized only by break reset can be changed arbitrarily.
The initial value can also be arbitrary. For example, external ST
When the hardware standby mode using the BY terminal is provided, all the control registers may be initialized in the hardware standby mode.

Also, the number and types of control signals for the emulator can be arbitrarily changed. Input detection of the emulator-only interrupt can also be changed. A bit for selecting input detection may be provided.

In the above description, the invention mainly made by the present inventor is applied to the emulation processor which is the field of use thereof and the emulator equipped with the emulation processor. However, the invention is not limited to this. The present invention is also widely applicable to the semiconductor integrated circuit device having at least two operating states and arranging the memory twice in the address space.

[0153]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). Means for making it possible to select whether to immediately enter the break mode after reset or to set the user mode in the state of the input terminal. In the break mode, access the emulation memory for each area or A means for designating whether to access the memory, a break condition is set in the emulation, and in particular, it has a bit for requesting single step processing. When such a bit is in a predetermined state, for each instruction of the user program By providing a means for automatically requesting a break interrupt, it is possible to take what was controlled outside the emulation processor into the emulation processor, so a wealth of information inside the emulation processor is used during emulation. It becomes possible.

(2) By the above (1), since the external control is taken into the emulation processor, the signal delay from the emulation processor to the emulator and the signal from the emulator to the emulation processor are delayed. It is possible to eliminate the effect of delay.

(3) According to the above (1), what is controlled externally is taken into the emulation processor, so that the emulation can be performed easily and at high speed without increasing the input / output signals between the emulation processor and the emulator. It becomes possible to control the processor for use.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a microcomputer that is an emulation target of an emulation processor that is an embodiment of the present invention.

FIG. 2 is a block diagram showing an emulation processor in the present embodiment.

FIG. 3 is an explanatory diagram showing a configuration of an emulator dedicated register in the present embodiment.

FIG. 4 is an explanatory diagram showing the configuration of the emulator-dedicated register (continued from FIG. 3) in the present embodiment.

FIG. 5 is an explanatory diagram showing a configuration of an emulator-dedicated register (continued from FIG. 4) in the present embodiment.

FIG. 6 is an explanatory diagram showing the configuration of the emulator-dedicated register (continued from FIG. 5) in the present embodiment.

FIG. 7 is an explanatory diagram showing a configuration of an emulator-dedicated register (continued from FIG. 6) in the present embodiment.

FIG. 8 is an explanatory diagram showing a configuration of a register dedicated to an emulator (continued from FIG. 7) in the present embodiment.

FIG. 9 is an explanatory diagram showing a configuration of a register dedicated to an emulator (continued from FIG. 8) in the present embodiment.

FIG. 10 is an explanatory diagram showing an address map of an address space in the present embodiment.

FIG. 11 shows the MEMCR and EWTCR in this embodiment.
FIG. 5 is an explanatory diagram showing an access state according to FIG.

FIG. 12 shows the MEMCR and EWTCR in this embodiment.
12 is an explanatory diagram showing an access state (continued from FIG. 11) according to FIG.

FIG. 13 is a block diagram showing a bus configuration of an emulation processor in the present embodiment.

FIG. 14 is a timing chart showing an example of bus timing in the present embodiment.

FIG. 15 is a timing diagram of break reset in the present embodiment.

FIG. 16 is a timing diagram of user reset in the present embodiment.

FIG. 17 is a block diagram of a break reset control circuit in the present embodiment.

FIG. 18 is a block diagram of a break acknowledge signal control circuit in the present embodiment.

FIG. 19 is a block diagram showing an example of an emulation dedicated control register in the present embodiment.

FIG. 20 is a block diagram of a break control circuit in the present embodiment.

FIG. 21 is a block diagram of an emulator equipped with an emulation processor according to the present embodiment.

FIG. 22 is an operation flowchart of the emulator equipped with the emulation processor according to the present embodiment.

[Explanation of symbols]

 CPU central processing unit DTC data transfer controller ROM read only memory RAM random access memory SCI serial communication interface A / D A / D converter IOP1 to IOP11 I / O port BSC bus controller CPG clock oscillator MS module select unit IAB, PAB internal address bus IDB, PDB Internal data bus Vcc, Vss power supply terminal AVcc, AVss analog power supply terminal RES reset input terminal STBY standby input terminal NMI interrupt input terminal EXTAL, XTAL clock input terminal MD0, MD1, MD2 operation mode input terminal MSELR module selection register MEMCR Memory control register EWTCR Wait control register BRKCR Break control Register BAR break address register BAMR break address mask register IRQCR emulator dedicated interrupt control register EMLSTKR emulator stack memory register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Suzuki 5-22-1, Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (14)

[Claims] 1. An emulation processor capable of emulating a microcomputer, which selects a first mode in which an emulation program operates or a second mode in which a user program to be emulated operates. And a means for setting a first reset state in which the entire emulation processor is reset or a second reset state in which only the microcomputer part to be emulated is reset. In the first reset state, prior to the start of operation. An emulation processor, which is in the first mode and is in the second mode prior to the start of operation in the second reset state. 2. The emulation processor according to claim 1, wherein the first and second reset states are selected by a common reset signal and a selection signal, and the selection signal has a different function after reset release. An emulation processor that operates as a control signal. 3. The emulation processor according to claim 1, wherein the selection of the first reset state and the second reset state depends on a state of a selection signal at a transition of the common reset signal to an inactive state. An emulation processor characterized by being selected. 4. An emulator equipped with the emulation processor according to claim 1, 2, or 3.
A logical sum signal of a reset signal of the user system and a reset signal of the emulator is input to the common reset signal, and when the reset signal of the user system is active, the selection signal is selected to the second reset state. An emulator characterized by having means for setting the selection signal to a state in which the first reset state is selected when the reset signal of the emulator is in an active state. 5. An emulation processor capable of emulating a microcomputer, having means for selecting a first mode in which an emulation program operates or a second mode in which a user program to be emulated operates. Then, divide the address space of the microcomputer to be emulated,
For at least one of the divided areas, in the second mode, there is provided means for designating whether to perform a bus cycle designated by the microcomputer or a bus cycle for emulation. Processor. 6. The emulation processor according to claim 5, further comprising a memory control bit corresponding to at least one of the divided address spaces, wherein in the second mode, the memory control bit is first. An emulation processor which performs a bus cycle designated by the microcomputer in the state 1) and performs a bus cycle for emulation when the memory control bit is in the second state. 7. The emulation processor according to claim 5, wherein the emulator wait is always valid in the emulation bus cycle. 8. The emulation processor according to claim 5, 6 or 7, wherein the address space is divided into three or more areas, and at least one divided area is other at least two divided areas. And an emulation processor characterized in that the size of the address space is different. 9. An emulator equipped with the emulation processor according to claim 5, 6, 7 or 8, wherein the emulation processor, the read / write of the memory of the user system, and the read / write of the memory of the emulator system. Is possible,
An emulator characterized by reading or writing the memory of a user system in a bus cycle designated by the microcomputer, and reading or writing the memory of an emulator system in a bus cycle for emulation. 10. An emulation processor capable of emulating a microcomputer, and means for selecting a first mode in which an emulation program operates or a second mode in which a user program to be emulated operates. A single step control bit, wherein the single step control bit is in the first state, in the second mode, and in the first mode.
In the emulation processor, the transition processing to the first mode is always performed at the time of completion of instruction execution other than the return instruction from the mode. 11. The emulation processor according to claim 10, wherein the single-step control bit is writable only in the first mode. 12. An emulation processor capable of emulating a microcomputer, which selects a first mode in which an emulation program operates or a second mode in which a user program to be emulated operates. It has a register designating an address, an address comparison circuit, first and second break interrupt control bits, and a trigger output terminal, and the address comparison circuit is a CPU of the microcomputer.
Which outputs the coincidence signal by inputting the address to be output by and the output of the register designating the address,
When the first break interrupt control bit is in the first state, the transition processing to the first mode is performed when the match signal is in the active state, and the match signal is sent to the trigger output terminal. An emulation processor having means for outputting from. 13. An emulation processor capable of emulating a microcomputer, and means for selecting a first mode in which an emulation program operates or a second mode in which a user program to be emulated operates. An instruction for performing a transition process to the first mode, a control terminal for performing a transition process to the first mode, and a multiple break interrupt control bit, wherein the multiple break interrupt control bit Is the first
State, the transition processing to the first mode by the control terminal is possible even in the first mode, and when the multiple break interrupt control bit is in the second state, in the first mode. An emulation processor, wherein transition processing to the first mode by the control terminal is prohibited. 14. The emulation processor according to claim 13, wherein the multiple break interrupt control bit is initialized to a second state in the second mode.