JPH0815264B2 - Path memory circuit for Viterbi decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A path memory circuit of a Viterbi decoder is composed of a selector and a latch circuit, and a history storage process of a maximum likelihood path is performed by a path select signal in a time division manner, and the number of gates is small. The latch circuit facilitates integration into an integrated circuit, and an arbitrary block configuration can be switched by external control.

[Industrial applications]

The present invention relates to a Viterbi decoder path memory circuit configured by using a latch circuit in a Viterbi decoder that performs error correction decoding of a convolutional code.

The Viterbi Decoder is a convolutional code (Conter Code).
volutional code) maximum likelihood decoding method, and selects the path with the closest code distance to the received code series as the maximum likelihood path from among a plurality of known code series and supports the selected path. It is used as a decoder in satellite communication systems and the like because it has high error correction capability.

The path memory circuit for storing the history of the maximum likelihood path in this Viterbi decoder requires the number of stages which is about 5 to 6 times the constraint length of the convolutional code. It is required to be configured in a physical manner.

[Conventional technology]

The Viterbi decoder, as shown in FIG.
The S circuit 62 and the path memory circuit 63 are main components. The distributor 61 calculates a branch metric from the received code and adds the branch metric to the ACS circuit 62. When the demodulated signal of the quadrature amplitude modulation signal is judged by, for example, 8-value soft judgment, the judgment output has a 3-bit structure, The received code having a total of 6 bits is added to the distributor 61.

The distributor 61 is composed of, for example, inverters 64 and 65 and adders 66 to 69 as shown in FIG. When the judgment output signals I and Q of the demodulation signal of the quadrature amplitude modulation signal are input, (I + Q), (I +), (+
4 types of branch metrics BM1 to BM4 of 4-bit configuration indicating 0 to 14 of Q) and (+) are output, and the ACS circuit 6
Added to 2.

The ACS circuit 62 includes an adder (Adder) and a comparator (Comparat
or) and a selector (Selector),
A combination of the respective first letters is called an ACS circuit. The ACS circuit 62 is composed of 2 ^k-1 ACS circuit units, ^where K is the constraint length of the convolutional code. When this constraint length K is set to 3, as shown in FIG. 17, 2 ^3-1 = 22 ² = 4 (pieces) ACS circuit units (ACS1 to ACS4) 71
~ 74. Each ACS circuit section 71-74
Calculates a new path metric from the branch metrics BM1 to BM4 and the path metric one symbol before, and outputs the path select signals PS1 to PS4 at that time.

For example, the ACS circuit unit 71 uses the branch metrics BM1, BM2
And the path metric one symbol before from the ACS circuit units 71 and 73 are added to calculate a new path metric, and the path select signal PS1 at that time is output. ACS circuit section 73
Is added with the branch metrics BM3, BM4 and the path metric one symbol before from the ACS circuits 72, 74 to calculate a new path metric, and the path select signal at that time is calculated.
Output PS3.

Each ACS circuit unit 71 to 74 is composed of adders (A) 75 and 76, a comparator (C) 77, and a selector (S) 78, as shown in FIG. The path metric is added to the adders 75 and 76, respectively, and the addition outputs of the adders 75 and 76 are compared by the comparator 77, and the signal of the comparison result is used as a path select signal in the selector 78 and the path memory circuit 63 (15th). In addition to the above), the smaller value of the addition result is output from the selector 78 as a new path metric and used for calculating the path metric of the next symbol.

As described above, the path memory circuit 63 stores the path select signal as the history of the maximum likelihood path. Conventionally, for example, the configuration shown in FIG. 19 is used. 19th
In the figure, only three stages out of five to six times the constraint length K of the convolutional code are shown, and the path memory cells MS11 to MS43 including the selector SEL and the flip-flop FF are shown.
The fixed pattern of “0”, “1”, “0”, “1” is input to the first-stage path memory cells MS11, MS21, MS31, MS41 as the first-stage set value, and The state indicates the lower 1 bit of "00", "01", "10", "11" in four states.

The path select signals PS1 to PS4 from the four ACS circuit units 71 to 74 are respectively the selectors SE of the path memory cells.
The output data of the two path memory cells in the preceding stage added to L are selected by the path select signals PS1 to PS4, added to the flip-flop FF, and set according to the common clock signal CK. That is, the contents of the path memory cell on the side determined as the surviving path in each decoding cycle are transferred at the timing of the clock signal CK according to the path select signal.

[Problems to be solved by the invention]

In the Viterbi decoder, the larger the constraint length K of the convolutional code, the higher the error correction capability, but on the other hand, there is a drawback that the circuit scale increases exponentially.
In addition, the path memory circuit 63 in the Viterbi decoder requires the number of stages which is about 5 to 6 times the constraint length K of the convolutional code, as described above. When the constraint length K of the embedded code is increased, it is necessary to increase the number of stages correspondingly. Further, since each path memory cell forming the path memory circuit 63 is composed of the selector SEL and the flip-flop FF, there is a drawback that the number of gates is relatively large, and thus it is not easy to be integrated into a circuit.

It is an object of the present invention to facilitate integration into an integrated circuit and switch to a configuration corresponding to a desired decoding speed.

[Means for solving problems]

The Viterbi decoder path memory circuit of the present invention will be described with reference to FIG. 1. In the Viterbi decoder path memory circuit, the path select signal from the ACS circuit is added to store the history of the maximum likelihood path. , A plurality of stages of latch circuits 3,
A selector 2 to which a path select signal from the ACS circuit is added is provided in front of each latch circuit other than the last latch circuit of the latch circuit 3, and the selector 2 and the latch circuit 3 constitute the path memory circuit. To form a pass memory cell 1 and to make the final stage latch circuit a slave latch circuit for the last stage latch circuit, and to operate a plurality of stages of latch circuits including this slave latch circuit in a sequentially different phase from the output side. Clock signal lines 4-1 to 4-1
4-n (FIG. 1 shows the case where n = 3).

In addition, in a path memory circuit for a Viterbi decoder which stores a history of maximum likelihood paths when a path select signal from the ACS circuit is added, each path memory cell 1 constituting this path memory circuit is replaced with a selector 2 and a latch circuit. Composed of 3 and
Clock signal lines 4-1 to 4-n for operating the latch circuits 3 corresponding to the respective stages from the output side in a sequentially different phase are provided.
The selector 2 of the path memory cell 1 at a position where the number of stages forming one block can be divided into an equal number of stages is used as a 3-1 selector and connected to the path memory cell 1 of the immediately preceding stage, and this 3-1 selector is connected to the path. When the selection operation is performed by the select signal or the output data of the immediately preceding pass memory cell 1 is selectively controlled, and the output data of the immediately preceding pass memory cell 1 is output, the 3-1 A control line 5 for operating a path memory cell having a selector as a slave latch circuit for the immediately preceding path memory cell 1 is provided, and a slave latch circuit is provided at the final stage.

[Action]

The latch circuit 3 latches the output data of the selector 2 which is controlled by the path select signal. When the latch circuits 3 of each stage are operated by the same clock signal,
Data will pass through to the final stage, but by separating the clock signal lines 4-1 to 4-n at each stage and adding clock signals with different phases, the internal state according to the path select signal from the ACS circuit. Can be performed, and the output data of the latch circuit 3 of the path memory cell at the final stage can be latched by the slave latch circuit.

Further, when the selector 2 of the path memory cell 1 at a position where a block consisting of a plurality of stages can be divided into an equal number of stages is a 3-1 selector and the 3-1 selector is controlled to perform a selection operation by a path select signal, The path memory cell having the 3-1 selector operates in the same manner as other path memory cells, and when the 3-1 selector is selectively controlled to output the output data of the immediately preceding path memory cell, The path memory cell having the 3-1 selector operates as a slave latch circuit for the latch circuit 3 of the immediately preceding path memory cell. Therefore, by selectively controlling the 3-1 selector via the control line 5, the desired number of stages can be divided, and the slave latch circuit can be formed at the final stage of each divided block. Further, the smaller the number of stages in the divided block, the smaller the number of clocks in one decoding cycle, so the decoding operation can be speeded up.
In that case, since the number of path memory cells that are diverted to the slave latch circuit increases, the number of stages of the path memory circuit decreases. That is, if the switching control is performed so as to increase the number of divided blocks of the path memory circuit having a predetermined number of stages, the number of clocks required in one decoding cycle can be reduced, which facilitates high-speed decoding, but on the other hand, The number of stages that can be used as path memory cells is reduced. On the other hand, if the number of divided blocks is reduced, the number of clocks required for one decoding cycle increases and high-speed decoding becomes difficult, but the number of stages that can be used as path memory cells increases. Therefore, it is possible to control the switching of the block configuration in accordance with a desired decoding speed or a desired number of stages.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, showing a case where the constraint length K of the convolutional code is 3 and one block has a three-stage configuration. S11 to S43 are the selector 2 and the latch circuit 3, respectively. Is a path memory cell composed of
L4 is a slave latch circuit. The selector 2 is a 2-1 selector that selectively outputs input data of two terminals according to a path select signal, and the selected output data is added to the latch circuit 3.

Path select signals PS1 to ACS from the ACS circuit (not shown)
PS4 is added to the selector 2 of the path memory cells S11 to S43, and the first-stage path memory cells S11, S21, S31, S41 have the first
As explained in Fig. 9, the initial setting value is added.

Also, the slave latch circuits L1 to L4 and the path memory cell S11
Clock signals CK0 to CK3 whose phases are sequentially different from each other are added to the respective stages of S43 to S43. Therefore, the clock signal CK
When 0, the output data of the block is latched in the slave latch circuits L1 to L4. That is, a plurality of stages of latch circuits and a selector 2 to which the path select signals PS1 to PS4 are added are provided in front of the latch circuits other than the final stage latch circuit, and the path memory cell 1 is provided by the selector 2 and the latch circuit 3.
And the final stage latch circuit as the slave latch circuits L1 to L4 for the immediately preceding latch circuit, the clock signals CK0 to CK3 sequentially different in phase from the output side are transmitted to the slave latch circuits L1 to L4 via the clock signal line. And the latch circuit 3 are added.

The output data of the slave latch circuits L1 to L4 becomes the input data of the next block when the path memory circuit has a multi-stage block configuration.

FIG. 3 is an operation explanatory diagram of one embodiment of the present invention.
(A) is a data clock signal, (b) is a path select signal, (c) is an internal clock signal, (d) to (g) are examples of clock signals CK0 to CK3, and clock signals CK0 to CK having different phases. CK3 can be easily formed by a known means such as a counter based on the internal clock signal shown in (c).

Further, when the clock signal CK0 shown in (d) is applied to the slave latch circuits L1 to L4, the output data of the latch circuit 3 of the path memory cells S13, S23, S33, S43 at the final stage of the block is changed to the slave latch circuits L1 to L4. Latched to L4. When the clock signal CK1 shown in (e) is applied to the latch circuit 3 of the last-stage path memory cells S13, S23, S33, S43, the output data of the selector 2 according to the path select signals PS1 to PS4 is output to the latch circuit. Latched to 3.

Further, the clock signal CK2 shown in (f) corresponds to the path memory cell S1.
When applied to the latch circuit 3 of 2, S22, S32, S42, the output data of the selector 2 according to the path select signals PS1 to PS4 is latched in the latch circuit 3. Also, when the clock signal CK3 shown in (g) is applied to the latch circuit 3 of the path memory cells S11, S21, S21, S41, the path select signals PS1 to PS4.
The output data of the selector 2 according to the above is latched in the latch circuit 3.

Therefore, the output data of the block is latched by the slave latch circuits L1 to L4 in one cycle of the data clock signal,
The data is transferred from the latch circuit 3 of each stage to the latch circuit 3 of the next stage according to the path select signals PS1 to PS4.

This embodiment shows a case where one block has a three-stage structure and is operated by four-phase clock signals CK0 to CK4, and one decoding cycle requires four clocks. It is also possible to increase the number of stages in one block, and in that case, if the number of stages is n, it is necessary to have a clock signal of n + 1 phase including a clock signal applied to a slave latch circuit that latches the output data of the block. Will be done. In this case, the smaller the number of stages n, the smaller the number of clocks required for one decoding cycle. Therefore, in the case of clock signals having the same speed, it is easy to shorten one decoding cycle and improve the decoding speed.

The latch circuit 3 has, for example, the configuration shown in FIG. 4, 11 is a data input terminal, 12 is a clock signal input terminal, 13 is an inverter, 14 and 15 are AND circuits, 16 is an OR circuit, Q is an output terminal.

When the clock signal is "0", the output signal of the inverter 13 becomes "1", and the data applied to the input terminal 11 is output from the output terminal Q via the AND circuit 14 and the OR circuit 16 and latched. The circuit goes through.

If the clock signal is "1", the data at the output terminal Q is fed back to the OR circuit 16 via the AND circuit 15,
The latch circuit is in the latched state.

A flip-flop that constitutes a path memory cell of a conventional example, for example, a flip-flop FF that constitutes each path memory cell of FIG. 19, has a latch circuit as shown in FIG.
It is configured by using individual pieces. FIG. 5 shows an example of a master-slave flip-flop configured by using two such latch circuits. In the figure, 21 is a data input terminal, 22 is a clock signal input terminal, 23 and 24 are latch circuits having the configuration shown in FIG. 4, and 25 is an inverter.

In this master-slave flip-flop,
The latch circuit 23 at the front stage serves as a master and the latch circuit 24 at the rear stage serves as a slave, and latches the data applied to the input terminal 21 in accordance with the clock signal applied to the input terminal 22. Therefore, the flip-flop forming the conventional path memory cell requires approximately twice as many gates as the latch circuit.

On the other hand, in the present invention, the path memory cell 1
Since it is composed of the selector 2 and the latch circuit 3, the number of gates is smaller than that in the conventional example using the flip-flop, and the integrated circuit is easy.

FIG. 6 is a block diagram of another embodiment of the present invention, showing a case of a plural block configuration. In the figure, BL1 to BL3
Is a block consisting of n stages of path memory cells, LA
Reference numerals 1 to LA3 are slave latch circuits, and a path memory circuit having 3n stages is configured as a whole. Further, clock signals CK0 to CKn having different phases are sequentially applied from the output side to the slave latch circuits LA1 to LA3 and the latch circuits of the n-stage path memory cells in the blocks BL1 to BL3.

The output data of each block BL1 to BL3 is the clock signal CK.
At the timing of 0, they are simultaneously latched by the slave latch circuits LA1 to LA3. In addition, in each of the blocks BL1 to BL3, data according to the path select signal is transferred in parallel and latched by the latch circuit of the path memory cell of the next stage. The path select signal is applied to each of the blocks BL1 to BL3 for one cycle of the data clock signal. In each of the blocks BL1 to BL3, the clock signals CK1 to CKn cause time-divisional latch circuits toward the output side. Transfers are made between.

In this case, as the number of stages n in each of the blocks BL1 to BL3 is reduced, the number of blocks is increased in order to obtain the total number of stages required for the path memory circuit.
As described above, since the number of clocks required for one decoding cycle can be reduced, the speed can be increased. On the contrary, as the number of stages n increases, the number of clocks required for one decoding cycle increases, but the slave latch circuit occupies the whole.
The ratio of LA1 to LA3 is reduced, and it is possible to efficiently form an integrated circuit.

FIG. 7 is a block diagram of still another embodiment of the present invention, in which one block has a seven-stage configuration, and the inside of the block can be further divided by a switching control signal from the outside. In the figure, M11 to M47 are path memory cells, 2 is a 2-1 selector, 2a is a 3-1 selector, 3 is a latch circuit, L1 to L4 are slave latch circuits, PS1 to PS4 are path select signals, and CK0. ~ CK7 is a clock signal, and SW is a switching control signal.

Even-numbered path memory cell M16 from the last stage of the block
-M46, M14-M44, M12-M42 has a 3-1 selector 2a, the path memory cells of the other stages have a 2-1 selector 2, and the 3-1 selector 2a has a 2-1 selector Similar to 2,
The switching control signal SW selectively controls whether the data selected by the pass select signals PS1 to PS4 is added to the latch circuit 3 or the output data of the immediately preceding pass memory cell is added to the latch circuit 3 as it is.

The path select signal PS1 from the ACS circuit (not shown)
~ PS4 is added to the selectors 2 and 2a of the path memory cells M11 to M47, and clock signals CK1 to CK7 having different phases are used.
Are added to the latch circuits of the path memory cells in the respective stages, and the clock signal CK0 is added to the slave latch circuits L1 to L4.

When the 3-1 selector 2a is controlled by the switching control signal SW to perform the selection operation by the path select signals PS1 to PS4, the same operation as the 2-1 selector 2 is performed.
The path memory cells M11 to M47 form a path memory circuit of seven stages in one block, and the output data of this block is latched in the slave latch circuits L1 to L4 at the timing of the clock signal CK0.

Further, according to the switching control signal SW, for example, the path memory cell M1
4 to M44 3-1 selector 2a uses path select signals PS1 to PS4
If it is controlled so that the output data of the immediately preceding pass memory cell is added to the latch circuit 3 of the own pass memory cell without performing the selection operation by the pass memory cells M14 to M14.
Reference numeral 44 is a slave latch circuit operated by the clock signal CK4. Therefore, a plurality of stages before this stage are set as one block, and the output data of the block is latched. The clock signals CK0 and CK4 are in-phase, the clock signals CK1 and CK5 are in-phase, the clock signals CK2 and CK6 are in-phase, and the clock signals CK3 and CK7 are in-phase. Use a different phase from the signal. In that case, the phases are sequentially changed from the output side. Therefore, in the divided blocks, the latch circuits 3 of the corresponding stages simultaneously perform the latch operation.

Further, by the switching control signal SW, along with the 3-1 selector 2a of the path memory cells M14 to M44, the path memory cells M16 to M46, M12
To M42 to control the 3-1 selector 2a to add the output data of the immediately preceding pass memory cell to the latch circuit 3 of its own pass memory cell, and at the same time to select the pass select signals PS1 to PS4.
If not controlled by, the odd-numbered stages become the above-mentioned one block and the even-numbered stages become the slave latch circuits. Therefore, it has a 4-block configuration. In that case, clock signal CK
0, CK2, CK4, CK6 have the same phase, clock signals CK1, CK3, CK5, CK7 have the same phase and different phases from the clock signals CK0, CK2, CK4, CK6.

FIG. 8 is an explanatory diagram of a path memory cell including a 3-1 selector. Mij (i = 1 to 4, j = 1 when applied to FIG. 7)
~ 7) is a path memory cell, 31 is a switching control signal SW (SW1, SW)
2) input terminal, 32 is the input terminal of the path select signal PSi,
33 and 34 are inverters, 35 and 36 are AND circuits, 41 to 43 are input terminals to which output data of other path memory cells are input, 44
~ 46 is an AND circuit, 47 is an OR circuit, 48 is a latch circuit, 49
Is an input terminal of the clock signal CKn, and 50 is an output terminal.

The case where the inverters 33, 34, AND circuits 35, 36, 44 to 46, and the OR circuit 47 constitute a 3-1 selector is shown. In addition, the AND circuits 44 to 46 and the OR circuit 47
-1 selector, and inverters 33, 34 and AND circuit 3
It is also possible to share 5,36 with other 3-1 selectors. The 2-1 selector is equivalent to the configuration in which the inverter 34 and the AND circuits 35, 36, 45 are omitted.
All the path memory cells are configured to have 3-1 selectors, and the switching control signal SW can be fixedly set to "1" for the path memory cells operated as the 2-1 selectors.

When the switching control signal SW applied to the input terminal 31 is "0", the output signal of the inverter 34 is "1" and the AND circuits 35 and 36.
Output signal of "0" becomes "0", the data applied to the input terminal 42 is applied to the latch circuit 48 via the AND circuit 45 and the OR circuit 47, and is latched at the timing of the clock signal CKn. In this case, the selection control by the path select signal PSi is not performed and the slave latch circuit operates.

When the switching control signal SW is "1", the output signal of the inverter 34 becomes "0", and the output signals of the AND circuits 35 and 36 are
It corresponds to the path select signal PSi. For example,
When the path select signal PSi is "1", the output signal of the AND circuit 36 becomes "1", and the data applied to the input terminal 43 passes through the AND circuit 46 and the OR circuit 47 and the latch circuit 48.
In addition, when the path select signal PSi is "0",
The output signal of the AND circuit 35 becomes "1", the data applied to the input terminal 41 is applied to the latch circuit 48 via the AND circuit 44 and the OR circuit 47, and is latched at the timing of the clock signal CKn, Similar to the path memory cell having the 2-1 selector, selection control by the path select signal PSi is performed.

If this path memory cell Mij is, for example, the path memory cell M32 in FIG. 7, the input terminal 41 is the output terminal of the path memory cell M21 and the input terminal 42 is the output terminal of the immediately preceding path memory cell M31. , Input terminal 43 to pass memory cell M
41 output terminals, and output terminal 50 is connected to the path memory cells M13 and M23.
When the path select signal PS3 is "0", the output data of the path memory cell M21 is selected and latched at the timing of the clock signal CK6. When the path select signal PS3 is "1", the output data of the path memory cell M41 is selected and latched at the timing of the clock signal CK6.

The above-mentioned 3-1 selector is controlled by the switching control signal SW so that the inside of the block can be further divided. When one block configuration is shown in FIG.
The figure and the four-block structure are shown in FIG. In addition, in FIG. 9 to FIG. 11, the path memory cells Mi2, Mi4,
Mi6 is a path memory cell having a 3-1 selector, path memory cells Mi1, Mi3, Mi5, Mi7 are path memory cells having a 2-1 selector, and the switching control signal SW has a 1, 2, 4 block configuration. Two types of switching control signals SW1 and SW for switching
2 is used.

In FIG. 9, the switching control signals SW1 and SW2 are both “1” (see FIG. 8), and all the path memory cells Mi1 to Mi7 operate as the path memory cells having the 2-1 secreter. Illustration of the signals SW1 and SW2 is omitted. In this case, the path memory cells Mi1 to Mi7 perform the selection operation of the output data of the preceding path memory cells by the path select signal PSi, and are latched by the clock signals CK1 to CK7 having different phases. Then, the output data of the final stage is latched by the slave latch circuit Li at the timing of the clock signal CK0, and operates as a path memory circuit having one block and seven stages.

FIG. 12 is a diagram for explaining the operation of the one block configuration described above. DCK is a data clock signal, CLK is an internal clock signal, PSi is a path select signal, and CK0 to CK7 are clock signals whose phases are sequentially different from the output side. Is.

The path select signal PSi is output during one cycle of the data clock signal DCK, and the output data of the path memory cell Mi7 at the final stage of the block is latched by the slave latch circuit Li by the clock signal CK0.

Also, at the timing of the clock signal CK1, the path memory cell M
The output data of the previous pass memory cell selected by the pass select signal PSi is latched by the i7 latch circuit, and selected by the pass select signal PSi at the timing of the next clock signal CK2 by the latch circuit of the pass memory cell Mi6. The output data of the pass memory cell of the preceding stage is latched, and the first stage set value is set in the latch circuit of the pass memory cell Mi1 at the timing of the clock signal CK7 in the same manner.

Further, the switching control signal SW1 applied to the path memory cell Mi4 is set to "0".
Then (see FIG. 8), this path memory cell Mi4 does not perform the selection operation by the path select signal PSi, but only performs the operation of latching the output data of the immediately preceding bus memory cell Mi3. The memory cell Mi4 operates similarly to the slave latch circuit Li. Therefore, as shown in FIG. 10, the path memory cells Mi1 to Mi3, M
The selectors i5 to Mi7 operate as 2-1 selectors, perform selection operation by the path select signal PSi, and pass memory cells Mi1 to Mi3 via the path memory cell Mi4 that operates as a slave latch circuit by the switching control signal SW1. A two-block path memory circuit in which the blocks and the blocks of the path memory cells Mi5 to Mi7 are connected is configured.

FIG. 13 is an explanatory diagram of the operation in the case of the above-mentioned two-block configuration, and the clock signal CK0 applied to the slave latch circuit Li
And a path memory cell that operates as a slave latch circuit
The clock signal CK4 added to Mi4 has the same phase, and the clock signals of the corresponding stages in the divided blocks have the same phase. That is, the clock signals CK1 and CK5 have the same phase, the clock signals CK2 and CK6 have the same phase, and the clock signals CK3 and CK7 have the same phase. Thereby, in the divided blocks, the transition of the internal state according to the path select signal PSi is performed in parallel.

In the case of the one block and seven stages configuration, one decoding cycle requires eight clocks. However, when the two block configuration is adopted, one block has three stages configuration, so one decoding cycle is four clocks. The small number facilitates shortening one decoding cycle and improving the decoding speed. In that case, the number of stages of the path memory circuit is reduced from 7 to 6.

Further, when the switching control signal SW1 applied to the path memory cell Mi4 and the switching control signal SW2 applied to the path memory cells Mi2, Mi6 are set to “0” (see FIG. 8), each 3-1 selector is
Without performing the selection operation by the path select signal PSi,
The output data of the immediately preceding pass memory cell is added to the latch circuit of the own pass memory cell, and the same operation as that of the slave latch circuit Li is performed. That is, as shown in FIG.
Path memory cells Mi2, M to which switching control signals SW1, SW2 are applied
i4, Mi6 become the slave latch circuit and pass select signal
The selection operation by PSi is performed by the pass memory cells Mi1, Mi3, Mi5, Mi7.
In this case, it operates as a 4-block path memory circuit.

FIG. 14 is an operation explanatory diagram in the case of a four-block configuration,
Even-numbered clock signals CK0, CK2, CK4, CK6 have the same phase, and odd-numbered clock signals CK1, CK3, CK5, CK7 have the same phase. The phase relationship of the clock signal is inverted. Therefore, the output data of the odd-numbered path memory cells Mi1, Mi3, Mi5, Mi7 are the even-numbered clock signals CK0, CK2, CK4, CK6 at the timings of the even-numbered slave latch circuits Li and Sl, respectively. Path memory cell Mi2, Mi
Latched by 4, Mi6.

As described above, in the case of the 4-block structure, one decoding cycle corresponds to 2 clocks, and the number of clocks is smaller than that in the case of the 2-block structure, so that one decoding cycle can be shortened easily and the speed can be increased. However, the number of stages as the path memory circuit is reduced from 7 stages to 4 stages, and is reduced by 2 stages as compared with the 6-stage configuration in the case of the 2-block configuration.

In the above-described embodiment, the one-block seven-stage configuration has the even-numbered path memory cell selector as the 3-1 selector 2a.
Although the case of switching to a 2-block configuration or a 4-block configuration is shown, the path memory cell provided with the 3-1 selector 2a is efficient if it can be divided into an equal number of stages in the basic block. When the 1 block 11-stage configuration is used as a basic block, in order to switch to the 3-block configuration, the selectors of the 4th and 8th path memory cells from the first stage may be the 3-1 selector 2a.
In addition, the selectors of all path memory cells are 3-1 selectors 2a
However, the number of required gates increases.

〔The invention's effect〕

As described above, the present invention provides the pass memory cell 1
Is composed of a selector 2 and a latch circuit 3, a slave latch circuit is provided at the final stage, and clock signals of different phases are sequentially added from the output side to the latch circuit corresponding to each stage and the slave latch circuit. The cell 1 has a smaller number of gates as compared to the case where the cell 1 is configured by using a flip-flop including two latch circuits in the conventional example, which facilitates integration into an integrated circuit, and has a phase sequentially different from the output side. By using the clock signal, the latch circuit 3
Even if it is configured by using, the data will not pass through to the final stage, and the history of the maximum likelihood path in the Viterbi decoder can be stored.

Further, the path memory cell including the 3-1 selector is arranged at a position where it can be divided into an equal number of stages, and the path memory cell having the 3-1 selector is operated as a normal path memory cell or as a slave latch circuit. By controlling the switching control signal via the control line 5, it is possible to perform block division for each desired number of stages even after integrated into a path memory circuit.

In that case, if the number of blocks is increased and the number of stages in one block is reduced, the number of clocks required for one decoding cycle can be reduced. Therefore, it is easy to shorten one decoding cycle without using a high-speed clock signal. Become. That is, it becomes easy to improve the decoding speed. On the contrary, if the number of blocks is reduced and the number of steps in one block is increased,
The number of clocks required for one decoding cycle increases, and one decoding cycle cannot be shortened unless a high-speed clock signal is used. However, since the number of path memory circuits operating as slave latch circuits is small, the desired number of stages for the path memory circuit is required. Can be easily obtained. In other words, the 3-1 selector can be controlled by the control line 5 in accordance with the decoding speed, the number of decoding stages, etc., and block division can be performed for each desired number of stages. do it,
Since it can be used by switching to a configuration corresponding to the purpose of use, there is an advantage that cost can be reduced.

[Brief description of drawings]

1 is an explanatory view of the principle of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is an operation explanatory view of one embodiment of the present invention, FIG. 4 is a latch circuit, and FIG. Is a block diagram of a master-slave flip-flop, FIG. 6 is a block diagram of another embodiment of the present invention, FIG. 7 is a block diagram of yet another embodiment of the present invention, and FIG. 8 is a 3-1 selector. Explanatory drawing of the path memory cell including, FIG. 9 is explanatory drawing of 1 block structure, 10th
FIG. 11 is an explanatory diagram of a 2-block configuration, FIG. 11 is an explanatory diagram of a 4-block configuration, FIG. 12 is an operation explanatory diagram of a 1-block configuration, and 13th.
FIG. 14 is an operation explanatory diagram of a 2-block configuration, FIG. 14 is an operation explanatory diagram of a 4-block configuration, FIG. 15 is a block diagram of a Viterbi decoder, FIG. 16 is a block diagram of a distributor, and FIG. 17 is an ACS circuit. A block diagram, FIG. 18 is a block diagram of an ACS circuit unit, and FIG. 19 is a block diagram of a main part of a conventional path memory circuit. 1 is a path memory circuit, 2 is a selector, 3 is a latch circuit,
4-1 to 4-3 are clock signal lines, 5 are control lines, and PS1 to P
S4 is a path select signal, CK0 to CK3 are clock signals, S11
-S43 are path memory cells, L1-L4 are slave latch circuits, and 2a is a 3-1 selector. "

Continuation of the front page (56) References JP-A-59-114936 (JP, A) Masaaki Shiga "Electronic Science Series 53 Counter Circuits and Their Applications" April 30, 1977 Issued by Sanban P. Co., Ltd. 35 to 36 (Fig. 217)

Claims (2)

[Claims] 1. A path memory circuit for a Viterbi decoder, which stores a history of maximum likelihood paths to which a path select signal from an ACS circuit is added, and a plurality of stages of latch circuits (3) and the latch circuits (3). ) In the preceding stage of each latch circuit other than the final stage latch circuit, the AC
A selector (2) to which a path select signal from the S circuit is added is provided, and the selector (2) and the latch circuit (3) form a path memory cell (1) constituting the path memory circuit, and The final stage latch circuit is used as a slave latch circuit for the immediately preceding latch circuit, and clock signal lines (4-1 to 4-1 for operating the plurality of stages of latch circuits including the slave latch circuit sequentially from the output side in different phases). 4-n) is provided, a path memory circuit for a Viterbi decoder. 2. A path memory circuit for a Viterbi decoder, which stores a history of maximum likelihood paths to which a path select signal from an ACS circuit is added, and each path memory cell (1) constituting the path memory circuit.
Is composed of a selector (2) and a latch circuit (3), and clock signal lines (4-1 to 4-) for operating the latch circuit (3) corresponding to each stage sequentially from the output side in different phases.
n) is provided, and the selector (2) of the path memory cell (1) at a position where the number of stages forming one block can be divided into an equal number of stages is used as a 3-1 selector and the path memory cell (1) of the immediately preceding stage is used. Connection control is performed to control whether the 3-1 selector performs the selection operation according to the path select signal or outputs the output data of the immediately preceding path memory cell (1), and the immediately preceding path memory cell When the output data of (1) is output, the path memory cell having the 3-1 selector is
A path memory circuit for a Viterbi decoder, wherein a control line (5) for operating as a slave latch circuit for the immediately preceding pass memory cell (1) is provided, and a slave latch circuit is provided at the final stage.