JPH01295533A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To employ a storage element with a slow operating speed as a path memory by providing a serial parallel conversion section converting a path selection signal into n-symbol parallel and a selector and revising an alive path in the path memory circuit for each n-symbol in the lump. CONSTITUTION:2-1 Selectors are adopted for selectors 5, n-stage of them are provided between storage elements 4 and path selection signals PS1-1 to PS1-n, PS2-1 to PS2-n,... converted into n-set of parallel signals are fed to them respectively. Thus, the selector 5 of the 1st state is operated selectively by the path selection signals PS1-1, PS2-1,... and the selector 5 of the 2nd stage is operated selectively by the path selection signals PS1-1, PS2-1,.... Thus, the storage element 4 has only to apply storing operation for each n-symbol. That is, the speed of a clock signal CLK is a speed of 1/n of the clock signal in an ACS circuit 1 and the decoder consists of circuit elements at a low speed operation.

Description

[Detailed Description of the Invention] [Summary] Regarding a Viterbi decoder that performs error correction decoding of convolutional codes, the purpose is to enable the use of a memory element with a slow operating speed as a path memory circuit. In a Viterbi decoder equipped with a path memory circuit to which a selection signal is applied and which stores the history of the maximum likelihood path, a serial-to-parallel converter converts the path selection signal from the ACS circuit into n parallel paths; The configuration includes a selector that adds the path selection signal converted into n parallels by the parallel converter and causes the storage element to update the surviving path every n symbols.

[Industrial application field]

The present invention relates to a Viterbi decoder that performs error correction decoding of convolutional codes.

Viterbi decoder
) is used in the maximum likelihood decoding method for convolutional codes. Among multiple known code sequences, the path with the closest code distance to the received code sequence is selected as the maximum likelihood path, and the selected path Because it obtains decoded data corresponding to the data and has a high error correction ability, it is used as a decoder in satellite communication systems and the like.

The path memory circuit that stores the history of the maximum likelihood path in this Viterbi decoder requires a number of stages approximately 5 to 6 times the constraint length of the convolutional code. It is requested that it be configured.

[Conventional technology]

FIG. 4 is a block diagram of a Viterbi decoder, and the Viterbi decoder is constructed with a branch metric calculation circuit 31, an ACS circuit 32, and a path memory circuit 33 as main elements. The branch metric calculation circuit 31 calculates a branch metric from the received code and adds it to the C8 circuit 32. For example, when a demodulated signal of a quadrature amplitude modulation signal (CAM signal) is determined by 8-value soft decision, I ,Q
Each phase becomes an output signal of 3 bits, and a received code of 6 bits in total is applied to the branch metric calculation circuit 31.

The branch metric calculation circuit 31 includes, for example, inverters 34, 35 and adders 36 to 3, as shown in FIG.
9, and a determination output signal 1.9 of the demodulated signal. Q is input, (1+Q), (1+Q), (T+Q
), (T+Gl), four types of branch metrics BMI to BM4 having a 4-bit configuration indicating values of O to 14 are outputted and added to the ACS circuit 32.

The ACS circuit 32 includes an adder (adder) and a comparator (
Comparator ) and selector (S elec
tor), and 211 ACS circuit units are provided for the constraint length K of the convolutional code. Figure 6 shows the case where the constraint length is set to =3, and -1 to 2.
= 23-1 = 4 ACS circuit sections (ACSI~A
CS4) consists of 41 to 44, and each AC8 circuit section 4
1 to 44 are branch metrics BM1 to BM4, and ■
By calculating and comparing a new path metric with the bus metric before the symbol, a surviving path is selected, and path selection signals Psi to PS4, which are the selection results of the surviving path at that time, are output.

For example, the ACS circuit unit 41 uses a branch metric BM.
I, BM2, and the bus metric one symbol before from the ACS circuit section 41.43 are added to calculate a new path metric link, and output the current path selection signal Psi.

The ACS circuit units 41 to 44 include, for example, adders 45 and 46, a comparator 47, and a selector 48, as shown in FIG.
The branch metric and the bus metric are added to adders 45 and 46, respectively, and the addition outputs of the adders 45 and 46 are added to a comparator 47 for comparison, and the comparison result signal is used for path selection. It is added as a signal to the selector 48 and the path memory circuit 33 (see FIG. 4), and the smaller addition result is output from the selector 48 as a new bus metric, and is used to calculate the bus metric of the next symbol.

For example, the path memory circuit 33 has memory cells MSll to MS43 each consisting of a 2-1 selector SEL and a flip-flop FF, as shown in FIG. 8 showing a three-stage configuration, and the output of the memory cell MSII is tier memory cell MS
12. The output of the memory cell MS21 is sent to the next stage memory cell MS32. In MS42, memory cell MS31
The output of the next stage memory cell MS12. MS22, and the output of memory cell MS41 is sent to the next stage memory cell MS32,
are connected to be added to the MS42, respectively.

Then, the first stage memory cells MSII to MS41 have 4
“00”, “01” of the internal state of the street.

“0” and “1” of LSB of “10” and “11” respectively
”, “0”, and “1” are input, and the path selection signals PS1 to P from the four ACS circuit units 41 to 44 are input.
S4 is added to the 2-1 selector SEL of the memory cell, and the paths are sequentially transitioned. That is, in each decoding cycle, the contents of the memory cell on the side determined as a surviving path is transferred using the path selection signal Psi-PS4, and a decoding output is obtained from the final stage.

The path memory circuit 33 can also be constructed from a random access memory, and FIG. 9 shows a conventional example 2.
Random access memory with surface configuration (RAMI, RAM2
) 53 and 54, in which 51 is an ACS circuit, 52 is a selector, 55 is a control circuit, and 56 is a maximum likelihood path selection section.

The random access memories 53 and 54 are controlled by a control circuit 55 so that one of them performs a read operation and the other performs a write operation, and access addresses are controlled by an address control circuit (not shown). Also ACS
A path selection signal from the circuit 51 is applied to the selector 52, and, for example, the surviving path of one symbol before from the random access memory 53 is selected according to the path selection signal.
Random access memo as a new survival pass! J5
Written to 4. That is, in the same way as in the case where the surviving paths are updated from the stage to the next stage in accordance with the path selection signals Psi to PS4 in FIG. written. Then, data is read from the address corresponding to the final stage and is applied to the maximum likelihood path selection section 56 to become a decoded output.

[Problem to be solved by the invention]

In the Viterbi decoder, the larger the constraint length K of the convolutional code, the greater the error correction ability, but on the other hand,
The disadvantage is that the circuit scale increases exponentially. Furthermore, the path memory circuit 33 requires a number of stages approximately 5 to 6 times the constraint length of the convolutional code, and the number of stages increases as the constraint length K is increased to improve the correction ability. In addition, since the surviving paths are updated in accordance with the path selection signal every time one symbol is decoded, it is necessary to configure circuit elements with operating speeds corresponding to the decoding speed, and in particular, it is necessary to configure circuit elements using random access memory. In this case, reading and writing are required a plurality of times for each decoding process of l symbols, so a high-speed operation memory is required.

An object of the present invention is to enable the use of a memory element with a slow operating speed as a path memory circuit.

[Means to solve the problem]

The Viterbi decoder of the present invention updates the surviving paths in the path memory circuit once every n symbols, and will be explained with reference to FIG.

In a Viterbi decoder equipped with a path memory circuit 2 that stores the history of the maximum likelihood path to which the path selection signal from the ACS circuit 1 is added, a serial-parallel process converts the path selection signal from the ACS circuit 1 into n parallel signals. The converter 3 and this serial/parallel converter 3 convert n
Path selection signals Psi-1 to Psi-n converted into parallel
, PS2-1 to PS2-n, . . . and a selector 5 that causes the memory element 4 to update the surviving path every n symbols. In this case, the clock signal CLK is applied to the clock terminal C, and the initial value or the internal state from the previous stage is applied via the selector 5 to the data terminal.

[Effect]

If the selector 5 is a 2-1 selector, n stages are provided between the storage elements 4, and each of them has n parallel converted path selection signals PSI-1 to PS1-n, PS2-1 to PS2-n,
Add... Therefore, the selector 5 at the first stage performs a selection operation based on the path selection signals Psi-1, PS2-1, . . .
Since the selection operation is performed by S2-2゜..., the memory element 3
Therefore, it is sufficient to perform a storage operation every n symbols.

That is, the clock signal CLK only needs to have a speed of 1/n of the clock signal in the ACS circuit 1, and it is possible to configure the circuit with low-speed operating circuit elements. In addition, if the circuit is configured with high-speed operation circuit elements, it becomes possible to decode convolutional codes with a high bit rate.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of the main part of an embodiment of the present invention. When the constraint length of the convolutional code is 3, the path selection signal is converted in two parallel ways, and the surviving path is selected every two symbols. Indicates a case where an update is to be performed.

In the same figure, 11-1 to 11-4.12-1 to 12-
4 is a flip-flop which converts the path selection signal Psi-PS4 from the ACS circuit into two parallel path selection signals Psi-1,
Psi-2,...PS4-1. 13-1 to 13-4.14-
1 to 14-4 are flip-flow knobs as memory elements;
15-1 to 15-8 are flip-flops, 16-1 to 1
6-4.17-1 to 17-4.18-1 to 18-4.1
9-1 to 19-4 are 2-1 selectors, which constitute the path memory circuit 2.

A data clock signal CK is applied to the flip-flops 11-1 to 11-4, and a clock signal CL obtained by dividing the data clock signal CK by two is applied to the other flip-flops.
Add K. Therefore, the flip-flops 13-1 to 13-4 and 14-1 to 14-4 constituting the memory element can be configured with half the operating speed of the conventional example, and the number of flip-flops is also smaller than that of the conventional example. It becomes approximately 1/2.

The flip-flops 12-1 to 12-4 are two flip-flops, one to which the Q terminal outputs of the flip-flops 11-1 to 11-4 are applied, and the other to which the path selection signals PS1 to PS4 are applied. Consisting of Ql.

The parallel-converted path selection signal is output from the Q2 terminal, and the parallel-converted path selection signals Psi-1 to PS4-1
is 2-1 selector 17-1 to 17-4.19-1 to 1
9-4, and the path selection signals Psi-2 to PS4-
2 is the 2-1 selector 16-1~16-4.18-1~
Added to 18-4.

Also, flip-flops 13-1 to 13-4.14-1 to 1
4-4 and 2-1 selector 16-1 to 16-4.17-
1-17-4.18-1-18-4.19-1-19-
4 is connected so that data is transitioned by a path selection signal, similar to the connection configuration in a normal path memory circuit.

Furthermore, the flip-flops 15-1 to 15-8 are for making it possible to output the output of the previous stage in which data is transitioned every 2 symbols every l symbol. .15-6.15-8 latches the output by the path selection signal PSi-1, and flip-flops 15-1°15-3.15. -5.15-7 is for latching the output by the path selection signal PS i-2.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, (al is the data clock signal CK, fb) is the path selection signal PSi
(i=1.2, 3.4), tc) is the clock signal CLK obtained by dividing the data clock signal CK by 2, (d),
fe) is the path selection signal Psi-1 converted into two parallel
, Psi-2. The ACS circuit outputs a path selection signal PSi for each symbol as shown in (b) in synchronization with the data clock signal CK shown in (a), and the flip-flops 11-1 to 11-4, 12-1 to 12- 4, it is converted into two parallel lines. That is, the path selection signal PSi shown in (b) is ■, ■, ■, ■, (51, ■ is the odd number ■,
■,■ are (as shown in d+, path selection signal PSi-1
As shown in (e), the even numbers ■, ■, ■ become the path selection signal PSi-2.

These two parallel path selection signals Psi-1 and PSi-2 are
2-1 selector 16-i, 17 with two stages between storage elements
-t+ is simultaneously added to 18-i and 19-i, and is applied every two symbols from flip-flop 13-1 to flip-flop 14-1, and from flip-flop 14-1 to flip-flop 15-1.15-3.15-. 5. Data will be transitioned to 15-7.

And in the final stage, the flip-flop 15-2.15
After obtaining the decoded output based on the Q terminal output of -4.15-6.15-8, flip-flop 15-1.15-3.15
The decoded output will be obtained based on the Q terminal output of -5.15-7.

The above-mentioned embodiment shows the case where the path selection signal from the ACS circuit is converted into two parallel signals, and therefore two stages of 2-1 selectors are provided between the storage elements. This two-stage 2-1
Instead of a selector, two parallel path selection signals PSi-1
, Psi-2 may also be provided. That is, when converting the path selection signal PSi from the ACS circuit into n parallel signals, n stages of 2-1 selectors or 2'-1 selectors are provided between the storage elements. In addition, in the final stage, n stages of 2-1 selectors are provided in order to serially output the outputs in which n parallel survival paths are updated simultaneously, and each output is i-
It will be added to n flip-flops.

Also, in the case where a path memory circuit is constructed using the random access memories 53 and 54 shown in FIG.
With Si-n, the surviving path can be updated every n symbols. That is, the path selection signal from the ACS circuit 51 is converted into n parallel signals, and the output of the selector 27-1 is written to the random access memory, reducing the number of accesses to the random access memory in the conventional example to 1/1.
Since it is possible to reduce the number to n, it becomes possible to use a memory with a low speed operation, and when a memory with a conventional operation speed is used, the decoding speed can be increased.

〔Effect of the invention〕

As described above, the present invention includes a serial/parallel converter 3 that converts the path selection signal Psi from the ACS circuit l into n parallel signals, and a selector 5 that causes the memory element 4 to update the surviving path every n symbols. The memory element 4 is provided with n
Since it is sufficient to perform a storage operation for each symbol, if the decoding speed is the same as in the conventional example, it becomes possible to use elements operating at low speed. Therefore, the path memory circuit 2 can be configured by the CMO 3 or the like with low power consumption and high degree of integration. Furthermore, if the device is constructed using elements having the same operating speed as the conventional example, the decoding speed can be improved.

If a 2-1 selector is used as the selector 5, n stages will be provided between the memory elements 4, but even if n stages of selectors with a simpler configuration than flip-flops etc. are provided,
Since the number of storage elements 4 can be reduced to approximately 1/n compared to the conventional example, it is possible to downsize the path memory circuit 2.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of main parts of an embodiment of the invention, Fig. 3 is a diagram explaining the operation of an embodiment of the invention, and Fig. 4 is a block diagram of a Viterbi decoder. , Figure 5 is a block diagram of the branch metric calculation circuit, Figure 6 is the ACS
A block diagram of the circuit, FIG. 7 is a block diagram of the ACS circuit section, FIG. 8 is a block diagram of the main part of the conventional path memory circuit,
FIG. 9 is a block diagram of a conventional path memory circuit. ■ is an ACS circuit, 2 is a path memory circuit, 3 is a serial/parallel converter, 4 is a memory element, 5 is a selector, psl-1 to PS1
-n, PS2-1 to PS2-n are parallel-converted path selection signals, and CLK is a clock signal.

Claims (1)

[Claims] In a Viterbi decoder comprising a path memory circuit (2) to which a path selection signal from an ACS circuit (1) is applied and stores a history of a maximum likelihood path, the ACS circuit (1) ) is added to the serial/parallel converter (3) that converts the path selection signal from n parallel into n parallel, and the path selection signal converted into n parallel by the serial/parallel converter (3) is added to the memory element (4). A Viterbi decoder comprising a selector (5) for updating a path every n symbols.