JPH06204896A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To prevent constitution from being enlarged and to provide a pass memory circuit capable of a high-speed operation for facilitating making into LSI by supplying '0' and '1' to the respective pass memory cells of the initial stage of the pass memory circuit as initial values. CONSTITUTION:The pass memory circuit is constituted of a flip-flop and a selector for storing the history of a maximum likelihood pass by pass selecting signals from an ACS circuit being added. '0' and '1' are used as the initial values of the respective pass memory cells 1340-1347 of the initial stage without relying on a constraint length K and the initial values are made possible to be selected and inputted corresponding to the pass selecting signals. By turning the initial stage input value of the constraint length K to a prescribed value in such a manner, K-1 stages can be reduced. Also, by grounding one of the input terminals of the respective pass memory cells 134a-1347 to be the initial stage of the pass memory circuit and connecting the other input terminals to a constant voltage source, '0' and '1' can be supplied as the initial values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called Viterbi decoder used in a maximum likelihood decoding method for a convolutional code.

[0002]

2. Description of the Related Art A Viterbi decoder is used in the maximum likelihood decoding method of a convolutional code, and the path having the closest code distance to the input code sequence is selected from among a plurality of known code sequences. It is selected as a likelihood path and decoded data is obtained corresponding to this selected path. Since it has high error correction capability, it is used as a decoder for satellite communication, for example.

Here, a conventional Viterbi decoder, for example, as shown in FIG. 3, has a branch metric calculator 101 as a code distributor and a plurality of ACSs (Add Compare Selec).
t) a state metric calculation unit 102 including a circuit,
It comprises a path memory circuit 103 and a majority decision circuit (maximum likelihood decision circuit) 104 which obtains a decoded signal by carrying out a majority decision based on the output of the path memory circuit 103.

That is, in FIG. 3, the quadrature modulated decoded signals I and Q via the input terminals 100 _I and 100 _Q are supplied as an input code to the branch metric calculation unit 101 as the code distributor. . In the branch metric calculation unit 101, four types of branch metrics (Hamming distance) for each node are calculated from these input codes.
Branch metric B calculated by calculating BM00 to BM11
M00 to BM11 are added to the state metric calculation unit 102 in the subsequent stage.
To each ACS circuit of.

In the state metric calculator 102, assuming that the constraint length is K, the state metric for 2 ^K-1 states is calculated and 2 ^K-1 path selection signals are output. Here, assuming that the constraint length K = 4, the state metric calculation unit 102, for example, a plurality of A's as shown in FIG.
It is composed of the CS circuits 102 _{0 to} 102 ₇ .

In FIG. 4, each ACS circuit 10 described above is used.
2 ₀ In - 102 ₇ calculates a new path metric corresponding terminal 110 _{00-110 10} by adding 1 symbol previous path metrics to branch metrics BM00~BM11 inputted through the two paths, these The path metric value of S is compared by the comparator, the path with the smaller path metric is selected as the surviving path, and the path selection signal (path selection signal in the path memory in the subsequent stage) S indicating the selected path is selected.
It outputs EL0 to SEL7 and the selected path metric (state metrics SM0 to SM7). The path selection signal SEL0~SEL7 is output from the terminal 111 _{0-111 7,} the state metric SM0~SM7
Are sent to other ACS circuits.

In addition, each ACS circuit 102 _{0 to} 102
₇ is an adder (Add
er) 122 and 123, a comparator (Comparator) 126,
And a selector 127.

In FIG. 5, terminals 120 and 121 of one ACS circuit are supplied with a set of branch metrics BM, and terminals 124 and 125 of the selected pair of path metrics from another ACS circuit. (State metric SM) is supplied. The branch metric BM and the state metric SM are added by the corresponding adders 122 and 123, respectively.
The outputs from 2,123 (new path metrics corresponding to the two paths) are sent to the comparator 126. In the comparator 126, the surviving path is selected, and the path is used as a path selection signal (bus selection signal) SEL at the terminal 12
It is output from 9. The path metrics from the adders 122 and 123 are also sent to the selector 127,
The selector 127 selects the two path metrics based on the path selection signal SEL from the comparator 126. The path metric selected by the selector 127 is sent from the terminal 128 to another ACS circuit as the state metric SM.

Path selection signals (path selection signals from each ACS circuit in FIG. 4) SEL0 to SEL7 from the state metric calculation unit 102 in FIG. 3 including the ACS circuits shown in FIGS. It is sent to the memory circuit 103. The path memory circuit 103 has path selection signals SEL0 to SEL from the state metric calculator 102.
EL7 is added to memorize the history of surviving passes.

Specifically, the path memory circuit 103 has a plurality of path memory cells 131 _{0 as} shown in FIG.
To 131 _7, 132 ₀ to 132 _7, 133 _0-13
3 ₇ , ... Note that FIG. 6 shows a part of the path memory configuration when the constraint length K = 4.

Referring to FIG. 6, each ACS circuit 10 described above is used.
Path selection signal from the 2 ₀ ~102 ₇ SEL0~SEL7
The corresponding each path memory cell 131 _{0-131 7,} 132 _{0-132 7} of the path memory circuit 103, 133
_{0 to} 133 ₇ , ... Here, the first stage of the path memory cell 131 _{0-131 7} ( "0",
"0"), ("1", "1"), ("0", "0")
Initial values of (“1”, “1”) ... Are applied as inputs. Each of these path memory cells 131 _{0 to} 13
1 ₇ , 132 _{0 to} 132 ₇ , 133 _{0 to} 133 ₇ , ...
· Then, the above-mentioned first-stage path memory cells 131 _{0 to} 131 ₇
The initial value input to is shifted so that the internal state is sequentially transitioned based on the clock CLK supplied from the terminal 151 and the path selection signals SEL0 to SEL7.
That is, the ACS circuits 102 ₀ to 10 ₀ to 10 10
The contents of the path memory cell on the side determined to be the surviving path in 2 ₇ are transferred to the subsequent path memory cell using the path selection signal.

Further, each path memory cell is specifically constructed as shown in FIG. In this FIG.
The terminals 141 and 142 are supplied with the data D1 and D2 from the previous-stage path memory cell (the above-mentioned initial value for the first-stage path memory cell), and these switch the path selection signal SEL supplied through the terminal 143. It is selected by the selector 144 which is used as a control signal. The output of the selector 144 is stored in the flip-flop 145 and is output to the terminal 146.
Is shifted by the clock CLK through the. The output of the flip-flop 145 is output from the terminal 147. When such a path memory cell has a constraint length K, a total of 2 ^K-1 states × constraint length (K × 5) states are combined to form the entire path memory circuit.

The outputs from these path memory cells are shown in FIG.
Is sent to the above-mentioned majority decision circuit (maximum likelihood determination circuit) 104.
The output terminal 105 is a decoded signal in which the content of the path memory circuit 103 having the history in which the state metric SM determined by the majority decision circuit 104 is the minimum is "0" or "1".
Is output from.

The path memory configuration when the constraint length K = 7 is as shown in FIG. The 8, the path portion of the memory structure ₍₀ each path memory cell 161 of the first stage to 16
1 ₆₃ and the second stage of each path memory cell 162 _{0-162 63)}
Shows only.

As a conventional path memory circuit for a Viterbi decoder, the one described in JP-A-63-275226 can be mentioned.

[0016]

In the Viterbi decoder, the error correction capability increases as the code constraint length K increases.

However, the path memory circuit used in the above-mentioned conventional Viterbi decoder normally has, as described above, the number of states of 2 ^K-1 × constraint length (K × 5), where K is the constraint length. Since the path memory cell is configured, the size of the path memory circuit exponentially increases when the constraint length K is increased in order to improve the error correction capability. Therefore, for example, in the case of an LSI, it is very difficult to manufacture in terms of gate scale and high-speed operation.

Therefore, the present invention has been proposed in view of the above-mentioned circumstances, and can prevent an increase in size of the structure,
An object of the present invention is to provide a Viterbi decoder having a path memory circuit that can operate at high speed and can be easily integrated into an LSI.

[0019]

The Viterbi decoder of the present invention is proposed to achieve the above-mentioned object, and includes a branch metric calculator for calculating a branch metric based on an input code, and a branch metric. A state metric calculation unit including a plurality of ACS circuits that outputs a path selection signal based on the above, a path memory circuit including a plurality of path memory cells to which the path selection signal is supplied, and an output of the path memory circuit. A Viterbi decoder having maximum likelihood determination means for performing maximum likelihood determination, wherein "0" and "1" are given as initial values to each of the path memory cells at the first stage of the path memory circuit. ,
When the constraint length is K, the number of stages of the path memory cells can be reduced by K-1 stages as compared with the conventional configuration.

In other words, the path memory circuit of the Viterbi decoder of the present invention comprises a selector and a flip-flop to which the path selection signal from the ACS circuit is added to store the history of the maximum likelihood path. , "0" and "1" are used as the initial value of the first-stage path memory cell regardless of the constraint length K, and this initial value can be selectively input according to the path selection signal. Further, in the Viterbi decoder with the constraint length K, by setting the input value of the first stage of the path memory circuit to a predetermined value, K-1 stages can be reduced as compared with the conventional case.

The initial value "0" given to each of the first-stage path memory cells of the path memory circuit is the ground potential, and "1" is the power supply potential.

[0022]

According to the Viterbi decoder of the present invention, by giving "0" and "1" as the initial values to the first-stage path memory cells of the path memory circuit, when the constraint length K is K, The number of path memory cells for one stage can be reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

The Viterbi decoder of the first embodiment of the present invention is
For example, as shown in FIG.
Branch metric calculation to calculate multimetric BM
And a path selection signal based on the branch metric BM
(Bus selection signal) Multiple ACS circuits that output SEL
State metric calculation unit, and the path selection signal
A plurality of path memory cells 1 shown in FIG. 1 to which SEL is supplied
34₀~ 134₇, 135₀~ 135₇・ ・ ・ From
Path memory circuit and the output of the above path memory circuit
And a majority circuit as a maximum likelihood determination means for performing maximum likelihood determination.
A Viterbi decoder having the above-mentioned pass memo shown in FIG.
Each path memory cell 134 in the first stage of the circuit ₀~ 134₇To
Is set to give "0" and "1" as initial values
It is a thing.

In FIG. 1, the case where the constraint length K = 4 is taken as an example.

Here, in the first embodiment of the present invention,
Each path memory cell 134 ₀ to 1 in the first stage of the path memory circuit
The 34 _7, from the reasons stated below, and correct to provide the "0" and "1" as an initial value.

Description will be made with reference to FIG. As shown in FIG. 6, when the constraint length K = 4, conventionally, the first stage of the path memory cell 131 _{0-131 7} of the path memory circuit, as an initial value in the order (0,0), (1, 1), (0,0), (1,1), (0,0),
(1,1), (0,0), (1,1) is given.
That is, the path memory cell 131 ₀ is given (0, 0) as an initial value, the path memory cell 131 ₁ is (1, 1), and the path memory cell 131 ₂ is (0, 0).
However, the path memory cell 131 ₃ has (1, 1), and the path memory cell 131 ₄ has (0, 0).
The 31 ₅ (1,1), the path memory cell 131 ₆ (0,0) is in the path memory cell 131 ₇ (1,1)
Is given as an initial value.

Further, as shown in FIG. 7, each path memory cell receives the input data D1, according to the path selection signal SEL.
It has a selector 144 for switching D2. Therefore, even the selector 144 of each path memory cell 131 _{0-131 7} above the first stage, of any one of the above initial value according to the path selection signal SEL (0,0) or (1,1) "0" or "1" is selected and output.

Here, each path memory cell 13 of the first stage
1 ₀ In to 131 _7, the input data D1, since the initial value supplied as D2 is (0,0) or (1,1), each path memory cell of the first stage 131 _0-1
31 in _7, the path selection signal SEL0~SEL
Even if only one of the input data D1 and D2 is selected by 7, the output of the selector 144 is "0" or "1" corresponding to the initial value (0,0) or (1,1). Becomes Therefore, the first-stage path memory cell 131
₀ output from to 131 ₇ output terminal 147 corresponds to the (0,0) or (1,1) of the initial value is "0" or "1".

[0030] That Specifically, the path memory cell 131 ₀ outputs are always "0", the path memory cells 131 ₁ outputs always "1", and so the path memory cell 131 ₂ in FIG. 6 Is 0, the output of the path memory cell 131 ₃ is “1”, the path memory cell 131 _{4 is}
Is 0, the output of the path memory cell 131 ₅ is “1”, the output of the path memory cell 131 ₆ is “0”, and the output of the path memory cell 131 ₇ is “1”.

Next, in the path memory circuit of FIG.
The first-stage path memory cell 131 ₀Output is the second stage
Path memory cell 132₀And 132₁Each one of
Sent to the input terminal of the path memory cell 131 of the first stage.
₁Is output from the second-stage path memory cell 132₂And 132
₃Each of the input terminals of
Cell 131₃Is output from the second-stage path memory cell 132_Four
And 132_FiveTo one input terminal of each of the above
Path memory cell 131₃Output is the second pass memory
LE 132₆And 132₇To each input terminal
It is designed to be used. In addition, the above-mentioned path memory of the first stage
Cell 131_FourIs output from the second-stage path memory cell 132₀
And 132₁To the other input terminal of
Path memory cell 131_FiveOutput is the second pass memory
LE 132₂And 132₃To the other input terminal of
First-stage path memory cell 131₆Output of the second stage
Memory cell 132_FourAnd 132_FiveEach of the other
The first stage of the pass memory cell 131₇The output of
Second-stage path memory cell 132₆And 132₇That's it
It is sent to the other input terminal.

Therefore, in each of the path memory cells 132 _{0 to} 132 ₇ in the second stage, as input data D1 and D2, (0,0), (0,0), (1,1), (1 , 1), (0,0), (0,0), (1,
1), (1,1) will be given. That is, (0,0) is given to the pass memory cell 132 _0, and (0,0) is given to the pass memory cell 132 _1.
The 2 ₂ (1,1), the path memory cell 132 ₃ (1,1), the path memory cell 132 ₄ (0,0)
However, the path memory cell 132 ₅ has (0, 0) and the path memory cell 132 ₆ has (1, 1).
(1, 1) is given to 32 ₇ .

Further, each path memory cell 1 of the second stage
32 _{0-132 7} also switch the input data D1, D2 in accordance with the same manner as described above path selection signal SEL selector 144
have. Therefore, the selector 144 of each of the path memory cells 132 _{0 to} 132 _{7 in} the second stage also selects (0,0) or (1,1) of the input data D1 and D2 according to the path selection signal SEL. Either "0" or "1" is selected and output.

Here, each path memory cell 1 of the second stage
Also in the case of 33 _{0 to} 133 ₇ , the input data D
The value supplied as 1, D2 is (0, 0) or (1,
Therefore, in each of the path memory cells 132 _{0 to} 132 ₇ in the second stage, the path selection signal SE
Even if only one of the input data D1 and D2 is selected by L0 to SEL7, the output of the selector 144 corresponds to (0,0) or (1,1) supplied as the input data D1 and D2. "0" or "1"
Becomes Therefore, the second-stage path memory cells 132 _0-
The output from the output terminal 147 of 132 ₇ is also "0" or "1" corresponding to (0,0) or (1,1) of these input data D1 and D2.

Specifically, the path memory cell 13
Two₀The output of will always be "0", and so on.
Cell 132₁Output becomes "0" and the path memory cell 1
32 ₂Is "1", the path memory cell 132₃Output
Is “1”, the path memory cell 132_FourOutput is "0",
Memory cell 132_FiveOutput is "0", pass memory cell
132₆Is "1", the path memory cell 132₇Out of
The power becomes "1".

In the path memory circuit,
Second-stage path memory cell 132 ₀Output of the third stage
Path memory cell 133₀And 133₁Each one of
It is sent to the input terminal, and the path memory cell 132₁Output
Is the third-stage path memory cell 133₂And 133₃That of
The path memory cell 132 is connected to one of the input terminals.₃of
The output is the third-stage path memory cell 133._FourAnd 133_Fiveof
The path memory cell 132 is connected to one of the input terminals.
₃Is output from the third stage path memory cell 133₆And 133
₇Are sent to one of the input terminals
It In addition, the path memory cell 132_FourOutput is the third stage
Path memory cell 133₀And 133₁Each of the other
To the input terminal of the path memory cell 132_FiveOutput is 3
Stage memory cell 133 of the stage₂And 133₃Each of
The path memory cell 132 is connected to the other input terminal.₆Output
Is the third-stage path memory cell 133_FourAnd 133_FiveThat of
The path memory cell 132 is connected to the other input terminal.₇of
The output is the third-stage path memory cell 133.₆And 133₇of
Each is sent to the other input terminal.

Therefore, in each of the path memory cells 133 _{0 to} 133 ₇ in the third stage, as input data D1 and D2, (0,0), (0,0), (0,0), (0 , 0), (1,1), (1,1), (1,
1), (1,1) will be given. That is, (0,0) is given to the pass memory cell 133 _0, and (0,0) is given to the pass memory cell 133 _1.
3 ₂ has (0,0), path memory cell 133 ₃ has (0,0), and path memory cell 133 ₄ has (1,1).
However, the path memory cell 133 ₅ has (1,1), and the path memory cell 133 ₆ has (1,1).
(1, 1) is given to 33 ₇ .

Further, each path memory cell 1 of the third stage
Similarly to 33 _{0 to} 133 _{7, the} selector 144 for switching the input data D1 and D2 in accordance with the path selection signal SEL is similar to the above.
Since each path memory cell 13 in the third stage has
Even 3 _{0-133 7} of the selector 144, the input data D1, D2 (0, depending on the path selection signal SEL,
"0" or "1" of either 0) or (1,1)
Will be selected and output.

Here, each path memory cell 1 of the third stage
Also in the case of 33 _{0 to} 133 ₇ , the input data D
The value supplied as 1, D2 is (0, 0) or (1,
1), the path select signal SE is applied to the path memory cells 133 _{0 to} 133 ₇ in the third stage.
Even if only one of the input data D1 and D2 is selected by L0 to SEL7, the output of the selector 144 corresponds to (0,0) or (1,1) supplied as the input data D1 and D2. "0" or "1"
Becomes Therefore, the third-stage path memory cells 133 _0-
The output from the output terminal 147 of 133 ₇ is also "0" or "1" corresponding to (0,0) or (1,1) of these input data D1 and D2.

Specifically, the path memory cell 13 described above is used.
3 _0-133 Each output of ₃ always "0", the output of the path memory cell 133 _{4-133 7} becomes always "1".

In the path memory circuit,
The path memory cell 133 of the third stage ₀Output of the 4th stage
Path memory cell 134₀And 134₁Each one of
Sent to the input terminal, the path memory cell 133₁Output
Is the fourth-stage path memory cell 134₂And 134₃That of
The path memory cell 133 is connected to one of the input terminals.₃of
The output is the fourth-stage path memory cell 134._FourAnd 134_Fiveof
The path memory cell 133 is connected to one of the input terminals.
₃Is the output of the fourth pass memory cell 134₆And 134
₇Are sent to one of the input terminals
It In addition, the path memory cell 133_FourOutput is the 4th stage
Path memory cell 134₀And 134₁Each of the other
To the input terminal of the path memory cell 133_FiveOutput is 4
Stage memory cell 134₂And 134₃Each of
The path memory cell 133 is connected to the other input terminal.₆Output
Is the fourth-stage path memory cell 134_FourAnd 134_FiveThat of
The path memory cell 133 is connected to the other input terminal.₇of
The output is the fourth-stage path memory cell 134.₆And 134₇of
Each is sent to the other input terminal.

[0042] Therefore, each path memory cell 134 _{0-134 7} of the fourth stage, as the input data D1, D2, sequentially (0,1), (0,1), (0,1), (0 , 1), (0,1), (0,1), (0,
1), (0,1) will be given. That is, each of the input data D1, D2 (0, 1) is given all the path memory cell 134 _{0-134 7.}

Each of the fourth-stage path memory cells 134 ₀
.About.134 ₇ also have a selector 144 for switching the input data D1 and D2 in accordance with the path selection signal SEL as in the above, and therefore each of the fourth-stage path memory cells 134 ₀ 〜
134 even ₇ of the selector 144, this path selection signal SE
Depending on L, either "0" or "1" of (0, 1) of the input data D1 and D2 is selected and output.

[0044] That is, since each path memory cell 134 _{0-134 7} of the fourth stage, the input data D1, D2 respectively supplied has a (0,1), each path of the fourth stage value output from the memory cell 134 _{0-134 7,} each path memory cell 134 _0-134 every ₇ in response to the path selection signal SEL0 to SEL7 "0"
Alternatively, it is either "1".

The above description will be summarized below with reference to FIG.
In the path memory circuit with the constraint length K = 4 of each of the path memory cells 131 ₀
To 131 _7, 132 ₀ to 132 _7, 133 _0-13
3 ₇ , 133 ₀ to 133 ₇ input data (D1, D
2) are, in order, the first stage (0,0), (1,1), (0,0), (1,1), (0,0), (1,1), (0,
0), (1,1) 2nd stage (0,0), (0,0), (1,1), (1,1), (0,0), (0,0), (1,
1), (1,1) 3rd stage (0,0), (0,0), (0,0), (0,0), (1,1), (1,1), (1,
1), (1,1) 4th stage (0,1), (0,1), (0,1), (0,1), (0,1), (0,1), (0,
It becomes 1), (0,1).

That is, each path memory cell in the fourth stage
134₀~ 134₇Is from the first stage (first stage) to the third stage
Each path memory cell 131₀~ 131₇, 132₀~ 1
32 ₇, 133₀~ 133₇Unlike the case of "0"
Can output any one of "1".

In other words [0047], each path memory cell 131 from the first stage to the third stage _{0-131 7,} 132 _0-13
In 2 ₇ , 133 _{0 to} 133 ₇ , the path selection signal SEL0
It can be seen that each output is constant regardless of which state of SEL7 is "0" or "1".
4 stage only for each path memory cell 134 _{0-134 7,} described above in the order as the initial value (0,1), (0,1), (0,1), (0,
1), (0,1), (0,1), (0,1), (0,1) are given, the respective path memory cells 131 _{0 to} 131 _{0 to} 13
1 _7, 132 _{0-132 7,} 133 _{0-133 7} it can be seen that it is possible to omit.

Therefore, in this embodiment, as shown in FIG.
As shown in FIG. 4, when the constraint length K = 4, 4 in FIG.
Of each path memory cell 134 _{0-134 7} corresponding to stage the (K (4)) as a first stage, each of these path memory cell 1
34 _{0-134 7} is to give as described above the (1,0) as the initial value.

As a result, in the present embodiment, compared with the conventional configuration of FIG. 6, the first stage to the third stage of FIG. 6 can be reduced, so that the configuration can be downsized and the number of these stages can be reduced. A path memory circuit that can operate at high speed and can be easily integrated into an LSI can be realized. Further, according to the present embodiment, even if the first stage to the third stage of FIG. 6 are reduced, the input data to the fourth stage (first stage of the present embodiment) does not change, so the decoding result (the final stage of the path memory) Output) does not deteriorate at all.

In FIG. 1, the fourth and subsequent stages (K
Although (4) to K + 4 (8) have the same configuration, they will be briefly described below.

The path memory cell 134 ₀ of the fourth stage
Is output from the fifth stage path memory cells 135 ₀ and 135 _1.
Each is sent to one input terminal of the output of the path memory cell 134 ₁ is the path memory cell 135 ₂ and 135
_The above-mentioned path memory cell 1 is connected to one of the _three input terminals.
The output of 34 ₃ is input to one input terminal of each of the pass memory cells 135 ₄ and 135 ₅ and
The output of ₃ is sent to one input terminal of each of the path memory cells 135 ₆ and 135 ₇ . The output of the path memory cell 134 ₄ is applied to the other input terminals of the path memory cells 135 ₀ and 135 ₁ , respectively.
The output of the pass memory cell 134 ₅ is the pass memory cell 1
The output of the path memory cell 134 ₆ is applied to the other input terminal of each of 35 ₂ and 135 ₃
The output of the path memory cell 134 ₇ is sent to the other input terminal of each of ₄ and 135 _{5 and} the other input terminal of each of the path memory cells 135 ₆ and 135 ₇ .

Each path memory cell 135 ₀ of the fifth stage
The input data D1 and D2 provided to each of the ˜135 ₇ are selected according to the path selection signals SEL0 to SEL7, and
The value output from each of the path memory cells 135 _{0 to} 135 ₇ of the stage becomes either “0” or “1” for each of the path memory cells 135 _{0 to} 135 ₇ according to the path selection signal SEL.

The path memory cell 135 ₀ of the fifth stage
Is output from the sixth-stage path memory cells 136 ₀ and 136 _1.
Of the path memory cells 135 ₁ and 136 ₂ and 136.
_The above-mentioned path memory cell 1 is connected to one of the _three input terminals.
The output of 35 ₃ is input to one input terminal of each of the path memory cells 136 ₄ and 136 ₅ and the above-mentioned path memory cell 135 3
The output of ₃ is sent to one input terminal of each of the path memory cells 136 ₆ and 136 ₇ . The output of the path memory cell 135 ₄ is applied to the other input terminals of the path memory cells 136 ₀ and 136 ₁ , respectively.
The output of the pass memory cell 135 ₅ is the pass memory cell 1
The output of the pass memory cell 135 ₆ is applied to the other input terminals of the pass memory cells 136 ₂ and 136 ₃ respectively.
The output of the pass memory cell 135 ₇ is sent to the other input terminal of each of ₄ and 136 ₅ , and the other input terminal of each of the pass memory cells 136 ₆ and 136 ₇ .

Each path memory cell 136 ₀ of the sixth stage
The input data D1 and D2 given to ˜136 ₇ are selected according to the path selection signals SEL0 to SEL7, and
The value output from each of the path memory cells 136 _{0 to} 136 ₇ of the stage becomes either “0” or “1” for each of the path memory cells 136 _{0 to} 136 ₇ according to the path selection signal SEL.

The sixth-stage path memory cell 136 ₀
Is the output of the seventh stage path memory cells 137 ₀ and 137 _1.
Of the path memory cells 136 ₁ and 137 ₂ and 137.
_The above-mentioned path memory cell 1 is connected to one of the _three input terminals.
The output of 36 ₃ is input to one of the input terminals of each of the path memory cells 137 ₄ and 137 ₅ , and the path memory cell 136
The output of ₃ is sent to one input terminal of each of the path memory cells 137 ₆ and 137 ₇ . The output of the path memory cell 136 ₄ is applied to the other input terminals of the path memory cells 137 ₀ and 137 ₁ , respectively.
The output of the pass memory cell 136 ₅ is the pass memory cell 1
The output of the path memory cell 136 ₆ is applied to the other input terminal of each of 37 ₂ and 137 ₃ , and
The output of the path memory cell 136 ₇ is sent to the other input terminal of each of ₄ and 137 ₅ , and the other input terminal of each of the path memory cells 137 ₆ and 137 ₇ .

Each path memory cell 137 ₀ of the seventh stage
To 137 ₇ input data D1, D2 given to is selected according to the path selection signal SEL0 to SEL7, the 7
The value output from each of the path memory cells 137 _{0 to} 137 ₇ of the stage becomes either “0” or “1” for each of the path memory cells 137 _{0 to} 137 ₇ according to the path selection signal SEL.

The path memory cell 137 ₀ of the seventh stage
Is output from the eighth stage path memory cells 138 ₀ and 138 ₁
Of the path memory cells 137 ₁ and 138 ₂ and 138.
_The above-mentioned path memory cell 1 is connected to one of the _three input terminals.
The output of 37 ₃ is input to one of the input terminals of the path memory cells 138 ₄ and 138 ₅ , respectively, and
The output of ₃ is sent to one input terminal of each of the path memory cells 138 ₆ and 138 ₇ . The output of the path memory cell 137 ₄ is applied to the other input terminals of the path memory cells 138 ₀ and 138 ₁ , respectively.
The output of the path memory cell 137 ₅ The path memory cell 1
The output of the path memory cell 137 ₆ is connected to the other input terminal of each of 38 ₂ and 138 ₃ ,
The output of the path memory cell 137 ₇ is sent to the other input terminal of each of ₄ and 138 ₅ , and the other input terminal of each of the path memory cells 138 ₆ and 138 ₇ .

Each path memory cell 138 ₀ of the eighth stage
Input data D1 and D2 given to 138 ₇ are selected according to the path selection signals SEL0 to SEL7.
The value output from each of the path memory cells 138 ₀ to 138 ₇ of the stage becomes either “0” or “1” for each of the path memory cells 138 ₀ to 138 ₇ according to the path selection signal SEL.

Each of the eighth-stage path memory cells 138 _0-
138 ₇ output and each path selection signal SEL0 to SEL
7 is sent to the latter stage configuration.

The theory described in the above embodiment of FIG. 1 holds regardless of the constraint length K. For example, in the above description, the case where the constraint length K = 4 is described, but the same effect can be obtained even when the constraint length K = 7.

As a second embodiment, the constraint length K is shown in FIG.
An example when = 7 is shown.

That is, normally, 1 when the constraint length K = 7.
Although the stages are composed of path memory cells for 64 states, this embodiment applies the above-described present invention to the first stage (K (7) in the figure).
By setting the initial value given to each of the path memory cells 167 _{0 to} 167 ₆₃ in the (stage) to (D1, D2) = (0, 1), it is possible to reduce the number of path memory cells for 6 stages as compared with the conventional case. Although the path selection signal SEL and the clock signal line to each path memory cell are omitted in FIG. 2, the structure of each path memory cell is the same as that in FIG. 1 with the constraint length K = 4 described above.

According to each of the above-described embodiments, the initial values given to the first stage (stage K (4) in FIG. 1 and stage K (7) in FIG. 2) are respectively set as described above. By setting 0, 1), it is possible to reduce the number of K−1 stages of pass memory cells as compared with the conventional technique, and the decoding result (the output of the last stage of the pass memory) is never deteriorated. That is, in the case of the constraint length K = 4 in FIG. 1, it is possible to reduce three steps as compared with the conventional case, and in the case of the constraint length K = 7 in FIG. Especially, constraint length K = 7
In the case of, it is possible to reduce 6 stages x 64 states, so L
It is very advantageous for SI conversion.

In each of the above embodiments, the path
The first stage of the memory circuit (the K (4) th stage in the diagram of FIG. 1 and the diagram of FIG. 2)
One of the above for each path memory cell that is the middle K (7th)
Ground the input terminal (GND potential, ground potential) and input the other
Input terminal to a constant voltage source (V_CC, V _DD, For example 5V)
By setting the above, each path memory cell of
The values are "0" (that is, Low level) and 1 "(
That is, a high level can be given. to this
Therefore, it is necessary to provide new means to generate the initial value.
Disappear.

[0065]

As described above, according to the present invention, "0" and "1" are given as initial values to the first-stage path memory cells of the path memory circuit, thereby increasing the size of the structure. It is possible to realize a Viterbi decoder having a path memory circuit that can prevent the above, can operate at high speed, and can be easily integrated into an LSI.

[Brief description of drawings]

FIG. 1 is a block circuit diagram for explaining each path memory cell and an initial value of a path memory circuit of a Viterbi decoder with a constraint length K = 4 according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining each path memory cell having a constraint length K = 7 and an initial value according to a second embodiment.

FIG. 3 is a block circuit diagram showing the overall configuration of a Viterbi decoder.

FIG. 4 is a block circuit diagram showing an overall configuration of a state metric calculation unit.

FIG. 5 is a block circuit diagram showing a specific configuration of an ACS circuit.

FIG. 6 is a diagram for explaining each conventional path memory cell having a constraint length K = 4 and an initial value.

FIG. 7 is a block circuit diagram showing a specific configuration of a path memory cell.

FIG. 8 is a diagram for explaining each conventional path memory cell having a constraint length K = 7 and an initial value.

[Explanation of symbols]

101 ... Branch metric calculation unit 102 ... State metric calculation unit 103 ... Path memory circuit 104 ... Majority decision circuit (maximum likelihood determination circuit) 134, 135, 136, 137, 138 ...・ Pass memory cell

Claims (2)

[Claims] 1. A branch metric calculator that calculates a branch metric based on an input code, and a plurality of ACSs that outputs a path selection signal based on the branch metric.
A state metric calculation unit including a circuit, a path memory circuit including a plurality of path memory cells to which the path selection signal is supplied, and a maximum likelihood determination unit that performs maximum likelihood determination on the output of the path memory circuit. In the Viterbi decoder, "0" and "1" are given as initial values to the first-stage path memory cells of the path memory circuit, respectively. 2. The initial value "0" given to each of the first-stage path memory cells of the path memory circuit is a ground potential, and "1" is a power supply potential.
Viterbi decoder as described.