CN114927156A - Shift register method and shift register structure comprising redundant storage unit - Google Patents
Shift register method and shift register structure comprising redundant storage unit Download PDFInfo
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- CN114927156A CN114927156A CN202210856034.5A CN202210856034A CN114927156A CN 114927156 A CN114927156 A CN 114927156A CN 202210856034 A CN202210856034 A CN 202210856034A CN 114927156 A CN114927156 A CN 114927156A
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- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G11C7/106—Data output latches
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G11C7/1087—Data input latches
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Abstract
The invention discloses a shift register method and a shift register structure comprising redundant storage units, wherein the method comprises the following steps: designing and determining the number of required clocks and the number of required latches; according to the number of required clocks, sequentially dividing the latches into a plurality of latch unit groups containing the same number of latches, wherein each latch unit group contains the number of latches and is equal to the number of clocks; setting the same sequential latch in each latch unit group as a redundant unit; configuring a respective delay for each clock; configuring a next-stage data acquisition circuit, and connecting the data acquisition circuit with each latch except the redundant unit in each latch unit group; therefore, the area of the chain type shift register structure can be reduced, and the overall power consumption of the shift register structure is reduced.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a shift register method and a shift register structure comprising redundant storage units.
Background
In DRAM design, in order to improve the yield, it is a common practice to provide redundant memory cells, such that when a defective memory cell is found in a test stage, a specific redundant memory cell is designated, and the designated redundant memory cell is set by a fuse to replace the defective memory cell. However, in practical applications, the fuse is located at a position separated from the position required by the setting value of the fuse. In DRAM, a shift register is used to load store and transfer fuse values of fuses. However, the number of fuse values to be loaded, stored and transferred in the DRAM chip may reach thousands or more, and the area and power consumption of the shift register for loading and storing these fuse values become the first technical problems to be considered in this field.
Taking the edge triggered chain type shift register structure in the prior art as an example, based on different types of selected flip-flops, the process of transferring data from one register to the next register is realized on the rising edge or the falling edge of a clock, fig. 1 is a schematic diagram showing the shift register principle of the shift register in the conventional structure, and the selected part of the frame in fig. 1 is the data array stored in the latch when the data loading and transmission are completed. Referring to fig. 1, taking a shift register for loading and storing 8-bit data as an example, the conventional flip-flop chain shift register is configured with a single clock which serially transfers data in a predetermined position and order, as shown in the frame, from Q at the last falling edge of the clock 7 To Q 0 The data stored in the 8 flip-flops is D 0 To D 7 Thus, in this example, the loading and storing of 8 bits of data is completed over 8 clock cycles. It is contemplated that as the number of data bits that need to be stored increases, then correspondingly more flip-flops and longer time periods are required to complete the loading and storing of the entire data. Obviously, the area of the shift register is reduced, and the power consumption thereof is reduced, which is a main direction of technical improvement.
As a further improvement, the prior art further proposes a shift register using pulse latches as shown in fig. 2. If only latches are used in such a shift register, all latches will be transparent as soon as the clock goes from high to low or from low to high, and the data will start to end immediately. Referring to fig. 2, the shift register structure includes 5 latches and is provided with 4 clocks. In the initial state, the 5 latches are sequentially the first latch to the fifth latch from left to right, and sequentially store data of (N-2, N-1, N, N +1, N + 2), the post latch takes the output of the pre latch as input according to the sequence from CLK3 to CLK0, and when the clock is switched to CLK0 again, the data in the fourth latch and the fifth latch are the same and are both N + 1.
Therefore, for a shift register using pulse latches, configuring the latches with delays becomes an indispensable design step. Accordingly, in order to implement the delay design under this structure, an additional delay unit needs to be configured to implement the delay of the data or the clock between two adjacent latches. When thousands of fuse values need to be stored, the additional delay unit is also contrary to the design concept of reducing the area of the shift register.
In summary, the prior art should be improved to solve the technical problems of low area utilization and large overall power consumption of the existing shift register structure, and at the same time, to solve the delay problem of the shift register using the pulse latch.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a shift register method and a shift register structure which can reduce the area of a chain type shift register structure and reduce the overall power consumption of the shift register structure and comprise redundant storage units.
In order to solve the above technical problem, the present invention adopts a shift register method including a redundant memory cell, the shift register method including the steps of: step S1, designing and determining the number of the needed clocks according to the number of the data bits to be stored, and then designing and determining the number of the needed latches; step S2, sequentially dividing the latches into a plurality of latch unit groups including the same number of latches according to the number of required clocks, wherein the number of latches included in each latch unit group is equal to the number of clocks determined by design; a step S3 of setting the same sequential latch in each latch unit group as a redundant unit; a step S4 of configuring a corresponding delay for each of the clocks; a step S5 of configuring a data obtaining circuit of a next stage and connecting the data obtaining circuit to each latch except the redundant cell in each latch cell group; step S6, after the data shift storage is completed, the data obtaining circuit obtains the data in each latch except the redundant cell in the latch cell group.
Preferably, in step S2, the step of sequentially dividing the latches into a plurality of latch unit groups including the same number according to the required number of clocks is specifically: when the number of the required clocks is determined to be N by design, and M latches are adopted, the M latches are divided into H latch unit groups, each latch unit group comprises N latches, wherein H is a value obtained by dividing M by N and then rounding up.
Further preferably, in step S3, the step of defining the same sequential latch in each latch unit group as a redundant unit specifically includes: for H latch unit groups, respectively defining N latches in each group as { Q 0 、Q 1 、Q 2 …Q N-2 、Q N-1 And sets the corresponding sequential latch Q in each group n Are redundant units.
Still further preferably, the last latch in each of said groups of latch units is set as a redundant cell.
Still preferably, in step S4, before the step of configuring a delay for each clock, the method further includes a step of sequentially corresponding each clock to the same sequential latch in each latch unit group, and setting N clocks to { CLK } 0 、CLK 1 、CLK N-2 、CLK N-1 And for any clock CLKx in the N clocks, which respectively corresponds to the X +1 th latch in each latch unit group and sends a clock signal, where X is an integer less than or equal to N-1, where a clock cycle of the N clocks is set to TCK, and for any clock in the N clocks, it lags behind (N-1)/N × TCK cycles compared with an adjacent previous clock.
Still further preferably, before the step S6, the method further includes: and configuring a pulse counter for each clock, and setting the pulse counter to stop after reaching a preset count.
Correspondingly, the present invention further provides a shift register structure based on the shift register method including the redundant memory unit, and the shift register structure includes: the latches are sequentially connected to form a latch chain, the input of any latch is connected with the output of the previous-stage latch, the latches are divided into a plurality of latch unit groups, and one latch at the same position in each latch unit group is a redundant unit; the data acquisition circuit is connected with the latches except the redundant unit in each latch unit group, wherein the clock period of N clocks is set to be TCK, and for any one clock in the N clocks, the clock lags behind (N-1)/N TCK periods compared with the adjacent previous clock, and after the data shifting and storing are completed, the data acquisition circuit acquires data.
Preferably, the last latch in each said group of latch cells is a redundant cell.
Still preferably, N of the clocks are set to { CLK 0 、CLK 1 …CLK N-2 、CLK N-1 And for any clock CLKx in the N clocks, it corresponds to the X +1 th latch in each latch unit group and sends a clock signal.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial technical effects:
1. the invention solves the technical problems of low area utilization and large overall power consumption of the existing shift register structure, and divides a plurality of latches contained in a latch chain into groups and selects the latch with a fixed position in a latch unit group as a redundant latch unit. The redundant latch unit is only used for moving data in the data transmission process and is not connected with the next-stage data acquisition circuit, so that the transmitted data is correct, and data conflict caused by clock switching is eliminated; in another aspect, compared with the shift register structure in the prior art, the shift register structure has the advantages that delay is realized by setting up the redundant latch unit and abandoning a clock, so that the shift register structure does not need to be provided with an additional delay unit as in the prior art, and the design area of the shift register is reduced in two aspects;
2. compared with the shift register method and structure in the prior art, when the data with the same number of bits is transmitted, the shift register method and structure reduce the number of required latches by increasing the clock, improve the utilization efficiency of the latches, and also achieve the technical purpose of reducing the design area of the shift register structure;
3. in the structure, the latches in the latch chain are grouped according to the number of the adopted clocks to form a plurality of latch unit groups containing the same number of latches, the number of the latches contained in each latch unit group is consistent with the number of the adopted clocks, for any clock CLKx in N clocks, the latches respectively correspond to the X +1 th latch in each latch unit group and transmit clock signals, thus, when a clock pulse arrives, only the latch corresponding to the current clock can change the state, for the shift register structure of M latches adopting N clocks, only M/N latches in one clock pulse can change the state, compared with the structure of the prior art, when each rising edge or falling edge, all triggers or latches can change the state, the peak current when the latches are switched is obviously reduced, meanwhile, the overall power consumption of the shift register structure is reduced.
Drawings
Fig. 1 is a schematic diagram illustrating a shift storage principle of a shift register in a conventional structure;
FIG. 2 is a schematic diagram showing a shift register structure using pulse latches;
FIG. 3 is a diagram illustrating a shift register structure including redundant memory cells according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating the shift register principle for loading and storing 8 bits of data using 3 clocks and 12 latches in the first embodiment;
FIG. 5 is a diagram illustrating a shift register structure including redundant memory cells according to a second embodiment of the present invention;
FIG. 6 is a diagram illustrating a shift register structure including redundant memory cells according to a fourth embodiment of the present invention;
fig. 7 is a diagram illustrating a shift register principle of loading and storing 9-bit data using 4 clocks and 12 latches in the fourth embodiment;
fig. 8 is a flowchart illustrating a flow of a shift register method including redundant memory cells according to a fifth embodiment.
Detailed Description
Embodiments of a shift register method and a shift register structure including redundant memory cells according to the present invention will be described with reference to the accompanying drawings. Those of ordinary skill in the art will recognize that the described embodiments can be modified in various different ways, without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are illustrative in nature and not intended to limit the scope of the claims. Furthermore, in the present description, the drawings are not to scale and like reference numerals refer to like parts.
It should be noted that, in the embodiments of the present invention, the expressions "first" and "second" are used to distinguish two entities with the same name but different names or different parameters, and it should be understood that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and no description thereof is provided in the following embodiments.
The preferred embodiment of the invention is provided for solving the technical problems of large area, low latch utilization rate and high overall peak power consumption when clock pulses arrive in the shift register method and structure in the prior art. In addition, the scheme of implementing delay between clocks by using an additional delay unit also causes an increase in the area of the shift register structure, so that the preferred embodiment of the present invention tries to increase the utilization rate of the latches under the chain-type shift register structure by increasing the clocks, and adds a redundancy unit in the shift register structure, thereby ensuring the correct rate of data shift register and implementing the delay effect by replacing the delay unit.
Referring to FIG. 2, when switching to CLK again, as previously described 0 In this case, two latches having the same data exist in the latch chain, i.e., the fourth latch and the fifth latch in the example shown in fig. 2, and in this case, the data cannot be stored correctly. The idea of a preferred embodiment of the invention is to consider one of the two latches in which the same data is present as redundant (dummy), i.e. the redundant latch is only used to shift data, and the data stored in it is not acquired during data acquisition, in other words, the data acquisition circuit is not connected to the redundant latch, thus allowing the redundant latch to be ignored when acquiring data.
Referring back to FIG. 2, according to CLK 3 To CLK 0 The post latch takes the output of the pre latch as input and switches to CLK again 0 Then, the data in the fourth latch and the fifth latch are the same and are both N + 1. Then if CLK 3 The corresponding latch is defined as redundant, and when the data is acquired, one bit of data stored in the latch is ignored, and the acquired data is consistent with the pre-loaded data. Based on this idea, the preferred embodiment of the present invention applies the method of selecting one latch in the latch unit group as a redundant latch and ignoring the data therein during data acquisition to the scenario of using a shift register structure with more latches to transmit more bits of data.
Example one
In one aspect of the invention, a shift register structure including redundant memory cells is provided. Referring to fig. 3, fig. 3 is a diagram illustrating a shift register structure including redundant memory cells according to a first embodiment of the present invention. As shown in the figure, the shift register structure described in the first embodiment is formed by connecting 12 latches in sequence to form a latch chain, and in this embodiment, a process of loading and storing 8 bits of data by using 3 clocks is taken as an example.
Define 12 latches as q 0 、q 1 、q 2 …q 9 、q 10 、q 11 Of the 12 latches, the latch is selected,the output of each latch corresponds to the input of the preceding latch. In the preferred embodiment of the present invention, each shift register structure is designed and selected according to the requirements of chip design and data transmission, and the number of latches included in each latch unit group corresponds to the number of clocks used. Then, in the first embodiment, since 3 clocks are selected for design and then 3 latches are correspondingly included in each group when the latches are correspondingly grouped, the group of the latches is defined as a latch unit group in the preferred embodiment of the present invention. 4 groups of latch units are defined as { Q 1 、Q 2 、Q 3 、Q 4 Each latch unit group comprises 3 latches respectively, and the last latch in the three latches of each latch unit group is set as a redundant unit (dummy). Then, specifically, latch the cell group Q 1 In (c) contains { q 0 、q 1 、q 2 Wherein q is 2 Is a redundant unit; latch unit group Q 2 In (c) contains { q 3 、q 4 、q 5 Wherein q is 5 Is a redundant unit; latch unit group Q 3 In (c) contains { q 6 、q 7 、q 8 Wherein q is 8 Is a redundant unit; latch unit group Q 4 In (c) contains { q 9 、q 10 、q 11 Wherein q is 11 Are redundant units.
3 clocks, each defined as CLK 0 、CLK 1 、CLK 2 . Wherein, CLK 0 Respectively connected with the latch unit group Q 1 Latch Q0 in (1) and latch unit group Q 2 Latch q in (1) 3 And latch unit group Q 3 Latch q in (1) 6 And a latch unit group Q 4 Latch q in (1) 9 Corresponds and transmits the clock signal. Referring to FIG. 3, and so on, CLK 1 Respectively connected with latch unit group Q 1 Latch q in (1) 1 Latch unit group Q 2 Latch q in (1) 4 Latch unit group Q 3 Latch q in (1) 7 And a latch unit group Q 4 Latch q in (1) 10 Corresponding and sending a clock signal; CLK 2 Respectively connected with latch unit group Q 1 Latch q in (1) 2 Latch unit group Q 2 Latch q in (1) 5 Latch unit group Q 3 Latch q in (1) 8 And a latch unit group Q 4 Latch q in (1) 11 Corresponds to and transmits a clock signal.
CLK 0 、CLK 1 、CLK 2 Is equal, in the first embodiment, CLK is set 1 Compared with CLK 0 Delayed by 2/3 clock cycles, correspondingly resulting in CLK 2 Compared with CLK 1 And then delayed for 2/3 cycles. Referring to fig. 4, fig. 4 is a schematic diagram illustrating the shift register principle of loading and storing 8-bit data using 3 clocks and 12 latches in the first embodiment. According to the first switching CLK 0 Then switching CLK again 1 Finally CLK 2 When a clock signal comes, one third of the 12 latches simultaneously changes state, and in the process of changing state, the one third latches take the output of the latch at the previous stage as the input of the latch and store the output. At any time during the shifting process, there are two latches of the same data in any three adjacent latches of the 12 latches. According to the shift principle of the latch, referring to FIG. 4, after 8 clock cycles, the redundant cell { q } 2 、q 5 、q 8 、q 11 The data stored in the latches at the previous stages are the same as the data stored in the latches at the previous stages, and the loading and storing processes of 8-bit data are completed.
And the data acquisition output is completed by the next-stage data acquisition circuit. Typically, a data acquisition circuit should communicate with the output of each latch in the chain of latches to acquire one bit of data stored in each latch. However, in the preferred embodiment of the invention, the data acquisition circuit is in communication with the output of each latch in sequence, except for the redundant cells, so that data stored in the redundant cells and considered redundant is ignored during operation of the acquisition circuit to ensure that the data in the remaining latches is consistent with the data to be loaded and stored. Due to the characteristics of shift register, when the data obtained from the latch is different in different clock pulses, it is necessary to determine whether the data shift storage is completed or not, or at what time to obtain the data in the latch. In this embodiment, a pulse counter, such as an accumulation counter, is configured for each clock, and a preset value is set for the pulse counter according to the number of bits of the transmission data, and when the pulse counter reaches the preset value, a signal is generated to stop the corresponding clock. When all the clocks are stopped, the data in the latch is fixed at the moment, and the data acquisition circuit acquires the data in the latch except the redundancy unit at the moment.
Referring back to fig. 1, the shift register of the flip-flop chain structure in the prior art requires 8 clock cycles of 1 clock to load and stores 8 bits of data through 16 latches (1 register includes 2 latches). Every clock comes, all 8 registers will change their state, and the peak power consumption is high. In addition to overcoming the problem of data redundancy, the technical solution in the first embodiment adopts 12 latches and loads 8 bits of data through 3 clocks. On one hand, data with the same length bit number is transmitted, the number of latches is reduced, and the area of a shift register structure is reduced; on the other hand, when a clock pulse arrives, only 4 latches will change their state and the peak power consumption will be significantly reduced.
Example two
For each group of latch cells, in embodiment one, the latches that are the last bit of each group are designed as redundant cells. In other preferred embodiments of the present invention, the positions of the redundant cells in each group of latch cells may be different.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a shift register structure including redundant memory cells according to a second embodiment of the present invention. The 3 latches are sequentially connected to form a latch chain, and 2-bit data is loaded and stored by adopting 3 clocks. In the second embodiment, three latches in the latch chain are defined as a first latch 100, a second latch 200, and a third latch 300, respectively, in order from left to right. Unlike the first embodiment, in the second embodiment, the second latch 200 is regarded as a redundant cell (dummy).
Setting three clocks in the second embodiment to be CLK correspondingly 0 、CLK 1 、CLK 2 . Wherein, CLK 0 Corresponding to the second latch 200 and transmitting the clock signal, CLK 1 Corresponds to the first latch 100 and transmits a clock signal, CLK 2 Corresponds to the third latch 300 and transmits a clock signal. The clock periods of the three clocks are equal and still set to CLK 1 A delay of 2/3 clock cycles compared to CLK0, correspondingly causing CLK 2 Compared with CLK 1 And then delayed for 2/3 cycles. In the shift register process of the shift register structure according to the second embodiment, the data stored in each latch changes with the clock signal as shown in the following table.
As in the first embodiment, the next stage of data acquisition circuitry is still in communication with the output of each latch in sequence, except for the redundant cells. Then, referring to the table above, it can be seen that the next CLK 0 At the time of arrival, although the second latch is the same as the data stored in the first latch, since the second latch is a redundant cell and is not in communication with the data acquisition circuit, at a second CLK 0 And acquiring data after arrival, namely obtaining correct data.
Of course, in the example of the second embodiment, it is also possible to set the first latch 100 of the three latches as a redundant cell, and accordingly set the clock corresponding to the first latch to CLK 0 And the data acquisition circuit is only corresponding to the second latch and the third latch.
EXAMPLE III
In the first embodiment and the second embodiment, it is shown how to group latches and configure clocks when different numbers of latches are used, and different numbers of bits of data are loaded and stored according to different design requirements, respectively. However, in actual conditions, the number of latches and the number of clocks to be used are determined according to the amount of data to be stored, and when the number of clocks is determined by design, it is necessary to take into consideration factors such as the number of wirings increased by the clocks and the maximum width of each clock pulse. Therefore, even if the number of data bits required to be stored is the same, different shift register structures and shift register methods can be adopted according to design requirements.
For example, when 9-bit data needs to be loaded and stored, the following structure and manner may be adopted:
1) adopting 13 latches to form a latch chain, dividing the latch chain into 4 latch unit groups each including 3 latches and a single latch, and making the last latch in each latch unit group be a redundant unit (dummy), configuring 3 Clocks (CLK), and making each clock correspond to one latch in each latch unit group and sending a clock signal according to the mode in the first embodiment:
2) with 12 latches, dividing into 3 latch unit groups each including 4 latches, and making the last latch in each latch unit group a redundant unit (dummy), 4 CLKs are configured, also in the manner in the first embodiment, so that each clock corresponds to one latch in each latch unit group and sends a clock signal.
It can be seen from the second case and the first and second embodiments that when each latch unit group includes 3 latches, if the shift register structure includes N latch unit groups, the maximum number of bits that can load and store data is 2N. However, in the first embodiment, the number of latches in the latch chain may be equally divided into a plurality of latch unit groups, in other words, the total number of latches may be divided by the number of latches (i.e., the number of clocks) included in each group. However, in actual use, the total number of latches may not be equally divided into several groups, for example, in the first case of the above example, the total number of latches may not be equally divided into several latch unit groups, and at this time, the number of latches included in each latch unit group is still determined according to the number of clocks determined by design, and the ungrouped latches are placed in the last bit of the entire latch chain, and an independent group including several latches, that is, several bits of data can be loaded and stored, is formed without including redundant cells.
Example four
With the technical solution in the first embodiment, in addition to overcoming the problem of data redundancy, 12 latches are used to load 8 bits of data through 8 clock cycles of 3 clocks. In the fourth embodiment, 12 latches are used to form a latch chain, but the utilization rate of the latches is increased by increasing the clock, and 9-bit data is transmitted.
Specifically, referring to fig. 6 first, fig. 6 is a schematic diagram illustrating a shift register structure including redundant memory cells according to a fourth embodiment of the present invention. As shown, the difference between the shift register structure in the fourth embodiment and the first embodiment is that 4 clocks are used, and accordingly 12 latches are divided into 3 groups of latch units, and each group of latch units includes 4 latches. 3 groups of latch units are defined as { Q 1 、Q 2 、Q 3 Each latch unit group comprises 4 latches respectively, and the last latch in the three latches of each latch unit group is set as a redundant unit (dummy). Then, specifically, latch the cell group Q 1 In (c) contains { q 0 、q 1 、q 2 、q 3 Wherein q is 3 Is a redundant unit; the latch unit group Q = includes { Q } 4 、q 5 、q 6 、q 7 In which q is 7 Is a redundant unit; latch unit group Q 3 In (c) contains { q 8 、q 9 、q 10 、q 11 Wherein q is 11 Are redundant units.
4 clocks, each defined as CLK 0 、CLK 1 、CLK 2 、CLK 3 . Wherein, CLK 0 Respectively connected with the latch unit group Q 1 Latch q in (1) 0 Latch unit group Q 2 Latch q in (1) 4 And a latch unit group Q 3 Latch q in (1) 8 Corresponds to and transmits a clock signal. Referring to FIG. 6, and so on, CLK 1 Respectively connected with latch unit group Q 1 Latch q in (1) 1 And latchUnit group Q 2 Latch q in (1) 5 And a latch unit group Q 3 Latch q in (1) 9 Corresponding and transmitting a clock signal; CLK 2 Respectively connected with latch unit group Q 1 Latch q in (1) 2 Latch unit group Q 2 Latch q in (1) 6 And a latch unit group Q 3 Latch q in (1) 10 Corresponding and sending a clock signal; CLK 3 Respectively connected with latch unit group Q 1 Latch q in (1) 3 And latch unit group Q 2 Latch q in (1) 7 And a latch Q in a latch cell group Q3 11 Corresponds and transmits the clock signal.
CLK 0 、CLK 1 、CLK 2 And CLK 3 Is equal, in the fourth embodiment, CLK is set 1 Compared with CLK 0 Delayed by 3/4 clock cycles, correspondingly resulting in CLK 2 Compared with CLK 1 Delayed by 3/4 cycles, CLK 3 And also compared with CLK 2 With a delay of 3/4 cycles. Referring to fig. 7, fig. 7 is a schematic diagram illustrating a shift register principle of loading and storing 9-bit data by using 4 clocks and 12 latches in the fourth embodiment, and the selected portion of the block in fig. 7 is the data array stored in the latch when the data loading transmission is completed. According to the first switching CLK 0 Then switching CLK again 1 、CLK 2 Finally CLK 3 When a clock signal comes, one fourth of the 12 latches simultaneously changes state, and in the process of changing state, the one fourth latch takes the output of the latch at the previous stage as the input of the latch and stores the output. At any time during the shifting process, there are two latches of the same data in any four adjacent latches of the 12 latches. According to the shift principle of the latch, referring to FIG. 7, after 8 clock cycles, the redundant cell { q } 3 、q 7 、q 11 The data stored in the latches at the previous stages are the same as the data stored in the latches at the previous stages, and the loading and storing processes of 8-bit data are completed.
Based on the fourth embodiment, it should be understood that a specific number of latches can be designed to achieve the loading and storing needs of different bit numbers of data.
In terms of power consumption, referring back to the conventional shift register structure shown in fig. 1, the power consumption for opening the gate is set to be P, and in the shift storage process for N-bit data, the power consumption satisfies:
wherein toggle times is the number of switching times.
And at 3 clocks, the power consumption satisfies:
therefore, the shift register structure comprising the redundant memory unit can obviously reduce peak current and total power consumption. By further generalization, it can be known that, in the case of n clocks, the power consumption should satisfy:
the total power consumption of the shift register structure based on the same structure is further reduced as the clock is increased.
EXAMPLE five
In summary, another aspect of the present invention is a shift register method including redundant memory cells according to the first to fourth embodiments. FIG. 8 is a flowchart illustrating a shift register method including redundant memory cells according to a preferred embodiment of the present invention. Referring to fig. 8, in the preferred embodiment, the shift register method includes the following steps: step S1, designing and determining the number of the needed clocks according to the number of the data bits to be stored, and then designing and determining the number of the needed latches; a step S2 of dividing the latches into a plurality of latch unit groups containing the same number in sequence according to the number of required clocks, and the number of latches contained in each latch unit group is equal to the number of clocks determined by design; a step S3 of setting the same sequential latch in each latch unit group as a redundant unit; a step S4 of configuring a corresponding delay for each of the clocks; a step S5 of configuring a next-stage data acquisition circuit and connecting the data acquisition circuit to each latch except the redundant cell in each latch unit group; step S6, in which the data obtaining circuit obtains data in each latch except the redundant cell in the latch cell group since the data shift storage is completed.
As described in the foregoing embodiments, for how the design requirement determines the number of clocks, and how many latches are selected, it is necessary to consider not only the length of the bit of the data to be stored, but also the wiring required by the clock, and the pulse width. In fact, as described in the foregoing embodiments, in practical applications, with the increase of clocks, the utilization rate of the latch is increased, and the peak current and the total power consumption of the shift register structure are correspondingly reduced, but at the same time, the number of traces corresponding to the clocks is also increased; on the other hand, as described in embodiments three and four, the number of latches required to store the same data is also reduced with the increase of the clock, and therefore, it is often necessary to balance the number of clocks used and the layout trace. In practical application, the number of the adopted clocks and the total number of the latches are adjusted according to the requirement of the current shift register data and the consideration standard of design.
When it is determined that N clocks and M latches are needed, the M latches are divided into H latch unit groups, and each latch unit group includes N latches. The number of latch cell groups, i.e. the number of M divided by N, is rounded up if M cannot be divided by N.
For the H latch unit groups, in the process of setting the redundancy unit, the Nth latch in the N latches of each group is the redundancy unit. For example, taking an example that each group of latch units includes 3 latches, if N groups of latch units are included, the first latch in each group may be set as a redundant unit, the middle latch may be set as a redundant unit, or the last latch in each group may be set as a redundant unit. It is not possible to set the first latch in the first group of latch units as a redundant cell, and the redundant cell in the other group is a middle or end latch. Generally, in the preferred embodiment of the present invention, for any size group of latch cells, the last latch in each group is set to be a redundant cell, thereby facilitating the data acquisition circuit to acquire data.
In a scheme in which the last latch in each group is a redundant cell, any one of the N clocks CLKx corresponds to the X +1 th latch in each group of latches. Referring to the fourth embodiment, it can be seen that the initial clock CLK 0 The clock signal is transmitted corresponding to the latch set as the redundant cell in each latch cell group. In step S4, the specific step of configuring the delay for each clock is to set the clock period of N clocks to TCK, and for any clock of N clocks, the delay is (N-1)/N × TCK periods compared with the previous clock. That is, any clock of 3 clocks lags behind the previous clock by 2/3 clock cycles, and any clock of 4 clocks lags behind the previous clock by 3/4 clock cycles.
Compared with the prior art, the invention has the following beneficial technical effects due to the adoption of the technical scheme:
1. the invention solves the technical problems of low area utilization and large overall power consumption of the existing shift register structure, and divides a plurality of latches contained in a latch chain into groups and selects the latch with a fixed position in a latch unit group as a redundant latch unit. The redundant latch unit is only used for moving data in the data transmission process and is not connected with the next-stage data acquisition circuit so as to ensure the transmitted data to be correct and eliminate data collision caused by clock switching; in another aspect, compared with the shift register structure in the prior art, the delay is realized by setting the redundant latch unit and abandoning the clock, so that the shift register structure does not need to configure an additional delay unit as in the prior art, and the design area of the shift register is reduced from two aspects;
2. compared with the shift register method and structure in the prior art, when the data with the same number of bits is transmitted, the invention reduces the number of required latches by increasing the clock, improves the utilization efficiency of the latches and also realizes the technical purpose of reducing the design area of the shift register structure;
3. in the structure, the latches in the latch chain are grouped according to the number of the adopted clocks to form a plurality of latch unit groups containing the same number of latches, the number of the latches contained in each latch unit group is consistent with the number of the adopted clocks, for any clock CLKx in N clocks, the latches respectively correspond to the X +1 th latch in each latch unit group and transmit clock signals, thus, when a clock pulse arrives, only the latch corresponding to the current clock can change the state, for the shift register structure of M latches adopting N clocks, only M/N latches in one clock pulse can change the state, compared with the structure of the prior art, when each rising edge or falling edge, all triggers or latches can change the state, the peak current when the latches are switched is obviously reduced, meanwhile, the overall power consumption of the shift register structure is reduced.
The above examples only show several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (9)
1. A shift register method including a redundant memory cell, the shift register method comprising the steps of:
step S1, designing and determining the number of the needed clocks according to the number of the data bits to be stored, and then designing and determining the number of the needed latches;
a step S2 of dividing the latches into a plurality of latch unit groups including the same number of latches in sequence according to the number of required clocks, wherein the number of latches included in each latch unit group is equal to the number of clocks determined by design;
a step S3 of setting the same sequential latch in each latch unit group as a redundant unit;
a step S4 of configuring a corresponding delay for each of the clocks;
a step S5 of configuring a next-stage data acquisition circuit and connecting the data acquisition circuit to each latch except the redundant cell in each latch unit group;
step S6, after the data shift storage is completed, the data obtaining circuit obtains the data in each latch except the redundant cell in the latch cell group.
2. The shift register method according to claim 1, wherein said step S2 of dividing said plurality of latches into a plurality of latch unit groups each having the same number in sequence according to the required number of clocks is embodied by: when the number of the required clocks is determined to be N by design, and M latches are adopted, the M latches are divided into H latch unit groups, each latch unit group comprises N latches, wherein H is a value obtained by dividing M by N and then rounding up.
3. The method according to claim 2, wherein in step S3, the step of defining the same sequential latch in each latch unit group as a redundant unit comprises: for H latch unit groups, respectively defining N latches in each group as { Q 0 、Q 1 …Q N-2 、Q N-1 And sets the corresponding sequential latches Q in each group n Are redundant units.
4. The method according to claim 3, wherein a last latch of each latch unit group is set as a redundant unit.
5. The method according to claim 4, wherein said step S4, before the step of configuring each of said clocks with a corresponding delay, further comprises a step of sequentially corresponding each clock to a same sequential latch in each of said sets of latch units, and setting N of said clocks to { CLK } 0 、CLK 1 …CLK N-2 、CLK N-1 For any clock CLKx in the N clocks, which respectively corresponds to the X +1 th latch in each latch unit group and sends a clock signal, X is an integer less than or equal to N-1,
setting the clock period of N clocks to TCK, the clock period of any one of N clocks is delayed by (N-1)/N × TCK periods compared with the adjacent previous clock.
6. The shift register method as claimed in claim 5, wherein step S6 is preceded by the steps of: and configuring a pulse counter for each clock, and setting the pulse counter to stop after reaching a preset count.
7. A shift register structure according to any one of claims 1 to 6, wherein the shift register structure comprises:
the latches are sequentially connected to form a latch chain, the input of any latch is connected with the output of the previous-stage latch, the latches are divided into a plurality of latch unit groups, and one latch at the same position in each latch unit group is a redundant unit;
a plurality of clocks, the number of clocks corresponding to the number of latches included in the set of latch units, each clock sequentially corresponding to the same sequential latch in each of the set of latch units and transmitting a clock signal,
a data acquisition circuit connected to each of the latches in each of the latch cell groups except for the redundancy cell, wherein,
setting the clock period of the N clocks to TCK, and for any one of the N clocks, delaying by (N-1)/N × TCK periods compared with the previous clock, after the data shift storage is completed, the data acquisition circuit acquires the data.
8. The shift register structure of claim 7, wherein a last latch in each of said sets of latch units is a redundant unit.
9. The shift register structure of claim 8, wherein N clocks are set to { CLK 0 、CLK 1 …CLK N-2 、CLK N-1 And for any clock CLKx in the N clocks, it corresponds to the X +1 th latch in each latch unit group and sends a clock signal.
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