JPH08149854A - Bridge type inverter device - Google Patents

Abstract

PURPOSE: To reduce the switching loss of the switch of an inverter device. CONSTITUTION: The switch circuit 5a of an inverter device is composed of first and second main switches TR1 and TR2, first to fourth auxiliary switches S1 -S4 , first and second reactors L1 and L2 , first and second capacitors C1 and C2, and first to sixth diodes D1 -D6 . The first and second main switches TR1 and TR2 are made to perform ZVS operation. At the time of fuming on of the first and second auxiliary switches S1 and S2 , they are made to perform ZCS operation, and at the time of turning off, they are made to perform ZVS operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge type, half bridge type or multi-phase inverter device.

[0002]

2. Description of the Related Art When a switch of a bridge type inverter for converting direct current into alternating current is turned on and off, switching loss occurs. To solve this kind of problem, the partial resonance is used to switch the switch to ZCS (Zero Current Switching) or ZVS.
It has been proposed to reduce switching loss, surge voltage, and noise by (zero voltage switching). However, there is a demand for an inverter device that can surely and easily achieve reduction of the loss of not only the main switch but also the partial resonance switch. Further, it is required to simplify the structure of the partial resonance circuit.

Therefore, an object of the present invention is to provide a bridge type inverter device which can meet the above demands.

[0004]

The invention according to claim 1 for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. One of the invention is provided between one end and the other end of a DC power supply. Alternatively, a plurality of switch circuits are connected, and the switch circuit connects the load with a current in a first direction and an opposite second current.
In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow a current in the direction of, at least one of the switch circuits is connected between one end and the other end of the DC power supply 1. A main conversion circuit comprising a series circuit of first and second main switches TR1 and TR2, wherein the interconnection middle point of the first and second main switches TR1 and TR2 is connected to a load; And the first main switch TR1 and the second main switch TR1 connected in anti-parallel
And a series circuit of the second diodes D1 and D2, the first auxiliary switch S1 and the first reactor L1,
The first auxiliary switch S1 is connected to the first reactor L.
The first auxiliary switch S1 and the first reactor L1 are arranged closer to one end side of the power source 1 than the one, and the one end of the power source 1 and the first and second main switches TR1 and T1.
A first auxiliary circuit connected between the interconnection midpoint of R2, a second auxiliary switch S2 and a second reactor L.
2 is a series circuit with the second auxiliary switch S2
Is arranged on the other end side of the power source 1 with respect to the second reactor L2, and the second reactor L2 and the second auxiliary switch S2 are connected to the first and second main switches TR.
1, a second auxiliary circuit connected between the interconnection middle point of TR2 and the other end of the power source 1, and one end of which is the first auxiliary circuit.
And a first capacitor C1 connected to the interconnection middle point of the second reactors L1 and L2 and a second capacitor C1 whose one end is connected to the interconnection middle point of the first and second reactors L1 and L2. Capacitor C2 and the first capacitor C
A third diode D3 connected between the other end of 1 and the terminal of the first reactor L1 on the side of the first auxiliary switch S1; and the second auxiliary switch S2 of the second reactor L2. A fourth diode D4 connected between the side terminal and the other end of the second capacitor C2, the first capacitor C1, the second reactor L2, and the second auxiliary switch S2. A fifth diode D5 connected in parallel to the circuit connected in series,
The first auxiliary switch S1 and the first reactor L
A sixth diode D6 connected in parallel to a circuit in which 1 and the second capacitor C2 are connected in series.
A third auxiliary switch S3 connected in parallel to the first reactor L1 through the third diode D3, and a fourth auxiliary switch S3 connected to the second reactor L2.
A fourth auxiliary switch S4 connected in parallel via the diode D4 of the first and second main switches TR1
, First control pulses for controlling ON of TR2 with a predetermined time gap Ta between them, and first control for controlling ON of the first auxiliary switch S1. A pulse is generated so as to include at least a part of the period from the trailing edge of the second main control pulse to the leading edge of the first main control pulse, and the second auxiliary switch S2 is turned on. The second auxiliary control pulse includes at least a part of a period from the trailing edge of the first main control pulse to the leading edge of the second main control pulse, and is predetermined between the second auxiliary control pulse and the first auxiliary control pulse. And a third auxiliary control pulse for controlling to turn on the third auxiliary switch S3 is simultaneously turned on for both the first auxiliary switch S1 and the first diode D1. At least one of the periods At a time during which both the second auxiliary switch S2 and the second diode D2 are turned on at the same time by generating a fourth auxiliary control pulse for turning on the fourth auxiliary switch S4. The present invention relates to an inverter device characterized by comprising a switch control circuit which is partially generated. Further, as described in claim 2, third and fourth capacitors Ca and Cb can be connected in parallel to the first and second main switches TR1 and TR2. As described in claim 3, the first and second auxiliary switches S1 and S
2 and the first and second reactors L1 and L2 in series with the first and second backflow prevention diodes Da and
Db can be connected. In addition, as shown in claim 4, the first and second reactors L1 in claim 1
, L2 in place of one reactor La first and second
Can be connected between the interconnection midpoints of the main switches TR1 and TR2 and the interconnection midpoints of the first and second auxiliary switches S1 and S2. Moreover, as shown in claim 5,
The third and fourth capacitors Ca and Cb can be added to the circuit of claim 4 as in the case of claim 2. Further, as shown in claim 6, the first and second reverse current blocking diodes Da and Db can be connected in series to the first and second auxiliary switches S1 and S2 in claim 4.

[0005]

According to the invention of each claim, the first
And the operation of the second auxiliary switches S1 and S2 causes the first
The ZVS effect of the second main switches TR1 and TR2 can be surely obtained, and the auxiliary switches S1 and S2 can also be operated in ZCS or ZVS. According to the fifth and sixth aspects of the present invention, the resonance current is flowed only in a predetermined section by a simple circuit that does not use an auxiliary switch, and the first and second main switches TR1 and TR2 are turned off at ZVS and turned on at ZCS operation is possible. Further, according to the inventions of claims 2 and 5, energy can be supplied to the resonance circuit by the first and second auxiliary resonance capacitors Ca and Cb, and a stable resonance operation can be obtained. According to the invention of claims 3 and 6, the first
Also, it is possible to prevent discharge of the parasitic capacitances of the second auxiliary switches S1 and S2 and improve efficiency. Further, according to the inventions of the respective claims, a power supply for applying the midpoint potential to the switch circuit is not required, and the structure of the power supply is simplified.

[0006]

[First Embodiment] Next, a bridge type inverter device according to a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, this inverter device is configured to convert a DC voltage of a DC power supply 1 into an AC by a bridge type inverter circuit and supply the AC to a load 2. The DC power supply 1 is composed of a rectifier circuit or a battery, and the load 2 is composed of, for example, an output transformer 3 connected to the load connection terminals 2a and 2b and a load circuit 4 connected to the output transformer 3.

The inverter circuit is composed of a combination of first and second switch circuits 5a and 5b having a half bridge structure. The first switch circuit 5a is a first and second main switch TR1 for forming a first arm of the bridge circuit.
, TR2 and first and second diodes D1, D2, in order to achieve ZVS or ZCS, first,
The second, third and fourth auxiliary switches S1, S2, S3,
S4, the first and second capacitors C1 and C2, and the first
And second reactors L1 and L2, and third, fourth and fifth reactors
And sixth diodes D3, D4, D5, D6 and first and second resistors R1, R2 as capacitor charging means.
Have and. The second switch circuit 5b includes third and fourth main switches TR3, TR4 to form a second arm of the bridge circuit, and seventh and eighth diodes D7,
In addition to having D8, in order to achieve ZVS and ZCS,
Fifth, sixth, seventh and eighth auxiliary switches S5, S6,
S7, S8 and third and fourth capacitors C3, C4
, Third and fourth reactors L3 and L4, and ninth to twelfth diodes D9 to D12.

First and second for forming a main conversion circuit
The series circuit of the main switches TR1 and TR2 is connected between one end and the other end of the power source 1, and the first and second main switches T1 and TR2 are connected.
The interconnection middle point of R1 and TR2 is connected to the first load connection terminal 2a as an output terminal. The first and second diodes D1 and D2 are connected to the first and second main switches TR1.
, TR2 are connected in anti-parallel. The series circuit of the third and fourth main switches TR3 and TR4 is also connected between one end and the other end of the power source 1, and the third and fourth main switches TR3 and TR3 are connected.
, TR4 are connected to the second load connection terminal 2b at the interconnection middle point. Seventh and eighth diodes D7, D8
Are connected in anti-parallel to the third and fourth main switches TR3, TR4. In addition, the first to fourth main switches TR1 to
TR4 is an insulated gate (MOS) field effect transistor having a structure in which the source is connected to the substrate, and the diodes incorporated therein are the first, second, seventh and eighth diodes D1, D2, D7. , D8.

A first circuit comprising a series circuit of a first auxiliary switch S1 and a first reactor L1 between one end of the power source 1 and the interconnection middle point of the first and second main switches TR1 and TR2. Auxiliary circuit is connected. A second auxiliary circuit composed of a series circuit of a second reactor L2 and a second auxiliary switch S2 between the interconnection middle point of the first and second main switches TR1 and TR2 and the other end of the power source 1. Are connected. One ends of the first and second capacitors C1 and C2 are respectively connected to the interconnection middle points of the first and second reactors L1 and L2. The other end of the first capacitor C1 is connected to the first reactor L1 via the third diode D3.
Is connected to the first auxiliary switch S1 side terminal of the second capacitor C2, and the other end of the second capacitor C2 is connected to the second reactor L2 via a fourth diode D4 having a direction opposite to that of the third diode D3. It is connected to the second auxiliary switch S2 side terminal. The fifth diode D5 is connected between the terminal (emitter) on the power source 1 side of the second auxiliary switch S2 and the other end (upper end) of the first capacitor C1. That is,
The fifth diode D5 is connected in parallel to the series connection circuit of the first capacitor C1, the second reactor L2 and the second auxiliary switch S2. The sixth diode D6 is connected between the other end (lower end) of the second capacitor C2 and the power supply 1 side terminal (collector) of the first auxiliary switch S1. That is, the sixth diode D6 is connected in parallel to the series connection circuit of the first auxiliary switch S1, the first reactor L1 and the second capacitor C2. The charging resistors R1 and R2 are connected in parallel to the fifth and sixth diodes D5 and D6. The third auxiliary switch S3 is in parallel with the first capacitor C1.
Is connected in parallel to the reactor L1 via a third diode D3. The fourth auxiliary switch S4 is connected in parallel to the second capacitor C2, that is, in parallel to the second reactor L2 via the fourth diode D4.

The second switch circuit 5b is substantially the same circuit as the first switch circuit 5a, and includes the third and fourth switches.
One end of the power supply 1 and the third and fourth main switches TR3 to achieve ZVS of the main switches TR3 and TR4 of
A fifth auxiliary switch S5 is provided between the middle point of interconnection of TR4.
And a third auxiliary circuit consisting of a series circuit of a third reactor L3. Third and fourth main switch T
A fourth auxiliary circuit consisting of a series circuit of a fourth reactor L4 and a sixth auxiliary switch S6 is connected between the interconnection middle point of R3 and TR4 and the other end of the power source 1. Third
And one ends of the fourth capacitors C3 and C4 are the third and fourth ends.
It is connected to the middle point of the interconnection of reactors L3 and L4. The other end of the third capacitor C3 has a ninth diode D
It is connected to the terminal of the third reactor L3 on the side of the fifth auxiliary switch S5 via 9 and the other end of the fourth capacitor C4 has a directivity opposite to that of the ninth diode D9.
6th of 4th reactor L4 through diode D10 of
It is connected to the auxiliary switch S6 side terminal. 11th
The diode D11 is connected between the lower terminal (emitter) of the sixth auxiliary switch S6 and the other end (upper end) of the third capacitor C3. That is, the eleventh diode D11
Is the third capacitor C3, the fourth reactor L4 and the sixth
Is connected in parallel to the series connection circuit with the auxiliary switch S6. The twelfth diode D12 is connected between the other end (lower end) of the fourth capacitor C4 and the upper terminal (collector) of the fifth auxiliary switch S5. That is, the twelfth diode D12 is connected to the fifth auxiliary switch S5 and the third auxiliary switch S5.
Is connected in parallel to the series connection circuit of the reactor L3 and the fourth capacitor C4. Charging resistor R3,
R4 is connected in parallel with the eleventh and twelfth diodes D11 and D12. 7th and 8th auxiliary switches S7,
S8 is connected in parallel with the third and fourth capacitors C3 and C4.

In FIG. 1, some of the connecting lines between them are omitted for convenience of illustration, but the switches TR1 to TR4 are not shown.
, S1 to S8 control terminals (bases) are connected to the switch control circuit 6. As shown in principle in FIG. 2, the control circuit 6 includes first, second, third and fourth main control pulse generation circuits 7, 8, 9, 10 and first to eighth auxiliary control pulse generation circuits. Circuits 11, 12, 13, 14, 15, 16, 1
7 and 18, an oscillator 19, and a phase control circuit 20. The first and second main control pulse generation circuits 7 and 8 are controlled by the oscillator 19 to generate the first and second main control pulses shown in FIGS. 3A and 3B, and the first and second main control pulses are generated. Supply to the bases of the main switches TR1 and TR2. The third and fourth main control pulse generation circuits 9 and 10 are controlled by the oscillator 19 and the phase control circuit 20 to generate the third and fourth main control pulses shown in FIGS. 3C and 3D, This is supplied to the bases of the third and fourth main switches TR3 and TR4. The first and second main control pulses and the third and fourth main control pulses are the same except that they have a phase difference between them. FIG.
The first and second main control pulses in (A) and (B) are alternately generated with a time gap Ta between them, as shown in FIG.
The third and fourth main control pulses in (D) also occur alternately with a time gap Ta. In this time gap Ta, the auxiliary switches S1, S2, S5 and S6 are turned on when the capacitors C1, C2, C3 and C4 are charged, and almost all the electric charges of C1, C2, C3 and C4 are generated by the resonance operation. The time required for release is set. That is, Ta
Is 0 to 90 degrees of the waveform of the resonance current of C1 L2 or C2 L1.
It is set to a degree or more.

The first auxiliary control pulse generation circuit 11 has a second
Of the second main control pulse of FIG. 3 (B) as shown in FIG. 3 (E).
T8 after a predetermined time from time t7 after a predetermined time from 6
The second auxiliary control pulse is generated until the time point. The first auxiliary control pulse can be generated in synchronism with the trailing edge time t6 of the second main control pulse, or can be generated slightly before this time t6. That is, the first auxiliary control pulse is formed so as to include at least a part of the period Ta from the trailing edge time t6 of the second main control pulse to the leading edge time t8 of the first main control pulse. The second auxiliary control pulse generation circuit 12 is connected to the first main control pulse generation circuit 7, and as shown in FIG. 3 (F), a time point after a predetermined time after the trailing edge time t0 of the first main control pulse. The second auxiliary control pulse is generated from t1 to time t3 after a predetermined time. The second auxiliary control pulse can be generated in synchronization with the trailing edge time t0 of the first main control pulse, or slightly before this time t0. That is, the second auxiliary control pulse is formed so as to include at least a part of the period Ta from the trailing edge time t0 of the first main control pulse to the leading edge time t2 of the second main control pulse. The third auxiliary control pulse generation circuit 13 is the second main control pulse generation circuit 8
Connected from the time t8 (the leading edge of the first main control pulse) after the trailing edge time t6 of the second main control pulse of FIG. 3B to the time t9 after a predetermined time. Generate a third auxiliary control pulse having This third auxiliary control pulse is applied to the first auxiliary switch S1 and the first diode D
Both 1 and 1 are formed so as to include at least a part of the period in which both are turned on at the same time. The leading edge of the third auxiliary control pulse is preferably after the leading edge of the first auxiliary control pulse by a time Tb corresponding to 90 degrees of the resonance current of the C1 L2 resonant circuit. Fourth auxiliary control pulse generation circuit 14
Is connected to the first main control pulse generating circuit 7,
A fourth auxiliary control pulse having a width from a time point t2 after the trailing edge time point t0 of the first main control pulse in (A) to a time point t4 after a predetermined time is generated. This fourth auxiliary control pulse is applied to the second auxiliary switch S2 and the second diode D2.
Are formed so as to include at least a part of a period in which both and are simultaneously turned on. The leading edge of the fourth auxiliary control pulse is preferably after the leading edge of the second auxiliary control pulse by a time Tb corresponding to 90 degrees of the resonance current of the C2 L1 resonance circuit. Fifth for second switch circuit 5b
~ The eighth auxiliary control pulse generation circuits 15-18 are
It is formed so as to generate the fifth to eighth auxiliary control pulses of FIGS. 3I to 3L by the same method as the fourth auxiliary control pulse generation circuits 11 to 14. The time points at which the first to eighth auxiliary control pulses are generated are determined using a counter.

[0013]

[Operation] The basic operation of the inverter circuit of FIG. 1 is the same as that of a known inverter. That is, while the main switches TR1 and TR4 shown in FIGS. 1 and 4 are turned on at the same time, the current in the first direction is generated in the circuit composed of the power source 1, the first main switch TR1, the load 2 and the fourth main switch TR4. Flow to load 2, second
Also, while the third main switches TR2 and TR3 are simultaneously turned on, a current in the second direction flows through the load 2 in the circuit composed of the power source 1, the third main switch TR3, the load 2 and the second main switch TR2. .

Next, the first to fourth main switches TR1 to T
The operation of R4 during the turn-on and turn-off periods will be described. However, the operation during the turn-off period of the first main switch TR1 and the turn-on of the second main switch TR2 shown in the vicinity of t0 to t2 in FIG. 3 and the second main switch TR2 shown in the vicinity of t6 to t8. During the turn-off period of the first main switch TR1, the turn-off period of the third main switch TR3 and the turn-off period of the fourth main switch TR4, and the turn-off period of the fourth main switch TR4. Operation, turn off of the fourth main switch TR4 and third main switch TR4
3 is substantially the same as the operation during the turn-off period, the operation during t0 to t2 in FIG. 3 and the operation in the vicinity thereof will be described in detail with reference to FIG. .

[0015]

[Capacitor Charging Operation] In this embodiment, it is necessary to precharge the first and fourth capacitors C1 and C2 in the directions shown in FIG. In order to perform this charging, the first and fourth main switches TR1 and TR4 are turned on. As a result, a charging current flows in the circuit of the first main switch TR1, the first capacitor C1 and the first resistor R1, and the first capacitor C1 is charged to the power supply voltage V. Also, a fourth resistor R4, a fourth capacitor C4 and a fourth main switch T
A current also flows in the circuit of R4, and the fourth capacitor C4 is charged. Of course, conversely, the second and third capacitors C2, C3 can also be precharged. After the inverter operation by the first to fourth main switches TR1 to TR4 is started, the loss in resonance is caused by the main switch TR.
Replenished via 1 to TR4.

[0016]

[Turn-off and turn-on operation] FIG. 4 shows the states of the respective parts of FIG. 1 in the section t0 to t5 of FIG. When the first main switch TR1 is turned off at time t0 when the first capacitor C1 is almost charged to the power supply voltage V, and the second auxiliary switch S2 is turned on at time t1 a little later than this time, The energy of the first capacitor C1 is released in the resonance circuit composed of the first capacitor C1, the second reactor L2, the second auxiliary switch S2 and the fifth diode D5, and the voltage Vc1 of the first capacitor C1 is As shown in FIG. 4 (E), the waveform decreases in the 90-180 degree section of the sine wave. At this time, since the fifth diode D5 is on, the second main switch T
The potential Vc1 of the first capacitor C1 is applied to both ends of R2, and as shown in FIG. 4 (I), t1 to t2.
Then, the voltage Vtr2 of the second main switch TR2 decreases toward zero. Also, the voltage Vtr1 of the first main switch TR1
Is the power supply voltage V to the voltage Vtr2 of the second main switch TR2.
Becomes a value obtained by subtracting, and slowly rises as shown in FIG. The first capacitor C1, the second reactor L2, the second auxiliary switch S2, and the fifth diode D5.
As shown in FIG. 4G, the resonance current I2 of the closed circuit composed of and flows with a waveform of a sine wave of 0 to 90 degrees in the section of t1 to t2. The first capacitor C1 at time t2
When the voltage Vc1 of the second diode D2 becomes zero, the reverse bias of the second diode D2 is released, and the current I2 due to the discharge of the stored energy of the second reactor L2 is commutated to the second diode D2 and the second reactor L2 and the second reactor D2. 2 auxiliary switches S
2 and the second diode D2 closed circuit flow as a circulating current. Since the fourth auxiliary switch S4 is turned on at the time t2 when the reactor current I2 reaches the peak, a closed circuit of the second reactor L2, the fourth diode D4 and the fourth auxiliary switch S4 is formed, and the closed circuit is formed here. Circulating current also flows. In the period after t2, the voltage of the first capacitor C1 is zero volt, and the voltage Vtr2 of the second main switch TR2 is also zero volt. Therefore, when the second main switch TR2 is turned on after t2, ZVS is achieved. The first main switch TR1 is set to ZVS at time t0.
Is turned off at. Even if the second auxiliary switch S2 is turned off at time t3 after the time t2 when the second main switch TR2 is turned on, the current I2 continues to flow as shown in FIG. 4G because the fourth auxiliary switch S4 is turned on. When the fourth auxiliary switch S4 is turned off at time t4, the second reactor L2
Resonance occurs in the circuit of the fourth diode D4 and the second capacitor C2, and a resonance current having a waveform in the 90 to 180 degree section of the sine wave flows as shown in FIG. 4 (G), and the second capacitor C2 Voltage Vc2 of sine wave increases as shown in FIG. 4 (F) and becomes the power supply voltage V at t5. The fourth diode D4 is cut off at t5, blocking the resonance current in the negative direction, the voltage Vc2 of the second capacitor C2 is held at V, and preparation for operation after t6 in FIG. 3 is completed. . As a result, Z when the second auxiliary switch S2 is turned off
VS is achieved. The ZCS operation is performed when the second auxiliary switch S2 is turned on. Therefore, the switching loss of both the main switch TR1 and the auxiliary switch S2 becomes small.

When the second main switch TR2 is turned off, the first auxiliary switch S1 is turned on to connect the second capacitor C2, the sixth diode D6, the first auxiliary switch S1 and the first reactor L1. A resonance circuit is formed, in which a current corresponding to the section t1 to t2 in FIG. 4 flows, and a current corresponding to the section t2 to t3 in FIG. 4 is generated by the first reactor L1, the first diode D1 and the first diode D1. A closed circuit consisting of one auxiliary switch S1 and a first reactor L1, a third auxiliary switch S3 and a third diode D3.
And a current corresponding to the section from t3 to t4 flows in the closed circuit of L1, S3 and D3, and t4 in FIG.
The current corresponding to the period from to t5 is the same as the first reactor L1 and the first reactor L1.
Flows in the closed circuit of the capacitor C1 and the third diode D3. Therefore, when the second main switch TR2 is turned off, the same operational effect as when the first main switch TR1 is turned off is obtained. Further, the same operation also occurs in the second switch circuit 5b, and the same effect can be obtained.

In FIG. 4, the load 2 is explained as no load.
Is regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flowing through. At this time, even if the storage currents of the main switches TR1 to TR4 flow, the voltages of the first to fourth main switches TR1 to TR4 do not rise suddenly at the turn-off time, so that the power loss is small.

This embodiment has the following effects. (1) Soft switching of the first to fourth main switches TR1 to TR4 and the first to eighth auxiliary switches (ZVS
Or ZCS) is enabled, and reduction of loss, reduction of surge voltage, and reduction of noise are achieved. (2) Since the snubber circuit loss does not substantially occur,
Efficiency is improved. (3) PW of constant frequency of the main switches TR1 to TR4
The M control becomes possible, and the efficiency improving effect due to the higher frequency of the inverter having the output transformer can be maintained. Further, the control circuit 6 can be simply constructed. (4) A power supply having a midpoint potential is unnecessary, and the power supply configuration is simple. (5) Since the circulating current period shown in t2 to t4 in FIG. 4 is provided, the degree of freedom at the time of turn-on becomes high. (6) In the period from t2 to t3, for example, two circulating current circuits passing through the second diode D2 and four circulating current circuits passing through the fourth auxiliary switch S4 are formed, so that the combined resistance component of the two parallel circuits is formed. Is smaller than in the case of only the circulating current circuit passing through the second diode D2.

[0020]

Second Embodiment Next, a bridge type inverter device according to a second embodiment of the present invention will be described with reference to FIG.
However, in FIG. 5 and FIG. 6, FIG. 7, FIG. 9, FIG. 10, and FIG. 11, which will be described later, the same parts as in FIG. In addition, the second switch circuit 5b
Has the same configuration as the first switch circuit 5a, and is shown as a block.

The first switch circuit 5a of the inverter device of FIG. 5 has the same configuration as that of FIG. 1 except that the first and second auxiliary resonance capacitors Ca and Cb are added to the switch circuit 5a of FIG. . The first and second auxiliary resonance capacitors Ca and Cb are connected to the first and second main switches TR1 and TR, respectively.
2 connected in parallel.

The first and second main switches TR1 of FIG.
TR2 and the first to fourth auxiliary switches S1 to S4 are shown in FIG.
Driven in the same way. Therefore, the basic operation of the circuit of FIG. 5 is the same as that of the circuit of FIG. In FIG. 5, the first auxiliary resonance capacitor Ca is connected in parallel to the first reactor L1 together with the second capacitor C2, and the second auxiliary resonance capacitor Cb is first connected to the second reactor L2.
Is connected in parallel with the capacitor C1. Therefore, for example, in the period from t1 to t2 in FIG. 4, two L2 C1 resonant circuits and an L2 Cb resonant circuit are formed.
Since the first and second auxiliary resonance capacitors Ca and Cb are directly connected to the power supply 1, the power supply voltage V is surely charged and the desired resonance operation can be surely obtained.
That is, in the circuit of FIG. 1, the first and second capacitors C1,
In some cases, C2 cannot be sufficiently charged to the power supply voltage V. In addition, a surge voltage may be generated when the main switches TR1 and TR2 are turned on / off due to the wiring inductance. However, as shown in FIG. 5, the first and second
The above problem is solved by adding the auxiliary resonance capacitors Ca and Cb. Therefore, the charging resistors R1 and R2 can be disconnected after the inverter is started.

[0023]

[Third Embodiment] The inverter device shown in FIG. 6 has the first and second reverse current blocking diodes Da and Db in the circuit of FIG.
The configuration is the same as that of FIG. The first and second backflow preventing diodes Da and Db are connected in series to the first and second auxiliary switches S1 and S2 and the first and second reactors L1 and L2.

There is a parasitic capacitance between the collector and emitter of the first and second auxiliary switches S1 and S2, which is the first capacitance.
And when the second auxiliary switches S1 and S2 are turned off, they are charged to the power supply voltage. In the circuit of FIG. 1, when the first and second main switches TR1 and TR2 are turned on, the energy of the parasitic capacitance causes the first and second main switches TR1 and TR2 and the first and second reactors L1 and L2 to move. Discharge through. However, by providing the first and second backflow blocking diodes Da and Db as shown in FIG. 6, this discharge is blocked, power loss is reduced, and efficiency is increased.

[0025]

[Fourth Embodiment] Next, an inverter device according to a fourth embodiment will be described with reference to FIGS. In the inverter device of FIG. 7, instead of the two reactors L1 and L2 of FIG.
It has two reactors La. The reactor La is connected between the interconnection middle point of the first and second main switches TR1 and TR2 and the interconnection middle point of the first and second auxiliary switches S1 and S2. Further, the interconnection middle point of the first and second capacitors C1 and C2 is connected to the interconnection middle point of the first and second main switches TR1 and TR2. First
The second auxiliary switches S1 and S2 are connected in series with each other without a reactor. The third and fourth diodes D3, D4 are connected to the first and second capacitors C1,
It is connected between the other end of C2 and the interconnection middle point of the first and second auxiliary switches S1 and S2. In FIG. 7, the others are configured the same as in FIG.

The operation of the inverter device of FIG. 7 is basically the same as that of FIG. 7 is different from FIG. 1 in that the resonance current flows through the common reactor La both when the first capacitor C1 is discharged and when the second capacitor C2 is discharged. That is, the first and second main switches TR1 and TR2 and the first to fourth auxiliary switches S1 to S4 are controlled according to FIG. 3, and t0 to t5.
In the section, it operates as shown in FIG. FIG.
As shown in (A) and (B), when the first main switch TR1 is turned off and the second auxiliary switch S2 is turned on at the time t1 thereafter, the energy of the first capacitor C1 becomes the first Second capacitor C1 and reactor La
Is discharged by the resonance circuit consisting of the auxiliary switch S2 and the fifth diode D5, and the potential V of the first capacitor C1 is
As shown in FIG. 8E, c1 decreases in the waveform of the sine wave in the 90 to 180 degree section. At this time, since the fifth diode D5 is on, the first main switch TR2 has the first diode across the first diode TR5.
The voltage Vc1 of the capacitor C1 of
As shown in FIG. 8 (I), the voltage Vtr2 of the second main switch TR2 decreases toward zero from t1 to t2. Further, the voltage Vtr1 of the first main switch TR1 becomes a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and rises slowly as shown in FIG. 8 (H). The resonance current Ia of the closed circuit composed of the first capacitor C1, the reactor La, the second auxiliary switch S2 and the fifth diode D5 is 0 to 0 of the sine wave in the section of t1 to t2 as shown in FIG. 8 (G). It flows with a 90-degree section waveform. t2
At this point, when the voltage Vc1 of the first capacitor C1 becomes zero, the reverse bias of the second diode D2 is released, and the current Ia due to the discharge of the stored energy of the reactor La is commutated to the second diode D2. Second
Flowing through the first closed circuit of the auxiliary switch S2 and the second diode D2 as a circulating current. Along with this, the reactor L
A second closed circuit of a, the fourth diode D4 and the fourth auxiliary switch S4 is formed, in which a circulating current also flows.
After the second auxiliary switch S2 is turned off, the current Ia continues to flow in the second closed circuit in the section from t3 to t4 in FIG. t4
At this time, when the second auxiliary switch S2 is turned off, the reactor La, the fourth diode D4 and the second capacitor C
Resonance occurs in the circuit of 2 and the resonance current of the waveform of the sine wave in the 90 to 180 degree section flows as shown in FIG.
8C, the voltage Vc2 of the capacitor C2 becomes sinusoidal, and becomes the power supply voltage V at t5. The fourth diode D4 is cut off at t5 to block the negative resonance current, and the voltage V2 of the second capacitor C2.
Hold c2 at V. This completes the preparation for the next operation.

When the second main switch TR2 is turned off, the first auxiliary switch S1 is turned on, and the resonance circuit of the second capacitor C2, the sixth diode D6, the first auxiliary switch S1 and the reactor La is formed. The current corresponding to the section from t1 to t2 in FIG. 8 flows in this circuit, and the current Ia corresponding to the section from t2 to t3 in FIG. 8 is generated by the reactor La, the first diode D1 and the first auxiliary switch S1. A first closed circuit consisting of and a reactor La and a third
Flow through a second closed circuit consisting of the auxiliary switch S3 and the third diode D3. The current Ia corresponding to the section from t3 to t4 in FIG. 8 flows through the second closed circuit. The current corresponding to the section from t4 to t5 in FIG.
Flows in the closed circuit of the capacitor C1 and the third diode D3.

FIG. 8 shows the reactor current I2 of FIG.
Since it is the same as that of FIG. 4 except that Ia is changed to Ia, the inverter device of FIG. 7 has the same effects as the inverter device of FIG.

[0029]

[Fifth Embodiment] The inverter device of FIG. 9 has the same structure as that of FIG. 7 except that the first and second auxiliary resonance capacitors Ca and Cb are added to the inverter device of FIG. It is a thing. In this FIG. 9 as well, the second and first auxiliary resonance capacitors Cb and Ca are connected in parallel to the first and second capacitors C1 and C2, and the same effect as in FIG. 5 is obtained.

[0030]

[Sixth Embodiment] The inverter device of FIG. 10 has the same structure as the inverter device of FIG.
, Db are added in the same manner as in FIG. 6 and have the same configuration as in FIG. Therefore, the same effect as that of FIG. 6 can be obtained by the inverter device of FIG.

[0031]

[Seventh Embodiment] Next, a half-bridge type inverter device according to a seventh embodiment of FIG. 11 will be described. The inverter device of FIG. 11 has a first and a second conversion capacitor C1 instead of the second switch circuit 5b of the inverter device of FIG.
1 and C12 are provided. A series circuit of capacitors C11 and C12 having a larger capacity than C1 and C2 is connected between one end and the other end of the power source 1, and the load 2 is connected to the midpoint of the interconnection. Switch circuit 5a of this half bridge device
1 is the same as that in FIG. 1, so that the same effect as that in FIG. 1 can be obtained. In addition, a half bridge circuit similar to that in FIG. 11 can be configured by using the switch circuit 5a in FIGS. 5 to 7 and FIGS.

[0032]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) A three-phase or multi-phase inverter device can be configured by connecting three or multiple switch circuits 5a shown in FIGS. 1, 5 to 7, and 9 to 10 in three-phase or multi-phase. (2) Main switches TR1 to TR4, auxiliary switch S1
~ S8 can be a semiconductor switch such as a field effect transistor. (3) By initially charging the capacitors C1 and C4 with independent charging devices, the charging resistors R1 to R4 can be omitted. Further, the charging resistors R1 to R4 can be replaced with switches to selectively flow the charging current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an inverter device of a first embodiment.

FIG. 2 is a block diagram showing a control circuit of FIG.

FIG. 3 is a waveform diagram of each part of FIG.

FIG. 4 is a waveform diagram of each part of FIG.

FIG. 5 is a circuit diagram of an inverter device according to a second embodiment.

FIG. 6 is a circuit diagram of an inverter device according to a third embodiment.

FIG. 7 is a circuit diagram of an inverter device according to a third embodiment.

FIG. 8 is a waveform diagram of each part of FIG.

FIG. 9 is a circuit diagram of an inverter device according to a fourth embodiment.

10 is a waveform diagram of each part of FIG.

FIG. 11 is a circuit diagram of an inverter device according to a fifth embodiment.

[Explanation of symbols]

 TR1 to TR4 Main switch S1 to S8 Auxiliary switch

Claims (6)

[Claims] 1. One or a plurality of switch circuits are connected between one end and the other end of a DC power supply, and the switch circuit connects a load with a current in a first direction and a second direction opposite thereto. In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It is composed of a series circuit of first and second main switches (TR1, TR2), and includes the first and second main switches (TR1, T2).
R2) a main conversion circuit whose interconnection middle point is connected to a load, and first and second diodes (D1, D2) antiparallel connected to the first and second main switches (TR1, TR2).
), The first auxiliary switch (S1) and the first reactor (L1
) In a series circuit, the first auxiliary switch (S1) is arranged at one end side of the power source (1) with respect to the first reactor (L1), and the first auxiliary switch (S1) And the first reactor (L1) are connected to one end of the power source (1) and the first and second main switches (TR1).
, TR2) and a second auxiliary switch (S2) and a second reactor (L2) that are connected between the middle point of interconnection of
), The second auxiliary switch (S2) is arranged on the other end side of the power source (1) with respect to the second reactor (L2), and the second reactor (L2) A second auxiliary switch (S2) connected between the interconnection middle point of the first and second main switches (TR1, TR2) and the other end of the power supply (1). Auxiliary circuit and one end of which is connected to the first and second reactors (L1, L2).
) The first capacitor (C1
), And one end thereof has the first and second reactors (L1, L2).
A second capacitor (C2
), And a third diode (D3) connected between the other end of the first capacitor (C1) and the terminal of the first reactor (L1) on the first auxiliary switch (S1) side. And a fourth diode (D4) connected between the second auxiliary switch (S2) side terminal of the second reactor (L2) and the other end of the second capacitor (C2). , A fifth diode () connected in parallel to a circuit in which the first capacitor (C1), the second reactor (L2) and the second auxiliary switch (S2) are connected in series. D5), the first auxiliary switch (S1), the first reactor (L1), and the second capacitor (C2) are connected in parallel to a circuit connected in series to a sixth circuit. Diode (D6) and the first reactor (L1) On the other hand, a third auxiliary switch (S3) connected in parallel via the third diode (D3), and a fourth diode (D4) to the second reactor (L2). A fourth auxiliary switch (S4) connected in parallel and a first and second main control pulse for controlling ON of the first and second main switches (TR1, TR2) are provided for a predetermined time. A first auxiliary control pulse, which is generated with a gap (Ta), for turning on the first auxiliary switch (S1) is generated at least from the trailing edge of the second main control pulse to the first main control pulse. A second auxiliary control pulse, which is generated so as to include a part of the period up to the leading edge of the control pulse, for turning on the second auxiliary switch (S2) is generated at least after the first main control pulse. From the edge to the leading edge of the second main control pulse A third auxiliary control pulse for controlling ON of the third auxiliary switch (S3), which is generated so as to have a predetermined time gap between the first auxiliary control pulse and the first auxiliary control pulse. Occurs during at least a part of a period in which both the first auxiliary switch (S1) and the first diode (D1) are simultaneously turned on, and controls the fourth auxiliary switch (S4) to be turned on. A switch control circuit for generating a fourth auxiliary control pulse for at least a part of a period in which both the second auxiliary switch (S2) and the second diode (D2) are simultaneously turned on. Inverter device characterized in that. 2. The first and second main resonance switches (TR1, TR2) are connected in parallel with first and second auxiliary resonance capacitors (Ca, Cb). An inverter device according to Item 1. 3. The first auxiliary switch (S1)
And a first backflow blocking diode (Da) connected in series to the first reactor (L1), the second auxiliary switch (S2) and the second reactor (L2). An inverter device according to claim 1 or 2, further comprising a second backflow blocking diode (Db) connected in series. 4. One or a plurality of switch circuits are connected between one end and the other end of the DC power source, and the switch circuits connect a load with a current in a first direction and a current in a second direction opposite thereto. In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It is composed of a series circuit of first and second main switches (TR1, TR2), and includes the first and second main switches (TR1, T2).
R2) a main conversion circuit whose interconnection middle point is connected to a load, and first and second diodes (D1, D2) antiparallel connected to the first and second main switches (TR1, TR2).
), A series circuit of first and second auxiliary switches (S1, S2) connected between one end and the other end of the power source (1), and the first and second main switches (TR1, TR2) interconnection middle point and the first and second auxiliary switches (S1,
S2) a reactor (La) connected to the interconnection middle point, and one end of which is the first and second main switches (TR1, T).
A first capacitor (C1) connected to the interconnection middle point of R2) and one end of which is the first and second main switches (TR1, T1).
A second capacitor (C2) connected to the interconnection middle point of R2) and the other end of the first capacitor (C1) and the first and second auxiliary switches (S1, S2) A third diode (D3) connected between the first and second auxiliary switches (S1, S2) and the other end of the second capacitor (C2). A fourth diode (D4) connected in between, the first capacitor (C1) and the reactor (La)
) And the second auxiliary switch (S2) are connected in series to a fifth diode (D5) connected in parallel, the first auxiliary switch (S1) and the reactor ( L
a) and a second capacitor (C2) connected in series to a sixth diode (D6) connected in parallel to the circuit, and the reactor (La) to the third diode. A third auxiliary switch (S3) connected in parallel via (D3) and a fourth auxiliary switch connected in parallel to the reactor (La) via the fourth diode (D4). (S4) and the first and second main control pulses for turning on the first and second main switches (TR1, TR2) are generated with a predetermined time gap (Ta) between them. A first auxiliary control pulse for turning on the first auxiliary switch (S1) is at least one of a period from a trailing edge of the second main control pulse to a leading edge of the first main control pulse. And the second auxiliary switch is generated. The second auxiliary control pulse for controlling ON of the switch (S2) includes at least a part of the period from the trailing edge of the first main control pulse to the leading edge of the second main control pulse, and A third auxiliary control pulse is generated so as to have a predetermined time gap between the first auxiliary switch (S1) and the third auxiliary switch (S3). ) And the first diode (D1) are both turned on at the same time, and a fourth auxiliary control pulse for turning on the fourth auxiliary switch (S4) is generated. An inverter device comprising: a switch control circuit that is generated during at least a part of a period in which both the second auxiliary switch (S2) and the second diode (D2) are simultaneously turned on. . 5. Further, first and second auxiliary resonance capacitors (Ca, Cb) are connected in parallel to the first and second main switches (TR1, TR2). An inverter device according to item 4. 6. A first backflow blocking diode (Da) connected in series with the first auxiliary switch.
And a second reverse current blocking diode (Db) connected in series with the second auxiliary switch (S2).