JPH08149484A - Video signal converter - Google Patents

Abstract

PURPOSE: To provide the video signal converter suitable for the interface conversion of an image signal connected between a signal generator and an image display device. CONSTITUTION: A luminance signal I and video signals R, G and B, for which the timing is matched with a clock signal CK, are inputted through flip-flop circuits 6R, 6G and 6B to respective data selectors 8R, 8G and 8B and an analog signal equipped with a level provided by the logical operations of the luminance signal I and the video signals R, G and B at the data selectors 8R, 8G and 8B is provided. That signal is amplified by amplifiers 13R, 13G and 13B while combining resistors 12R, 12G and 12B and resistors 9R1, 9R2, 9R3, 9G1, 9G2, 9G3, 9B1, 9B2 and 9B3 and video signals R', G' and B' of analog outputs and synchronizing signals H' and V' outputted through a buffer circuit are outputted to the image display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal converter which is used by being connected between a signal generator which is an information processing device such as a personal computer and an image display device and which is suitable for interface conversion of image signals. .

[0002]

2. Description of the Related Art Conventionally, TTL output and analog output are available as interfaces for image signals output from a signal generator which is an information processing device such as a personal computer. The signal generator whose interface is a TTL output is used by being connected to an image display apparatus whose interface is TTL, and the signal generator whose interface is an analog output is used by being connected to an image display apparatus whose interface is an analog.

[0003]

As described above, the image signals of each interface can be connected only to the image display device of each dedicated interface, and other combinations are impossible. Therefore, it is impossible to directly connect the image signal output from the TTL interface to the image display device of the analog interface (1VP-P 75Ω).

When the display color is doubled by the luminance signal I, the interface having the TTL output can be used only for the dedicated image display device. Further, the image signal of the TTL interface including the luminance signal I could not be connected to the image display device of the analog interface only by adjusting the voltage level.

As described above, in the conventional image signal interface, there is a big problem that the generally used analog image display device cannot be effectively utilized.

An object of the present invention is to provide a video signal converter which can solve these problems with a simple structure and which is suitable for interface conversion of an image signal connected between a signal generator and an image display device.

[0007]

A flip-flop is constructed so that video signals R, G and B, which are TTL level image signals, synchronizing signals H and V, and a luminance signal I and a clock signal CK are input. Circuits 6R, 6G, 6
The luminance signal I and the video signals R, G, B whose timings are adjusted by the clock signal CK via B, 7 are input to the respective data selectors 8R, 8G, 8B, and the luminance signals in the respective data selectors 8R, 8G, 8B An analog signal having a level obtained by the logical operation of I and the video signals R, G, B is applied to the resistors 9R1, 9R2, 9R3, 9G1, 9G2 corresponding to the resistors 12R, 12G, 12B.
Amplifier 1 selected from 9G3, 9B1, 9B2, 9B3
Video signals R ', G', B'amplified by 3R, 13G, 13B and synchronization signals H ', V'output through the buffer circuits 10, 11 are output to the image display device. Is.

In the video signal converter, the input synchronizing signals H and V may be mixed by an exclusive OR circuit and may be superposed on the video signal G'through a capacitor.

[0009]

The TTL level video signals R, B, G and the luminance signal I are synchronized by the timing of the clock signal CK in the flip-flop circuit (FF) and converted into analog voltages of several gradations in the data selector. Since the impedance is converted by the amplifier, analog level video signals respectively synchronized with the clock signal CK can be output to the image display device.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a main part of the present invention, FIG. 2 is a specific circuit configuration diagram of FIG. 1, and FIG. 3 is a specific circuit configuration diagram of a video signal R in FIG. In the figure, 1 is a signal generator for outputting a TTL level image signal, 2 and 4 are multi-core metal cables, 3 is a video signal converter, and 5 is an analog interface image display device.

In the figure, 6R, 6G, 6B and 7 are flip-flop circuits (FF) each of which is a known circuit, and 8R, 8G and 8B are input video signals R and
This is a data selector for generating analog voltages of several gradations by the logical action of G and B and the luminance signal I. Also, 9R1, 9R2, 9R3, 9G1, 9G2
9G3, 9B1, 9B2, 9B3, 12R, 12G, 1
2B, 14R, 14G, and 14B are resistors, and 13R, 13G, and 13B are amplifiers for impedance conversion to output in 75 Ω system, respectively.
Reference numerals 0 and 11 are buffer circuits each composed of a known circuit.

According to the video signal converter of the present invention having such a configuration, the image signal output from the signal generator 1 is transmitted to the image display device 5 as follows. First,
Video signals R, G, B of each TTL level as image signals
And synchronization signals H and V, luminance signal I, and clock signal CK
Are output from the signal generator 1 and input to the video signal converter 3 via the metal cable 2. And
The TTL level image signal input to the video signal converter 3 is converted into an analog voltage of three gradations and amplified in the video signal converter 3, and the metal cable 4 is also used.
Is output to the image display device 5 by using the video signal R (red) as an example, referring to FIG. 2 and FIG.
This will be specifically described.

In the figure, the video signal R (red) output from the signal generator 1 and the clock signal CK are input to the flip-flop circuit 6R for the video signal R, and the luminance signal I and the clock signal CK are the video signals. It is input to the flip-flop circuit 7 common to R, G and B. Then, the video signal R and the luminance signal I are synchronized by utilizing the timing of the clock signal CK in the respective flip-flop circuits 6R and 7, and the synchronized video signal R and luminance signal I are the video signal R. Data selector 8R. In the data selector 8R, an analog voltage determined by the resistor 12R and appropriately selected resistors 9R1, 9R2, 9R3 is generated by the logical action corresponding to the HIGH and LOW states of the video signal R and the luminance signal I, respectively. . The analog voltage generated by the data selector 8R is, for example, the video signal R and the luminance signal I.
Is HIGH when the video signal R and the luminance signal I are LOW, respectively, and 0V when the video signal R is HIGH and the luminance signal I is LOW,
It becomes the voltage like this. And the data selector 8R
The analog voltage generated from is output as an analog video signal R ′ whose impedance is converted by the amplifier 13R so that the analog voltage can be output to the analog interface system.

Similarly, a TTL level video signal G,
B is converted and output as analog video signals G'and B '. In this way, the TTL level video signal R,
G and B are converted by the luminance signal I and the clock signal CK into analog video signals R ', G', and B'having respective levels. The TTL level sync signals H and V are output as TTL level or analog sync signals H ′ and V ′ through the buffers 10 and 11, and the TTL 7-line video signal is converted into an analog 5-line video signal. Output.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. In this embodiment, TTL level synchronizing signals H and V are mixed by an exclusive OR circuit 17, and the mixed signal is stored in a capacitor 18. It is configured to be superimposed on the video signal G ′ via Therefore, 7 at TTL level
Since it is possible to convert the video signal of the line to the video signal of 3 lines at the analog level, the number of cores of the optical fiber cable can be reduced from 7 to 3 by transmitting by the optical image transmission method, and inexpensive video signal conversion It becomes possible to provide a container.

[0015]

According to the video signal converter of the present invention, T
Since the video signal of the TL interface can be converted into the video signal of the analog interface and output, it is possible to effectively utilize the image display device of the analog interface, which cannot be used conventionally. Further, since the luminance signal can be logically applied to the video signal to double the display color, the image quality can be greatly improved. Further, according to the optical image transmission system using the E / O converter, the number of lines of the optical fiber cable can be reduced to 5 or 3, so that an inexpensive video signal converter can be obtained. There are great practical effects.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the present invention.

FIG. 3 is a specific configuration diagram for a video signal G for explaining the present invention.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

[Explanation of symbols]

1 signal generator 2,4 multi-core metal cable 3 video signal converter 5 image display device 6R, 6G, 6B, 7 flip-flop circuit 8R, 8G, 8B data selector 9R1, 9R2, 9R3, 9G1, 9G2, 9G3, 9
B1, 9B2, 9B3 12R, 12G, 12B, 14R, 14G, 14B Resistor 10, 11 Buffer circuit 13R, 13G, 13B Amplifier 17 Excessive OR circuit 18 Capacitor R, R ', G, G', B, B 'Video signal H, H'Horizontal sync signal V, V'Vertical sync signal I Luminance signal CK Clock signal

Claims (2)

[Claims] 1. Flip-flop circuits 6R and 6G are configured so that video signals R, G and B, which are TTL level image signals, synchronization signals H and V, and a luminance signal I and a clock signal CK, respectively, are input. , 6B and 7 are input to the respective data selectors 8R, 8G and 8B, and the luminance signal I and the video signals R, G and B, which are timed by the clock signal CK, are input to the respective data selectors 8R,
Luminance signal I and video signals R, G, B in 8G, 8B
An analog signal having a level obtained by the logical operation of the resistor 9 corresponding to the resistors 12R, 12G, and 12B.
R1, 9R2, 9R3, 9G1, 9G2, 9G3, 9B
Amplifiers 13R and 13 are selected by selecting from 1, 9B2 and 9B3.
Video signals R ', which are amplified by G and 13B respectively.
A video signal converter characterized in that G ', B'and synchronizing signals H', V'output via buffer circuits 10, 11 are output to an image display device. 2. The video signal converter according to claim 1, wherein the input synchronizing signals H and V are mixed by an exclusive OR circuit 17, and a capacitor 1 is provided.
8. A video signal converter characterized by being configured to be superimposed on a video signal G'through 8.