JPS63226780A - Video signal processor - Google Patents

Abstract

PURPOSE:To rapidly read out a stored video signal by outputting a read instructing signal from an operation means so that a storing means is controlled to a readable state in synchronism with a vertical synchronizing signal in an inputted composite video signal. CONSTITUTION:A composite video signal from an input terminal 2 is stored in a field memory 9 through a brightness signal separating circuit 6, a color difference signal demodulating circuit 7 and a color difference/original color converting circuit 8. When a read instructing signal is applied from the operation means, a control signal generating circuit 15 switches a changeover switch SW1 to a reading mode in synchronism with the initial vertical synchronizing signal in the inputted composite video signal and a control signal is applied from a read control circuit 18 to a field memory 9 to read out data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention stores images obtained from television receivers, video recorders, video cameras, etc., and stores them as still images in the graphic memory of, for example, a personal computer. The present invention relates to a video signal processing device that can write data to a video signal.

BACKGROUND ART In recent years, with the advent of semiconductor memory, video signal processing devices that can store images from television receivers, video tape recorders, video cameras, etc. and write them as still images to personal computers, etc. have been developed. has been devised.

When a still image is written to a personal computer via such a video signal processing device, the personal computer can perform image processing and image analysis such as enlarging or reducing the still image, or extracting features. .

The video signal processing device is provided with a memory that stores the digitized video signal, and by providing a write control signal or a read control signal to the memory, the input video signal can be written into the memory. Alternatively, reading is performed.

Problems to be Solved by the Invention In this video signal processing device, when reading the video signal stored in the memory to the personal computer, for example, the following processing is performed. first,
When the writing of the video signal for one screen into the memory of the video signal processing device is completed, the video signal processing device outputs a signal to the personal combinator that the writing is completed. Next, a signal is output from the personal computer side to the video signal processing device asking whether it is OK to start reading. When the video signal processing device receives this signal and determines that it is ready for continuous output,
A signal indicating this is output to the personal computer.

After such a signal response is performed, the video signal stored in the memory is transferred to the personal computer B.
μ, 1! For example, the data is stored in a graphic memory provided in a personal computer. In this way, conventionally, when reading the video signal stored in the memory to the personal computer side, a signal response has to be made multiple times between the personal computer and the video signal processing device, and the It takes a long time to read out the video signal.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a video signal processing device that can read video signals stored in a memory at high speed.

Means for Solving the Problems The present invention provides a storage means in which a video signal for one field period is stored, an operating means for generating a read instruction signal for reading out the stored contents of the storage means, and a state in which the storage means is in a writable state. and a switching means that generates a control signal that controls the switching operation of the switching means, and the switching means that generates a control signal that controls the switching operation of the switching means. A video signal characterized in that, after a vertical synchronization signal of a composite video signal is input and a read instruction signal is input, the switching means is caused to perform a switching operation in synchronization with the first vertical synchronization signal. It is a processing device.

Function: In the video signal processing device according to the present invention, when the video signal stored in the storage means is read by the ablating means, the operation means outputs a read instruction signal to the switching control means.

The switching control means includes the video signal processor! ! J. A vertical synchronization signal of a composite video signal is input to the device. When a read instruction signal from the operating means is input to this switching control means, a control signal is output in synchronization with the first vertical synchronization signal after input of the read instruction signal. In this way, the control signal output from the switching control means is applied to the switching means, thereby controlling the switching operation of the switching means. That is, the switching means can switch and control the storage means between a writable state and a readable state based on the control signal.

Therefore, in the video signal processing device, by outputting a read instruction signal from the operating means, the storage means can be selectively changed from a writable state to a continuous readable state in constant synchronization with the vertical synchronization signal of the input composite video signal. can be controlled. In addition, since the storage means is brought into a readable state only by outputting a read instruction signal from the operation means, it is possible to read out the video signal stored in the storage means at high speed.

Embodiment FIG. 1 shows a video signal processing device 1 which is an embodiment of the present invention.
FIG. 2 is a block diagram showing the electrical configuration of FIG.

The video signal processing device 11 includes an input terminal 2 that is connected to, for example, a television receiver or a video tape recorder to which a composite video signal is input, and a connection section that is connected to a 7 address bus and a data bus of a personal computer 3. 4 is provided.

From the composite video signal inputted from the input terminal 2, a luminance signal Y is separated in a luminance signal separation circuit 6, and demodulated in a color difference signal demodulation circuit 7, resulting in a (B-Y) signal, a (R-Y) signal, and Three color difference signals of the (G-Y) signal are obtained.

These three color difference signals are respectively given to the color difference/primary color conversion circuit 8 together with the brightness signal Y separated by the brightness signal separation circuit 6, and are converted into three primary color signals, namely BM,
It is converted into an R signal and a G signal. These primary color signals are output to the field memory 9, where they are digitized and written as a still image for one field.

The field memory 9 is composed of three field memories 10, 11, and 12 for B signal, R signal, and G signal, and a serial access method is used for both input and output. Each field memory 10.1
These field memories 10, 11 .
12 is shifted by one dot in the column direction when a serial clock signal, which will be described later, is applied, and shifted by one line in the row direction, when an increment pulse signal, which will be described later, is applied. Note that in this embodiment, for simplicity, each field memory 10.11.12
Each dot will be explained as having a 1-bit configuration.

The input composite video signal applied to the luminance signal separation circuit 6 is also applied to a synchronization signal separation circuit 13, where horizontal and vertical synchronization signals are separated. This synchronization signal separation circuit 1
The output of No. 3 is applied to the color difference signal demodulation circuit 7 for clamping operation, and is also applied to the write control circuit 14. The vertical synchronization signal separated by the second synchronization signal separation circuit 13 is sent to the control/signal generation circuit 15, which will be described later.
It is also given to

The write control circuit 14 has, for example, 28°636
A clock signal output from a write clock signal oscillator 16 having an oscillation frequency of MHz is applied via a frequency dividing circuit 17. In the write control circuit 14, a plurality of write control signals are created based on the synchronization signal output from the synchronization signal separation diagram @13 and the clock signal output from the write clock signal oscillator 16. These plurality of write control signals are applied to the field memory 9 via the read/write mode changeover switch SW1. Each primary color signal output from the color difference/primary color conversion circuit 8 is digitized and written into the field memory 9 based on the plurality of write control signals.

On the other hand, address bus! 1 and data bus! 2 are respectively connected to an address bus and a data bus (not shown) within the personal computer 3 via the connection section 4. The output signals of the personal computer 3 are each an address bus! 1 and data bus! 2 to the read control circuit 18 and the control signal generation circuit 15.

Note that a clock signal having a frequency of 4 MHz, for example, used in the personal computer 3 is applied to the readout control circuit 18 from the personal computer 3 via the connection g4. The read control circuit 18 generates a plurality of read control signals based on the output signal of the personal computer 3 and the clock signal. These plurality of readout control signals are transmitted through the changeover switch S.
The signal is applied to the field memory 9 via W1.

When these plurality of readout control signals are applied to the field memory 9, each color data written in each field memory 10, 11, and 12 for the Bff, R, and G signals is sequentially transferred to the primary color signal changeover switch. It is output to SW2. The primary color changeover switch SW2 is switched by a switching control signal output from the personal computer 3, and is controlled to selectively output blue data, red data, and green data, for example, in this order to the serial/parallel conversion circuit 19. .

In the serial/parallel conversion circuit 19, each color data serially inputted via the changeover switch SW2 is converted into parallel data and outputted to the personal computer 3 via the data bus 12. The parallel converted color data is written into a graphic memory (not shown) provided in the personal computer 3.

When the video signal is written into the graphic memory in this manner, image processing can be performed by normal operation of the personal computer 3.

FIG. 2 is a timing chart for explaining the operation of the field memory 9. FIG. 1 (1) shows a composite video signal for only one horizontal scanning line. In this composite video signal, the period from time to to time t1 is the horizontal blanking period 7)'), II)IJt
l Empty time 1rJ t 2ma-Cf) MrmT1ftt
This is the period of the video signal (see (2) in the same figure) 6 In this embodiment, the serial clock signal as shown in (3) in the same figure is applied to the field memory 9 into which such a composite video signal is input. SC is given. As a result, in the write period Tw within the video signal period T1, the analog video signal is digitalized and written into the field memory 9 as serial data.

Next, the reading operation of the field memory 9 will be explained. Each color data written in the field memory 9 is given to the personal computer 3 via the data bus 2. Memory 10 for B signal, R signal and G signal
, 11, 12 are sequentially switched from blue data to red data to green data by the changeover switch SW2, converted into parallel data by the conversion circuit 19, and output onto the data bus of the personal computer 3. be done. That is, when reading the data written in the field memory 9, first, for example, 8 pins are output from the beginning of the B signal field memory 10, and all the blue pins written in the B signal field memory 1o are output. When the data is output, the first 8-bit data of the R signal field memory 11 is read out. In this way G
When all the data in the signal field memory 12 is read out, the reading out for one screen is completed (see FIG. 3).

The reason why such a reading method is necessary is that the data bus of a personal computer normally has only 8 bits.

FIG. 4 is a timing chart for explaining the basic operation of this embodiment. The operation related to the changeover switch SW1 will be described below with reference to FIGS. 1 and 4.

Note Switching between the read mode and the write mode in the video decoding processing device 1 is performed by the changeover switch SW1. That is, when the changeover switch SWI is switched to the write mode side, a write control signal output from the write control circuit 14 is applied to the field memory 9. When the read mode is switched to 1llll (on the personal computer 3 side), a read control signal output from the read control circuit 18 is applied to the field memory 9.

When the changeover switch SW1 is switched to the read mode,
From the read control circuit 18, for example, FIGS.
), namely, the read 7g operation control signal RAS, the serial clock signal SC, the refresh control signal REF, the enable signal WE, the increment signal INC, and the upstream row reset signal RCR. A control signal is applied to the field memory 9 via the changeover switch SWI. As a result, the data written in the field memory 9 is read out.

For example, in the period from time ts to time tn, R
Red data for one screen is read out from the signal field memory 11. During the period from time EI La to time tb, one row of red data is serially read out using the serial clock signal SCB, refresh control signal REF, and the like.

The switching control of this changeover switch SW1 is controlled by the switching control signal A output from the control signal generating circuit 15. That is, when the switching side transport signal A is at L level, the mode is a write mode, and when it is at an H level, the mode is a read mode (see FIG. 4 (3)).

The control signal generation circuit 15 includes, for example, a D-type 7-lip 70-tube, and outputs the switching control signal A.
For example, it outputs a clock switching signal for controlling the frequency dividing period of the frequency dividing circuit 17.

Further, as described above, the vertical synchronizing signal V is inputted to the control signal generating circuit 15 from the matching signal separating circuit 13 (see (2) in the same figure).

Therefore, for example, when the video signal processing device 1 is in the write mode, if the personal computer 3 wants to switch to the read mode, the control signal of l-level from the personal combination 1-3 is sent to the control signal generation circuit 15. Output to. For example, when the control signal becomes H level at time 10 (see (1) in the figure), at the rising edge of the vertical synchronization signal (see time L1) immediately after this,
The switching control signal A becomes H level and this state is maintained.

When the switching control signal A becomes H level in this way,
As described above, the changeover switch SWI is switched to the read mode side 9, and the respective field memories 10, 11, and 12 are sequentially read out. That is, from time t2 to time t3, blue data is first sent to the personal computer 3. From time t3 to time t4 and from time 4 to time L5, red data and green data are sent to the burner computer 3, respectively. In this way, at time 5, 1ii! is written in the field memory 9! Transmission of still image data for i1 page is completed.

In this way, switching from the write mode to the read mode is realized from the personal computer 3. As mentioned above, this switching timing is determined by the control signal A! It is synchronized not when the level reaches 4, but at the rising edge of the vertical synchronizing signal immediately after that. That is, switching to the read mode is performed after waiting for the vertical blanking period TB (see (7) in the figure).

When the reading of the video signal is completed, the personal computer 3 sets the control signal to the L level at time t6. As a result, the switching control signal A, which is the output of the control signal generating circuit 15, goes to the L level at the rising edge of the vertical synchronizing signal (2) immediately after this (see time mark 7), and the selector switch SW1 is switched to the write mode side. Note that at this time t7, since each color data in the field memory 9 has just been read out, no data has been written in the field memory 9.

Therefore, after time L7, since the mode is switched to the write mode, the input video signal is again written into this field memory 9 as one field's worth of still images.

Note that the switching of the read mode is performed during the vertical blanking period T.
The purpose of waiting for I3 is to accurately read out one screen's worth of video numbers. That is, if the mode is switched to the read mode without waiting for the vertical blanking period TB, an unsightly phenomenon will occur in which, for example, the image is switched in the middle of the displayed screen. Further, the time required for the readout operation for one screen is determined by the timing at which the burner computer 3 sets the control signal A to the L level. That is, the FA! required for the read operation! This is because the switching timing waits for the vertical blanking period, so that each waiting time occurs before and after the read operation. In this embodiment, the reading time for the read operation is approximately 0.2 seconds on average.

The time required for a write operation in write mode is one field period, or 1760 seconds.

Further, as described above, when the read operation is completed, the mode is switched to the write mode, and each color data for one screen is written into the field memory 9 again.

Furthermore, the timing of switching to the read mode is performed after waiting for the vertical blanking period. Therefore, the personal computer 3 can set the frfr control signal A to H level at any time.

That is, no matter when the personal computer 3 issues a read command to set the control signal A to I level,
It is possible to always accurately read out one screen. Also,
The video signal path 3! l! In the lil 1, when changing to the read mode, this can be realized without exchanging various signals as described in the prior art section. Therefore, in this video signal processing device 1, a still image of a video signal can be written to the graphic memory in the personal computer 3 at high speed.

Effects As described above, in the video signal processing device according to the present invention, when the storage means is placed in a readable state, this can be realized by outputting only a read instruction signal from the operation means.

Therefore, responses to various control signals as described in the prior art section can be significantly suppressed, and the read operation of the storage means can be performed at high speed.

Furthermore, the switching timing between the writable state and the readable state is synchronized with the vertical synchronization signal regardless of the output timing of the read signal, so that one field's worth of taste image signals can always be read out accurately.

[Brief explanation of the drawing]

FIG. 1 shows a video signal processing device ra1 which is an embodiment of the present invention.
2 is a timing chart for explaining the operation of the field memory 9 in the write mode. FIG. 3 is a timing chart for explaining the operation of the field memory 9 in the read mode. FIG. 4 is a timing chart for explaining the operation related to the changeover switch SWI, and FIG. 5 is a timing chart showing an example of a read control signal output from the read control circuit 18. 1... Video signal processing device, 2... Input terminal, 3...
・Personal computer, 4...Connection part, 9...
Field memory, 13... Synchronization signal separation circuit, 14
...Write control circuit, 15...Control signal generation circuit,
18...Read control circuit, SWI...Read/write mode selection switch

Claims (1)

[Scope of Claims] 1. A storage means in which a video signal of a field period is stored, an operating means for generating a read instruction signal to read out the stored contents of the storage means, and a state in which the storage means is placed in a writable state and a readable state. and a switching control means that generates a control signal to control the switching operation of the switching means, and the switching control means receives the read instruction signal and the vertical synchronization signal of the composite video signal. 1. A video signal processing device, wherein the switching means is configured to perform a switching operation in synchronization with a first vertical synchronization signal after a readout instruction signal is inputted.