JPH08149010A - Analog-digital converter - Google Patents

Abstract

PURPOSE: To attain the A/D conversion of high resolution in a simple circuit constitution by comparing the phase of the signal transmitted via a delay circuit with the phase of the carrier output that is not transmitted via the delay circuit and then digitizing the comparison output. CONSTITUTION: The output of a carrier circuit 1 is branched into two parts by a distributor 2, and one of these two branched outputs of the distributor 2 is branched into 2<n-1> parts by a distributor 41. Then one of these 2<n-1> outputs is connected to a phase comparator 61 and others are connected to the phase comparators 62 to 6 (2<n> -1) via the delay circuits 52 to 5 (2<n> -1). In regard to the delay times of the circuits 52 to 5 (2<n> -1), the circuit 52 is delayed by T/2<n+1> . Thereafter the delay time is increase by t/2<n+1> and the i-th delay time is (i-1)0 T/2<n+1> . The other output of the distributor 2 is branched into 2<n> -<1> by a distributor 42 via a phase modulator 3 and a delay circuit 50 and inputted to the other terminal of the phase comparators 61 to 6 (2<n> -<1> ). Then an analog signal is inputted to the modulator 3, and the output of each phase comparator is outputted via a logical gate 7.

Description

Detailed Description of the Invention

[0001]

The present invention is used in high speed analog-to-digital conversion. The present invention is suitable for use in a sampling oscilloscope. The present invention is suitable for use in an LSI tester.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG. FIG. 12 is a block diagram of a conventional device. Hereinafter, in order to make the description easy to understand, the resolution (the number of bits n) is described as “4”. The outputs of the carrier wave generation circuit 1 are divided into signals having the same number as the resolution (4 bits) and the same phase by the distributors 21, 23 and 26. Each branch thus divided corresponds to a data bit.

The signal split into each branch is further split into two signals of equal phase (22, 24, 25, 27).
One of them is input to the phase comparators 61 to 64 via the phase modulators P1 to P4. The other divided signal is input to the same phase comparators 61 to 64 as a reference signal. The outputs of the phase comparators 61 to 64 are the filters 15
It is input to the amplitude comparators 161 to 164 via 1 to 154. This output is the digital signal output.

The modulation depth control terminals of the phase modulators P1 to Pn are connected to the analog signal input terminal 10 via the buffer amplifier 11. Phase modulators P1 to P connected between the distributors 21 to 27 and the phase comparators 61 to 64 at each branch.
The modulation depth of n is 0 to π radians in the branch corresponding to the MSB, and doubles as the number of digits decreases. In this conventional example, this is realized by connecting a plurality of phase modulators 3 having a modulation depth of 0 to π radians in series. In other words, the number of MSB branches is 1 and the next bit is 2 so that the number increases by 2 as the number of digits decreases, and the LSB (least significant bit: Least
Significant Bit) is 2 ^n-1 . That is, n
= 4, so there are eight.

Next, the operation of the conventional example will be described. The sine wave output from the carrier wave generation circuit 1 is divided into two signals having the same phase. The sine wave signal has a frequency sufficiently higher than the band of the analog signal input, and the higher the purity, the better. One of the phases is changed in proportion to the amplitude of the analog signal input. The phase of the other divided signal is compared by the phase comparators 61-64. In this conventional example, multipliers are used as the phase comparators 61-64. The product of two sine functions with different phases is sin (ωt + θ) × sin ωt = 1/2 [cos θ−
cos (2ωt + θ)]. Where ω is the angular frequency, t is the time, and θ is the phase difference. As a result, the filters 151 to 1 are added to the output of the multiplier.
It can be seen that an output proportional to the cosine of the phase difference can be obtained by multiplying by 54 and removing the double frequency component of the original sine wave.

When the analog signal input changes from zero to full scale, the phase of the phase modulator P1 corresponding to the MSB changes from 0 to π radian, so the phase comparator 61
The output of is proportional to the half cycle of the cosine function.
Amplitude comparators 161 to 164 having zero as a reference level
By passing through, digital data whose input is high level up to half the full scale and low level above that can be obtained. Thereafter, digital data similar to the above operation principle can be obtained in the same manner. FIG. 13 is a diagram showing the relationship between the analog signal strength and the outputs of the filters 151 to 154 and the digital signal output. The horizontal axis represents the analog signal strength, and the vertical axis represents the filter output and digital signal output. The phases of the outputs of the filters 151 to 154 are proportional to the analog signal input from the analog signal input terminal 10, and the modulation depth thereof is as shown in FIGS. 13 (a) to 13 (d) with respect to the full scale of the input. Then, it will be doubled in sequence. The outputs of the filters 151 to 154 are input to the amplitude comparators 161 to 164 and output as digital signals (see Japanese Patent Application No. 6-022632, not yet published at the time of filing of the present application).

[0007]

In the analog-to-digital converter shown in the conventional example, the maximum frequency of the analog input is limited to f _C / 2 ^{n -1} (f _C is the carrier frequency, n is the resolution (bit)). To be done. Because the speed of the phase change is equal to the input in MSB, increases by 2 as the digit goes down, and becomes 2 ^n-1 times in LSB, so that the phase change of LSB matches the carrier frequency. Becomes

Therefore, if the carrier frequency is fixed and the resolution is increased, the upper limit frequency that can be converted is lowered, while if the upper limit frequency is increased, a high carrier frequency is required. For example, 1 bit / s at 8 bits
In order to realize the above speed, a carrier signal of 128 GHz is required.

Further, in the conventional example, a large number of variable phase shifters are required to achieve high resolution. Although it depends on the method, the number of resolutions (unit bits) is roughly equal to the power of 2. The conversion speed is limited by the delay time of these phase shifters. Further, since it is necessary to drive a large number of these phase shifters, a large driving capability is required for the analog input.

The present invention has been made against such a background, and an analog circuit with high resolution can be provided by a simple circuit structure.
It is an object of the present invention to provide an analog / digital converter capable of realizing digital conversion. The present invention
It is an object of the present invention to provide an analog / digital converter capable of performing high speed analog / digital conversion.

[0011]

A first aspect of the present invention is an analog-digital converter, which is characterized by an analog signal input terminal (10), a carrier wave generation circuit (1), and A first phase modulator (3) for phase-modulating a carrier wave with an analog signal, wherein the carrier wave and the output signal of the first phase modulator are relatively (2 ⁿ
-1) Delays with different stages (n is resolution) are given (2 ⁿ
-1) delay circuits (5) are provided in the carrier wave output path or the first phase modulator output path, and ( ^2n-
1) The number of delay circuits (5) is such that the relative delay time of the i-th (i ≦ n) delay circuit is (i−1) · T / (2 ^{n + 1} ) (where T is the carrier wave period). (2 ⁿ -1) first phase comparisons that compare the phase of the signal that has been set and that has passed through this delay circuit with the phase of the carrier wave output that does not pass through this delay circuit or the output of the first phase modulator (6) and this first phase comparator (6)
And a logic gate (7) which outputs an n-bit digital signal as an input.

All the delay circuits (5) are provided on the carrier wave output path side, and a fixed T. [(1/4) -2- ^{(n + 1)} ] is provided in the first phase modulator output path. It is desirable that the delay circuit (50) is inserted.

Alternatively, the delay circuit (5) may be inserted into the carrier wave output passage side and the first phase modulator output passage side substantially equally.

The carrier wave used in the present invention is preferably a sine wave.

The delay circuit may have a structure in which a plurality of stages of delay elements each having a unit delay time T / 2 ^{n + 1} are connected in cascade.

A second aspect of the present invention is an analog-to-digital converter, which is characterized in that it is provided with a plurality of m second phase modulators for phase-modulating a carrier wave by analog signals. The second phase modulators have a modulation depth of θ × 2 ^{j−1 for the j-} th (j ≦ m) modulator, where θ is a constant, and the m second phase modulators B-type analog-digital converter including m second phase comparators for comparing the output phase with the phase of the carrier wave respectively, and the analog-digital converter (this is referred to as A-type analog-digital converter) And a common analog signal input, the output of the B-type analog-digital converter becomes an upper bit output and the output of the A-type analog-digital converter becomes a lower bit output.

[0017]

In the present invention, delays having different (2 ⁿ -1) stages (n is resolution) are gradually provided between the carrier signal and the signal phase-modulated by the analog signal. This (2 ⁿ -1)
The stage delay has a relative delay time of (i−1) · T / (2 ^{n + 1} ) (where T is a carrier frequency) for the i-th (i ≦ n) delay. The phase of the signal having this delay is compared with the phase of the signal not having this delay in (2 ⁿ -1) stages. Based on this comparison result, an n-bit digital signal is generated and output.

Also, a plurality of carrier waves are formed by analog signals.
Each of the phases is phase-shifted, and this n-stage phase modulation
The th (i ≦ n) th modulation depth is θ × 2 ^{i−1 where} θ is a constant and the output phase of this n-stage phase modulation is compared with the phase of the carrier wave. It is also possible to generate and output an n-bit digital signal based on the comparison result. By using this method and the method described above in combination, for example, the upper bits can be digitally output by this method and the lower bits can be digitally output by the above method. By doing so, an analog-digital converter can be realized with a small amount of hardware.

[0019]

【Example】

(First Embodiment) The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the first embodiment of the present invention.

The present invention is an analog-digital converter, which is characterized by the analog signal input terminal 1
0, a carrier wave generating circuit 1 for generating a sine wave, and a phase modulator 3 for phase-modulating this carrier wave with an analog signal, and a relative (2) is provided between the carrier wave and the output signal of the phase modulator 3. (2 ⁿ -1) delay circuits 52 to 5 (2 ⁿ -1) giving different delays of ⁿ -1) stages (n is resolution)
Is provided in the distributor 41 as the carrier output path or the distributor 42 as the output path of the phase modulator 3, and
^{The n} −1) delay circuits 52 to 5 (2 ⁿ −1) have a relative delay time of (i−1) · T / (2 ^{n + 1} ) for the i-th (i ≦ n) delay circuit 5 i. (where, T is the carrier period) is set to, the carrier that is not via the delay circuit from 52 to 5 (2 ⁿ -1) delay circuit the phase of the signal through from 52 to 5 (2 ⁿ -1) (2 ⁿ -1) phase comparators 61 to 61 for comparing the output or the phase of the output of the phase modulator 3
6 and (2 ⁿ -1), the phase comparator 61~6 (2 ⁿ -
It is provided with a logic gate 7 which receives the output of 1) as an input and outputs an n-bit digital signal.

In the first embodiment of the present invention, the delay circuits 52-5 are provided.
(2 ⁿ -1) are all provided on the side of the distributor 41, and a fixed delay circuit of T · [(1/4) -2- ^{(n + 1)} ] is provided in the output path of the first phase modulator. 50 is inserted.

The output of the carrier wave generating circuit 1 is branched into two by the distributor 2. One of the outputs of the distributor 2 is 2 in the distributor 41.
^n-1 (n is a resolution (bit)), one is passed to the phase comparator 61, and the rest is passed through the delay circuits 52 to 5 (2 ⁿ -1) to the phase comparators 62 to 6 (2 ^n). -1) is connected. The delay time of the delay circuit 52~5 (2 ⁿ -1), the delay circuit 52 is T / 2 ^{n +} 1 (T is the period of the carrier wave), increasing T / 2 ^{n + 1} at a time in sequence below, i-th delay (I-1) ・ T /
It becomes 2 ^{n + 1} . The other output of the distributor 2 is (2 ⁿ −
1) and is input to the other terminals of the phase comparators 61 to 6 (2 ⁿ -1). The delay time of the delay circuit 50 is T · (1 / 4−2− ^{(n + 1)} ), which is equal to the central one of the (2 ⁿ −1) delay circuits. An analog signal input is applied to the phase control terminal 10 of the phase modulator 3. The outputs of the phase comparators 61 to 6 (2 ⁿ −1) are output via the logic gate 7.

Next, the operation of the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows the phase comparators 61 to 6
It is a figure which shows the relationship between the phase difference which (2 ^<n- 1 ^> ) detects, and an output. The horizontal axis shows the phase difference, and the vertical axis shows the output state. FIG. 3 is a diagram showing input / output waveforms of the logic gate 7.
The horizontal axis shows the analog input level, and the vertical axis shows the state of the input / output waveform. First, the sine wave output from the carrier generation circuit 1 is divided into two signals having the same phase by the distributor 2. The phase modulator 3 changes one of the phases in proportion to the amplitude of the analog signal input. This is compared with the phase of the other divided signal by the phase comparators 61 to 6 (2 ⁿ -1).

Now, when the analog signal input changes from 0 to full scale, the phase of the phase modulator 3 changes from 0 to π.
Suppose it changes to radians. Further, the phase comparators 61 to 61
6 Characteristics of (2 ⁿ -1) is output when the phase difference between the input as shown in FIG. 2 is a [pi ± [pi / 2 radians H, 0 ± π / 2
To L. Then, the output from each phase comparator is shown in FIG.
As shown in (a). In addition, in this FIG.
Examples of bits are shown below. When this is subjected to a logical operation by the logic gate 7, the output is as shown in FIG. 3B, and the analog input is converted into a gray code digital signal.

A specific configuration of the phase comparators 61 to 6 (2 ⁿ -1) will be described with reference to FIG. FIG. 4 shows the phase comparator 61.
It is a figure which shows the concrete structure of-6 ( ^2n- 1). First,
The multiplier 81 multiplies two signals whose phases are to be compared. The product of two sine functions having different phases is expressed by the following equation. sin (ωt + θ) × sin ωt = 1/2 [cos θ-cos (2ωt + θ)] (5-1) where ω is an angular frequency, t is time, and θ is a phase difference.
From this, it can be seen that an output proportional to the cosine of the phase difference can be obtained by passing the output of the multiplier 81 through the filter 82 and removing the frequency component of twice the original sine wave. Then, the sign of this result is inverted (the inverted output is taken out in FIG. 4), and the amplitude comparator 83 discriminates the amplitude at the zero level to convert it into a digital signal, whereby the phase comparison characteristic shown in FIG. 2 is obtained.

A specific structure of the logic gate 7 is shown in FIG.
FIG. 5 is a diagram showing a specific configuration of the logic gate 7. The embodiment of the present invention is configured by combining a plurality of exclusive OR gates.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of a second embodiment device of the present invention. As shown in FIG. 6, the phase comparator 61
6 (2 ^n-1 -1) has one input connected to the distributor 41, and the other inputs of the same phase comparators 61-6 (2 ^n-1 -1) have delay circuits 51-5 (2). ^It is connected to the distributor 42 via ^n-1 -1). The phase comparator 6 (2 ^n-1 ) is directly connected to the distributors 41 and 42. Phase comparator 6 (2 ^{n + 1} +
One of the inputs 1) to 6 (2 ⁿ -1) has a delay circuit 5 (2
^The same phase comparators 6 (2 ^{n + 1} +1) to 6 (2 ⁿ −) are connected to the distributor 41 via ⁿ⁻¹ +1) to 5 (2 ⁿ −1).
The other input of 1) is directly connected to the distributor 42.

With the configuration shown in FIG. 6, an analog-digital converter similar to that of the first embodiment of the present invention can be realized.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of the third embodiment device of the present invention. As shown in FIG. 7, the delay time T /
^{2n + 1} delay elements 91 to 9 ( ^2n- 2) are replaced by ( ^2n- 2)
These are connected in series, and the phase difference between before and after the connection point and each connection point and the output of the phase modulator 3 is detected.

With the configuration shown in FIG. 7, an analog-digital converter similar to that of the first embodiment of the present invention or the second embodiment of the present invention can be realized.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram of the device of the fourth embodiment of the present invention. As shown in FIG. 8, in the fourth embodiment of the present invention, an analog-digital converter is realized by applying the method of the conventional example to upper bits and the method of the present invention to lower bits. . Here, output 4
Among the bits, a method of generating the upper 2 bits by the conventional example and the lower 2 bits by this method will be described.

Phase modulators 31-34 and phase comparators 61-61
By balancing the number of 65, an analog / digital converter can be realized with a small amount of hardware. For example, in the first embodiment of the present invention, a 6-bit analog
To make a digital converter, one phase modulator 3 and 63 phase comparators 6 are required. On the other hand, the top 3
If the bits are realized by the conventional example and the lower 3 bits are realized by this method, the number of phase modulators 3 is increased to 8, but the number of phase comparators 6 is 10.

The concrete structure of the distributor 2 is shown in FIG. Figure 9
FIG. 3 is a diagram showing a specific configuration of distributor 2. It can be realized by a resistance divider, a Wilkinson divider, various directional couplers and the like as shown in FIG.

The concrete structure of the phase modulator 3 is shown in FIG. FIG. 10 is a diagram showing a specific configuration of the phase modulator 3. As shown in FIG. 10, it can be realized by combining a 90 ° hybrid and a varactor diode. By changing the reverse bias voltage of the varactor diode according to the analog input, the phase of the reflected wave can be changed, and as a result, the phase of the hybrid output can be changed. A so-called branch line coupler, rat race circuit, directional coupler, or the like can be used as the 90 ° hybrid.

The concrete structure of the phase comparator 6 is shown in FIG. FIG. 11 is a diagram showing a specific configuration of the phase comparator 6. As shown in FIG. 11, the multiplier in the phase comparator 6 can be realized by a Gilbert cell or a double balance type mixer using a diode. Besides, it can be realized by a mixer using a transistor or the like.

Besides, the delay circuit 5 or the delay element 9
As for the transmission line (coaxial cable, microstrip line, whose length is adjusted to obtain the desired delay time,
Coplanar line) and others.

[0037]

As described above, according to the present invention,
High resolution analog-to-digital conversion can be realized with a simple circuit configuration. High-speed analog / digital conversion can be performed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a phase difference detected by a phase comparator and an output.

FIG. 3 is a diagram showing input / output waveforms of a logic gate.

FIG. 4 is a diagram showing a specific configuration of a phase comparator.

FIG. 5 is a diagram showing a specific configuration of a logic gate.

FIG. 6 is a block configuration diagram of a second embodiment device of the present invention.

FIG. 7 is a block configuration diagram of a third embodiment device of the present invention.

FIG. 8 is a block configuration diagram of a fourth embodiment device of the present invention.

FIG. 9 is a diagram showing a specific configuration of a distributor.

FIG. 10 is a diagram showing a specific configuration of a phase shifter.

FIG. 11 is a diagram showing a specific configuration of a phase comparator.

FIG. 12 is a block diagram of a conventional example device.

FIG. 13 is a diagram showing the relationship between analog signal strength, filter output, and digital signal output.

[Explanation of symbols]

1 Carrier wave generation circuit 2, 21-27, 41, 42 Distributor 3, 31-34 Phase modulator 7 Logic gate 10 Analog signal input terminal 5, 50, 52-5 ( ^2n- 1) Delay circuit 6, 61- 6 (2 ⁿ -1) Phase comparator 71-73 Digital signal output terminal 81 Multiplier 82, 151-154 Filter 83 Amplitude comparator 9, 91-9 (2 ^n- 2) Delay element 161-164 Amplitude comparator

Claims (6)

[Claims] 1. An analog signal input terminal (10), a carrier wave generation circuit (1), and a first phase modulator (3) for phase-modulating this carrier wave with an analog signal. (2 ⁿ -1) delay circuits (5) that give different delays of (2 ⁿ -1) stages (n is resolution) relative to the output signal of the phase modulator of In the output path of the first phase modulator, the (2 ⁿ -1) delay circuits (5) are provided at the i-th (i≤
The relative delay time of the delay circuit of n) is set to (i-1) · T / (2 ^{n + 1} ) (where T is the carrier frequency), and the phase of the signal passing through this delay circuit is set to this delay circuit. (2 ⁿ -1) first phase comparators (6) for comparing with the phase of the carrier wave output or the first phase modulator output that has not passed through, and the first phase comparator (6)
An analog-digital converter of A type, characterized in that it has a logic gate (7) for receiving an n-bit digital signal as an input. 2. The delay circuit (5) is all provided on the carrier wave output passage side, and T. [(1/4) -2- ^{(n + 1)} ] is provided in the first phase modulator output passage. A type analog-digital converter according to claim 1, wherein said fixed delay circuit (50) is inserted. 3. The A-type analog-digital converter according to claim 1, wherein the delay circuit (5) is inserted into the carrier wave output path side and the first phase modulator output path side substantially equally. 4. The A according to claim 1, wherein the carrier wave is a sine wave.
Type analog-to-digital converter. 5. The delay circuit has a unit delay time T / 2 ^{n + 1.}
5. The A-type analog-digital converter according to claim 4, wherein said delay elements are cascaded in a plurality of stages. 6. A plurality of m second phase modulators for respectively phase-modulating a carrier wave by an analog signal are provided.
The second phase modulators have a modulation depth of θ × 2 ^{j−1 for the j-} th (j ≦ m) modulator, where θ is a constant, and the m second phase modulators A B-type analog-to-digital converter including m second phase comparators for comparing the output phase with the phase of the carrier wave, respectively.
The A type analog-digital converter described above is provided, and the B type analog
The digital converter output becomes the upper bit output, and the A
Type analog-to-digital converter output is a lower bit output, an analog-to-digital converter.