JP3133213B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used as an element of an electronic circuit. The present invention is used to simplify the circuit of an analog-to-digital converter. INDUSTRIAL APPLICABILITY The present invention is used to reduce characteristic fluctuation of an analog-to-digital converter. The present invention is suitable for use in an ultra-high speed analog-to-digital converter.

[0002]

2. Description of the Related Art The present applicant has filed a Japanese Patent Application No. 6-022632.
No. (not published at the time of filing the present application) proposed an analog-digital converter.

This analog-to-digital converter detects the phase difference between a signal obtained by modulating the phase of a reference signal by the analog signal and the reference signal, and weights the depth of the phase modulation at this time by a binary code.・ Perform digital conversion.

That is, the phase of the reference signal is modulated in proportion to the analog signal, and the periodicity of the phase modulation (the output phase reciprocates between 0 and 2π radians as the intensity of the modulated signal increases) is used. It performs analog-to-digital conversion.

[0005] The modulated signal and the reference signal are input to a phase comparator, and the output of the phase comparator is, for example, a phase difference between the phase of the modulated signal and the phase of the reference signal of 0 to (1).
/ 2) When it is within the range of π radian, “+1” is set, and (1)
/ 2) When in the range of π radian to π radian, “−
1 ". At this time, assuming that the modulation depth of the most significant bit is π radian, the output of the phase comparator is “+1” while the analog input is “0” to half the full scale.
"-1" from half full scale to full scale
Becomes Since the modulation depth of the bit at the next position is doubled, the output of the phase comparator is “+1” while the analog input is “0” to 1/4 full scale. "-1" from scale to 3/4 full scale,
From 3/4 full scale to full scale, "+
1 ". In this way, digital signal conversion is performed sequentially up to the least significant bit, and the analog signal is converted into a negative logic Gray code.

[0006] The number of phase modulators for generating a modulated signal is equal to the number of bits, and the modulation depth sequentially increases by twice as the order of the digits decreases from the most significant bit to the least significant bit.
For example, a modulation depth nθ can be created by connecting a plurality of phase modulation elements having a modulation depth θ in series and multiplying θ by the number n of connected stages. By appropriately setting the number of connection stages in this manner, a desired modulation depth can be generated.

[0007]

This analog-to-digital converter is an excellent device that can perform high-precision, high-accuracy, high-sensitivity analog-to-digital conversion. However, the number of stages of phase modulation elements having the same characteristics is high. Also need to be connected in series,
The variation of the phase modulation element becomes a problem.

[0008] In addition, analog-to-digital converters in which integrators and comparators are connected in multiple stages are known. In any case, a change in amplitude due to a change in the characteristics of the constituent elements is directly linked to an error.

SUMMARY OF THE INVENTION The present invention has been made in view of such a background, and an object of the present invention is to provide an analog-to-digital converter which simplifies hardware and is not affected by variations in hardware characteristics.

[0010]

SUMMARY OF THE INVENTION The present invention is an analog-to-digital converter, which is characterized by a reference signal generator (5) for generating a reference signal having a constant period, and a phase of the reference signal. A phase shifter (2) for displacing according to the strength of the input analog signal (1), a phase scaler (4) for generating binary signals indicating two or more different states in synchronization with the reference signal, and the phase shifter And a phase shift detector (3) for transmitting the value of the binary signal for each specific phase of the output of the device (2).

[0011] The phase scaler 2 ⁰ double frequency in synchronization with the reference signal, respectively, 2 x ^1, ..., may comprise means for generating each fold 2 ^n-1 n different binary signal desirable.

The phase shift amount detector (3) includes a trigger generator (30) for generating a trigger signal for each specific phase of the output of the phase shifter (2), and an output of the phase scaler based on the trigger signal. It is desirable to include an n-bit latch circuit for latching a binary signal.

Preferably, the phase scaler (4) includes a multiplier for multiplying the reference signal twice by n-1 times.

The phase scaler (4) may include a frequency divider which divides a signal having a frequency of 2 ^{n -1} times the reference signal by n-1 times in half.

The phase scaler (4) may be configured to include a 2 ^{n -1} stage Johnson counter.

[0016]

A reference signal having a constant period is generated, and the phase of the reference signal is shifted in accordance with the strength of the input analog signal. On the other hand, the frequency is 2 in synchronization with the reference signal.
⁰ times, 2 _^1-fold, 2 _^doubles, ........., 2 ^n-1 times by different n
At least 2 ⁿ in synchronization with the binary or reference signal
A digital signal is obtained by generating a binary signal indicating each state and extracting the value (n bits) of the binary signal for each specific phase of the signal displaced according to the intensity of the input analog signal.

The extraction may be performed, for example, by generating a trigger signal for each specific phase of the displaced signal, and latching the binary signal based on the trigger signal.

Each of the frequencies is 2 ⁰ in synchronization with the reference signal.
Fold, 2 _^1-fold, 2 _^doubles, ........., a method of generating by a factor 2 ^n-1 n different binary signal, a reference signal by a factor of two n-
The frequency may be multiplied once, or a signal having a frequency 2 ^{n -1} times the frequency of the reference signal may be frequency-divided n-1 times by half. Alternatively, a ^2n-1 Johnson counter may be used.

That is, according to the present invention, one reference signal is divided into two, one of the reference signals is phase-shifted by an analog amount, and the phase shift amount is generated based on the other reference signal. Analog-digital conversion is performed by measuring above.

That is, the phase of the reference signal is shifted in proportion to the analog signal. On the other hand, a measurement reference value of the phase shift amount is generated according to the reference signal. For example, the measurement reference value of the first bit is generated as “1” when the reference signal is within a range of 0 to π radians, and is generated as “0” when the reference signal is within a range of π radians to 2π radians. The measurement reference value of the second bit is “1” when the reference signal is within the range of 0 to (１ ／) radian, and “0” when the reference signal is within the range of (１ ／) radian to π radian. And The value is "1" from π radian to (3/2) radian, and "0" from (3/2) π radian to 2π radian. Hereinafter, similarly, the reference signal is multiplied to the required number of bits, and a measurement reference value is set.

In accordance with the measurement reference value, a phase shift amount of the reference signal shifted in proportion to the analog signal is measured, and the result is output as a digital value.

As described above, the information in the analog-to-digital converter deals only with the phase information, and adopts a configuration independent of the amplitude. -A digital converter can be realized.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a detailed block diagram of the apparatus according to the embodiment of the present invention.

The present invention relates to an analog / digital converter, which is characterized by a reference signal generator 5 for generating a reference signal having a constant period, and an analog / digital converter for converting the phase of the reference signal into an analog signal inputted from an input terminal 1. a phase shifter 2 for shifting in accordance with the intensity of the signal, 2 ⁰ double frequency respectively in synchronization with the reference signal, 2 x _^1, 2 ² _times, ........., 2 ^n-1 times by n different two Phase scaler 4 for generating value signal
And a phase shift amount detector 3 for transmitting the value (n bits) of the binary signal for each specific phase of the output of the phase shifter 2.

The phase shift amount detector 3 includes a trigger generator 30 for generating a trigger signal for each specific phase of the output of the phase shifter 2, and n trigger signals for latching the output binary signal of the phase scaler based on the trigger signal. And binary signal holders 45 to 47 as bit latch circuits.

The phase scaler 4 includes multipliers 40 and 41 for multiplying the reference signal twice by two.

In the embodiment of the present invention, a case where the output is 3 bits will be described. The reference signal generator 5 generates a system clock having a frequency f ₀ . In the embodiment of the present invention, a sine wave will be described. Trigger generator 30 of phase shift detector 3
Generates a trigger when the sine wave from the phase shifter 2 indicates a predetermined phase. The phase scaler 4
As shown in FIG. 2, multipliers 40 and 41 for doubling the sine wave from reference signal generator 5, and binary signal generators 42-4.
4. Binary signal generators 42 to 44
Is a circuit that performs a comparison operation on an input sine wave analog value with a predetermined threshold value and converts the analog value into a binary digital value.

The binary signal holders 45 to 4 of the phase shift amount detector 3
Numeral 7 holds the digital values output from the binary signal generators 42 to 44 when the latch trigger output from the trigger generator 30 is input. Binary signal holders 45 to 47
Are 1-bit outputs, and a 3-bit parallel digital value is output to the output terminal 6 as a whole.

A specific example of the phase shifter 2 will be described with reference to FIG. FIG. 3 is a diagram illustrating a specific example of the phase shifter 2. FIG.
(A) is a reflection type phase shifter using a 90 ° hybrid, and FIG. 3 (b) is a configuration diagram of a reflection type phase shifter using a circulator. If the sine wave output of the reference signal generator 5 is given to this input terminal and the capacitance value of the varactor diode is changed according to the analog value to be converted from analog to digital, an output having a phase shift θ can be obtained from the output terminal. Can be

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. FIG. 4 shows the binary signal generators 42-4.
4 is a diagram showing an input signal of No. 4. FIG. 5 shows the binary signal generator 4
It is a figure which shows the output signal of 2-44. FIG. 6 is a diagram showing the trigger timing of the trigger generator 30. If the output out ₅ (t) of the reference signal generator 5 is set to out ₅ (t) = sin (ω ₀ t) ω ₀ = 2πf ₀ , the output out ₂ (t) of the phase shifter ₂ becomes the phase shift amount θ
Then, out ₂ (t) = sin (ω ₀ t + θ). The outputs of the multipliers 40 and 41 are also sine waves, and out ₄₀ (t) = sin (2ω ₀ t + ψ ₄₀ ) out ₄₁ (t) = sin (4ω ₀ t + ψ ₄₁ ). By changing the length of the delay line or the like, ψ ₄₀ , ψ ₄₁ = 2πi [deg] (i: integer) can be obtained. Therefore, out ₄₀ (t) = sin (2ω ₀ t) out ₄₁ (t) = sin (4ω ₀ t). The outputs out ₅ and out at this time
₄ and out ₄₁ are shown in FIG. Here, the time axis is normalized by ω ₀ t.

Next, the outputs y of the binary signal generators 42 to 44
Is defined as y = [0: (x <0), 1: (x ≧ 0)] when the input is x, and out ₅ , out ₄₀ , and out ₄₁ are respectively generated as binary signals. O when input to devices 42-44
out ₄₂ , out ₄₃ , and out ₄₄ define the domain of t in the interval [0,
2π radians], out ₄₂ = [1: (0 ≦ t ≦ π), 0: (π <t <2
π)] out ₄₃ = [1: (0 ≦ t ≦ (1/2) π) (π ≦ t ≦
(3/2) π), 0: ((1/2) π <t <π) ((3
/ 2) π <t <2π)] out ₄₄ = [1: (0 ≦ t ≦ (１ ／) π)) ((1 /
2) π ≦ t ≦ (3/4) π) (π ≦ t ≦ (5/4) π)
((3/2) π ≦ t ≦ (7/4) π), 0: ((1 /
4) π <t <(1/2) π) ((3/4) π <t <π)
((5/4) π <t <(3/2) π) ((7/4) π <
t <2π)]. This relationship is shown in FIG. FIG. 6 shows the trigger generator 3
0 indicates the trigger timing. Here, the trigger for latching is output when the phase of the input sine wave is “0” (time when the sine wave changes from negative to positive).

Now, the amount of phase shift by analog input is -1.
[Rad], the trigger signal for latching is output at ω ₀ t = 1. At this time, the outputs out ₄₂ , out ₄₃ , and out ₄₄ shown in FIG. 5 indicate “1”, “1”, and “0”, respectively, which are held as digital values. Similarly, the phase shift amount is
If it is 2, -3, -4, -5, -6 [rad], the output digital values are as shown in Table 1.

[0033]

[Table 1] In the embodiment of the present invention, the analog input value of the phase shifter 2 has been described as the phase shift amount θ, but the phase shifter 2 may have various other analog input values. That is, if the amplitude of a sine wave is generally ignored, V = sin (ω ₀ t−kz + θ) (where k is the wave number and z is the path length). Of these, ω
_Since 0t is the scale of the analog / digital converter, it is not considered as an analog input value. Next, considering that k changes, k is generally k = 2π / λ. Therefore, when λ changes (when the permittivity of the substrate through which the electromagnetic wave passes changes), the change can be represented by a digital value. Alternatively, the case where z is changed is similarly considered.

The measurement reference value of the phase scaler 4 can be determined other than that shown in FIG. FIG. 7 is a diagram showing another example of input signals of the binary signal generators 42 to 44. In the embodiment of the present invention, the phase scaler 4 outputs out ₅ = + 0 out at t = + 0 as shown in FIG. _The phase was adjusted so that ₄₀ = + 0 out ₄₁ = + 0, but as shown in FIG. 7, when the phase was adjusted so that out ₅ = + 1 out ₄₀ = + 1 out ₄₁ = + 1 at t = 0, as shown in FIG. , Ω ₀ t changes from “0” to “π radian” in a gray code as shown in Table 2 (ω ₀ t is not used from π radian to 2π radian).

[0035]

[Table 2] Further, in the embodiment of the present invention, it has been described that the reference signal generator 5 is multiplied to generate a doubled wave and a quadrupled wave. FIG. 8 is a block diagram of another embodiment of the present invention. As shown in FIG. 8, the high frequency generated by the high frequency
The frequency may be divided by the frequency dividers 48 and 49 to generate a sine wave to be input to the phase shifter 2.

FIG. 9 is a block diagram of the Johnson counter, and FIG. 10 is a diagram showing an output from the binary signal generator of the Johnson counter. As shown in FIG. When a Johnson counter is used, the state of 8 can be represented by 4 bits as shown in FIG. 10 only by the delay by the delay circuits 10 to 12. In this way, even if the number of bits increases, it is not necessary to use an ultra-high frequency for the LSB. However, in this case, 2 ^n-1 bits are 2
^Since it represents the state of ⁿ , code conversion as shown in Table 3 is required.

[0037]

[Table 3] Further, the reference signal generator 5 only needs to be accurate in phase, not necessarily a sine wave, but may be a triangular wave or a rectangular wave. Further, the trigger may be any number of times. That is, in addition to the zero-crossing point as shown in FIG. 6, for example omega ₀ t
= "0" when triggering at zero crossing point around 4,
"1" and "0" are obtained. At this time, if only the MSB is inverted, the same "1", "1",
“0” is obtained. Therefore, "1", "1", and "0" can be obtained even at two zero cross points during one cycle, and the conversion rate can be doubled.

[0038]

As described above, according to the present invention,
The hardware can be simplified, and an analog-to-digital converter that is not affected by hardware characteristic fluctuations can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of the apparatus according to the embodiment of the present invention.

FIG. 3 is a diagram showing a specific example of a phase shifter.

FIG. 4 is a diagram showing an input signal of a binary signal generator.

FIG. 5 is a diagram showing an output signal of a binary signal generator.

FIG. 6 is a diagram showing trigger timing of a trigger generator.

FIG. 7 is a diagram showing another example of an input signal of the binary signal generator.

FIG. 8 is a block diagram of another apparatus according to the embodiment of the present invention.

FIG. 9 is a block diagram of a Johnson counter.

FIG. 10 is a diagram showing an output from a binary signal generator of a Johnson counter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Phase shifter 3 Phase shift amount detector 4 Phase scaler 5 Reference signal generator 6 Output terminal 10-12 Delay circuit 30 Trigger generator 40, 41 Multiplier 42-44 Binary signal generator 45-47 2 Value signal holder 48, 49 Frequency divider 50 High frequency generator

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (6)

(57) [Claims] 1. A reference signal generator (5) for generating a reference signal having a constant period, and a phase shifter (2) for displacing the phase of the reference signal according to the intensity of an input analog signal (1).
A phase scaler (4) for generating a binary signal indicating two or more different states in synchronization with the reference signal, and a value of the binary signal for each specific phase of the output of the phase shifter (2). An analog-to-digital converter comprising a phase shift detector (3) for transmitting. Wherein said phase scaler are each 2 ⁰ times the frequency in synchronization with the reference signal, 2 x ^1, ......, 2 ^n-1
2. The analog-to-digital converter according to claim 1, further comprising means for generating n binary signals that differ by a factor of two. 3. The phase shift amount detector (3) includes: a trigger generator (30) for generating a trigger signal for each specific phase of the output of the phase shifter (2); and the phase scaler based on the trigger signal. 3. An analog-to-digital converter according to claim 1, further comprising an n-bit latch circuit for latching the output binary signal. 4. The analog-to-digital converter according to claim 1, wherein the phase scaler includes a multiplier for multiplying the reference signal by n-1 times in units of two. 5. The phase scaler (4) converts a signal having a frequency of 2 ⁿ⁻¹ times the reference signal into n−1 by half.
3. The analog-to-digital converter according to claim 1, further comprising a frequency divider for frequency division. 6. The analog-to-digital converter according to claim 1, wherein said phase scaler (4) includes a 2 ^{n -1} stage Johnson counter.
Digital converter.