RU2613843C1 - Method for converting analog signal to digital quadrature code and device for its implementation - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: method for conversting the analog signal at the intermediate frequency (IF) down to the digital quadrature code, is characterized in that the sampling frequency is set equal to the quadruple signal frequency after dividing the original frequency by the stroboscopic coefficient. The device, implementing the method, includes an analog-to-digital converter (ADC), a digital oscillator with digital control (DODC), two multipliers (MUL), a cycle delay line (CDL), two adders (ADD) and a subtractor (SUB).

EFFECT: reducing the sampling frequency against the processed signal frequency at the IF by the stroboscopic effect, increasing the identity of the quadrature components by the linear approximation of the discrete sampling amplitudes.

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Description

The group of inventions relates to radar and can be used as a digital receiver for converting an analog signal at an intermediate frequency (IF) with decreasing into a digital quadrature code.

A known method and device conversion (Handbook of radar. / Under the editorship of MI Skolnik. Transl. From English. Under the general editorship of BC Willow. In 2 books. Book 2. Moscow: Technosphere, 2014. - 680 p., ISBN 978-5-94836-381-3 [method, Fig. 25.8 and device, Fig. 25.9]). The method consists in analogue signal transfer to zero frequency with its decomposition into quadrature components, low-frequency filtering of the spectrum of quadrature components with their subsequent conversion to digital code.

A device for implementing this method contains two multipliers, a local oscillator that generates reference signals shifted in phase by π / 2, two low-pass filters and two analog-to-digital converters (ADCs).

The disadvantages of this device are the mismatch of the amplification coefficients in the quadrature channels and the phase deviation between them from π / 2 due to hardware errors and external factors.

Also known device "Coherent radar receiver with a digital device for amplitude and phase correction of the quadrature components of the receiving signal", RF patent No. 2273860, 04/10/2006, bull. No. 10, and "Fast calibration of the in-phase-quadrature imbalance", RF patent No. 2407199, 12/20/2010, bull. No. 35. All of them do not fully solve the tasks assigned to them, because Alignment between channels of amplification factors and phase shift is also carried out with a hardware error. In addition, when processing broadband signals, the phase shift and gain are generally not constant in the signal band, which also limits the possibilities for using these devices. At the same time, the volume of equipment increases, power consumption and reliability decreases.

There is also a known method and device of conversion, selected as a prototype (Reference for radar. / Ed. By M. I. Skolnik. Transl. From English. Under the general ed. BC. Willow. In 2 books. Book 2. Moscow: Technosphere, 2014 . - 680 p., ISBN 978-5-94836-381-3 [method, Fig. 25.10 and device, Fig. 25.11]). The method consists in converting a signal at an intermediate frequency (IF) F ₀ into a digital code, transferring it to a zero frequency with its decomposition into quadrature components, and their subsequent low-pass filtering in each channel.

A device for implementing this method contains an ADC, two digital multipliers, a digital local oscillator that generates reference signals with an ADC clock frequency shifted in phase by π / 2, as well as two digital low-pass filters and two decimators.

The disadvantages of this method and device are the high sampling rate, a large number of arithmetic operations and high power consumption.

The technical result of the group of inventions is: a reduced sampling frequency relative to the frequency of the processed signal on the IF due to the stroboscopic effect, a reduced number of arithmetic operations due to simplification of the decomposition into quadrature components and filtering, high identity of the quadrature components due to the linear approximation of the amplitudes of the discrete samples, as well as reduced Energy consumption.

The specified technical result is achieved by the fact that in the method of converting an analog signal to an inverter F ₀ down to a digital quadrature code according to the invention, discrete samples with a frequency ƒ _t are read from a signal on an inverter F ₀ and divided into quadrature components, while the sampling frequency is set to be quadrupled frequency ƒ ₀ , which corresponds to the ratio of the carrier frequency F _{0 of the} input IF signal to the stroboscopic coefficient equal to (4⋅N-3), where N is the number of stroboscopic intervals, while the frequency ƒ _{0 is} located it is married in the first interval, and F ₀ in the Nth frequency interval.

At a given sampling frequency, the decomposition of discrete samples into quadrature components is simplified, the amplitude of the reference signal at this sampling frequency takes integer values: 1, 0, and -1, and in order to form amplitude samples in the in-phase channel, a cyclically repeating sequence arrives at the reference input of the multiplier: 1, 0, -1, and 0, and to form discrete amplitude samples in a quadrature channel, a cyclically repeating sequence arrives at the same time: 0, -1, 0, and 1.

Also, filtering of low-frequency components with decimation in each quadrature is simplified, the essence of which is to eliminate zero samples, and the difference between the amplitude samples in the quadrature channels and the true values due to different read times is compensated by a linear approximation.

In the device for implementing the method, the indicated technical result is achieved in that in the device for converting the analog signal to the inverter F ₀ with decreasing into a digital quadrature code containing an analog-to-digital converter (ADC) and two multipliers (UMN), the information inputs of the first and second multipliers are connected to the ADC output, digitally controlled digital local oscillator (DSC), the outputs of which are connected to the corresponding reference inputs of the UMN, the clock inputs of the DSC and ADC are combined and the clock frequency is applied to them, and the information the ADC’s ion input receives a signal at the inverter, according to the invention, a subtractor (CUT), a delay line per clock (LZT) and two adders (SUM) are introduced, while the LZT output is connected to the first input of the first SUM, and the second input of the first SUM and the LZT input are connected with the output of the first UMN, the output of the second UMN is connected to the first input of the second adder and subtracting the VCH input, and the output of the first SUM is connected to the second input of the second SUM and the subtracting VCH input, while the outputs of the second SUM and VCH are the device outputs.

According to the claimed method of converting a signal to an IF, the number N of stroboscopic intervals is selected from the condition under which the band of the processed signal is at least twice as narrow as each interval. In accordance with the selected number of intervals, the clock frequency ƒ _t = 4F ₀ / (4⋅N-3) is set, which is fed to the clock inputs of the ADC and the central oscillator. A real analog signal of the form cos (2π⋅F ₀ ⋅ƒ _t + ϕ) is input to the ADC, and samples X _n = cos (π⋅n / 2 + ϕ) are sequentially read from its output. Two reference signals are formed at the output of the central oscillation center, shifted relative to each other by π / 2, which, in view of the given relation ƒ _t / ƒ ₀ = 4, take the values: 1, 0, -1, 0, 1, 0, etc. Therefore, the multiplication operations when separating the quadrature components are simplified and perform the functions of keys that pass the signal to the output without changing, block it or invert the sign, and if the signal is skipped to the output in one channel, it is blocked in the other, and vice versa. Thus, an array of even samples (-1) ⁿ ⋅X _2n is read from the output of the first multiplier-key, and an array of odd samples (-1) ^{n + 1} ⋅X _{2n + 1} is read from the output of the second multiplier-key, with zero samples defined by the reference signal are excluded. Such an exclusion of zero samples is equivalent to decimation; therefore, the clock frequency at the outputs of the key multipliers is halved. The deviation from the orthogonality of the quadrature components due to not simultaneous but sequential reading of the discrete samples (-1) ⁿ ⋅X _2n and (-1) ^{n + 1} ⋅X _{2n + 1 is} compensated by linear extrapolation in accordance with the system of equalities

The group of inventions characterized by the above essential features as of the filing date of the application is not known in the Russian Federation and abroad and meets the requirements of the “novelty” criterion.

The applicant has not identified technical solutions having features that match the sets of distinctive features of the claimed inventions, ensuring the achievement of the claimed technical result, and therefore it can be concluded that the inventions comply with the patentability condition "inventive step".

The inventions can be implemented industrially using well-known technical means, technologies and materials and meet the requirements of the patentability conditions "industrial applicability".

The invention is illustrated by graphic materials, where in FIG. 1 shows the frequency axis with the indicated values of the clock frequency, the original signal, as well as signals in each stroboscopic interval; in FIG. 2 shows a temporary waveform with rare samples from it; in FIG. 3 shows the waveforms of the quadrature components of the signal at the output of the multipliers; in FIG. 4 shows the oscillograms of the quadrature components of the signal after a linear approximation of their amplitudes; in FIG. 5 shows a quadrature signal in the phase plane before orthogonalization of the components; in FIG. 6 shows a quadrature signal in the phase plane after orthogonalization of the components; in FIG. 7 shows the dependence of the interference suppression coefficient on Doppler phases before orthogonalization and after; in FIG. 8 is a block diagram of an apparatus for converting an analog signal to a digital quadrature code.

In a method for converting an analog signal to a digital code according to the invention:

- the clock frequency ƒ _t is selected, the value of which determines the duration of the stroboscopic interval, while in the first interval the real frequency is four times less than the clock frequency (in Fig. 1, the spectrum of the actual signal in each interval is highlighted by a solid line, and the complex spectrum resulting from sampling with the clock frequency , marked with a dashed line). As a result of a rare reading of samples from a signal with a carrier frequency F _0, their values coincide with the samples if they were read from a signal with a carrier frequency ƒ ₀ (in Fig. 2, two sinusoids with a frequency of ƒ ₀ and F _0, respectively, and vertical lines with a frequency ƒ _t are located at the points where the amplitudes of these sinusoids coincide);

- the array of these samples is sequentially sorted by parity, and the signs of the samples are inverted in turn, and each selected array corresponds to the values of the quadrature components (in Fig. 3 - oscillograms of the selected quadrature components of the LFM signal, and in Fig. 5 these values are presented in the phase plane, deviation which from the circle indicates a violation of orthogonality);

- then, in one of the arrays, the amplitudes of neighboring samples are averaged, because discrete samples of quadrature values were read sequentially at different times, then the average value corresponds to the amplitude if the samples were read simultaneously in in-phase and quadrature channels. After that, symmetric addition and subtraction of the quadrature components is performed, which is equivalent to the total rotation of the signal phase by π / 4, which does not affect the further processing result, but equalizes the transmission coefficients between the quadrature channels (Fig. 4 shows the oscillograms of the quadrature components of the LFM signal after linear approximation amplitudes of discrete samples, and in Fig. 6, these same values are presented in the phase plane, which are located around the circumference, which indicates a high quality of orthogonality).

A device for converting an analog signal to a digital quadrature code, the block diagram of which is shown in Fig. 8, contains an analog-to-digital converter (ADC) 1 and two multipliers (UMN) 3 and 4, the information inputs of the first and second multipliers 3 and 4 are connected to the ADC digitally controlled digital local oscillator (DSC) 2, the outputs of which are connected to the corresponding reference inputs of UMN 3 and 4, the clock inputs of the DSC 2 and ADC 1 are combined and the clock frequency is supplied to them, and the signal from the inverter is fed to the information input of the ADC 1.

According to the invention, a subtractor (CUT) 8, a delay line per clock (LZT) 5 and two adders (SUM) 6 and 7 are introduced into the device, while the output of the LZT 5 is connected to the first input of the first SUM 6, and the second input of the first SUM 6 and the input LZT 5 is connected to the output of the first UMN 4, the output of the second UMN 3 is connected to the first input of the second SUM 7 and the subtracting input VCH 8, and the output of the first SUM 6 is connected to the second input of the second SUM 7 and the subtracted input VCH 8, while the outputs of the second SUM 7 and VCH 8 are the outputs of the device.

The method of converting an analog signal to a digital quadrature code is implemented by the proposed device as follows.

A real signal at the inverter is fed to the ADC information input, and a clock frequency arrives at the clock inputs of the ATsA and TsGCU, the value of which is much lower than the frequency of the input signal, but which satisfies the requirement ƒ _t = 4⋅F ₀ / (4⋅N-3). In FIG. 2, the frequency of the sine wave of the input signal for this example is F ₀ = 39 MHz, and the clock frequency is ƒ _t = 12 MHz, from which the amplitude samples from the input signal are read, in FIG. 2 they are presented in the form of vertical lines. The sequence of discrete samples X _n from the ADC output is simultaneously fed to two key multipliers with UMN memory. Two sequences are formed in the DCHC device for synchronously discrete samples, which, by virtue of the condition ƒ _t = 4⋅ƒ ₀ , where ƒ ₀ is the frequency of the material signal in the first stroboscopic interval, in FIG. 2 is shown by a dashed line, integer values are cyclically taken: 1, 0, -1, and 0. From the outputs of the central digital clock center these cyclically repeating sequences shifted relative to each other by a clock go to the control inputs of two key multipliers with UMN memory at the same time: 1, 0, -1 and 0, and on the second: 0, -1, 0 and 1. At the same time, an even sequence of discrete samples (-1) ⁿ ⋅X _2n is formed at the output of the first UMN, and an odd sequence is generated at the output of the second ( -1) ^{n + 1} ⋅X _{2n + 1} . Moreover, at the moment of formation of even samples in the first UMN, the second one does not respond to zero values along the way and retains the previous value at its output - an odd discrete sample, the same actions are performed when forming odd discrete samples. Thus, separation is made into in-phase and quadrature components with simultaneous decimation - decimation.

From the output of the first UMN, even samples arrive at the input of the LZT and at the second input of the first SMS, and from the output of the LZT, the samples delayed to the clock cycle arrive at the first input of the first SMS. From the output of the second UMN, the odd samples go to the first input of the second SUM and subtracting the VCH input, and from the output of the first SUM, after dropping the least significant bit, which is equivalent to dividing by two, the averaged even samples go to the second input of the second SUM and the subtracted input of CUT. Finally, these actions provide a high-quality separation of the signal into quadrature components.

All components of the device can be performed using a functionally complete element - an ADC that does not require ultra-high clock frequency, and digital circuits of any series, which are available in a large assortment, or one integrated circuit chip - FPGA.

Thus, the proposed method for converting an analog signal to a digital quadrature code and a device for its implementation allow:

- reduce the sampling frequency relative to the frequency of the processed signal on the IF due to the stroboscopic effect;

- reduce the number of arithmetic operations due to the simplification of the decomposition into quadrature components and filtering;

- increase the identity of the quadrature components due to the linear approximation of the amplitudes of the discrete samples;

- reduce power consumption.

Because the imbalance of the quadrature components arising in the process of their decomposition in the digital receiver due to hardware and algorithmic errors leads to the appearance of a mirror frequency channel, which significantly affects the quality of the suppression of reflected signals from passive interference, and the proposed method and device were checked taking into account the coefficient suppression by simulation.

The simulation of the operation of the device for converting an analog signal to a digital quadrature code was performed in a Mathcad environment with mandatory synthesis of the reflected signal with linear frequency modulation (LFM) at an intermediate frequency F ₀ = 39 MHz. Discretization was carried out at a reduced frequency ƒ _t = 12 MHz, which is four times higher than the frequency ƒ ₀ = 3 MHz (Fig. 2) of the signal in the first stroboscopic interval. The orthogonalization quality of the quadrature components in the device was checked by the method of simulating reflected signals in the entire range of Doppler phases from 0 to π, i.e. from stationary local objects to the first "blind" speed, processing them in the device under study, followed by compensation by the method of double interperiodic subtraction with "blowing".

The characteristics of the LFM signal were set typical of medium-range radar detection: the signal duration T = 10 μs, and the band Δƒ = 0.8 MHz.

The simulation results shown in FIG. 6, a quadrature LFM signal in the phase plane, confirm the high quality of the decomposition of the signal into quadrature components in the device. In FIG. Figure 7 shows the suppression results, where the values of the Doppler phase are plotted along the abscissa and the decibels are suppressed by the ordinate, using double cross-period subtraction with “blowing”. Moreover, the decomposition of the signal into quadrature components was performed using the proposed device, where the upper line is the result of suppressing the amplitudes of the quadrature components without approximation, and the signals were read from the outputs of the multipliers, and the bottom, taking into account the linear approximation, and the signals were read from the outputs of the second adder and subtractor.

Claims (4)

1. A method of converting an analog signal at an intermediate frequency (IF) F ₀ down to a digital quadrature code, characterized in that discrete samples with a frequency ƒ _t are read from the signal on an IF F ₀ and divided into quadrature components, while the sampling frequency is set equal to quadruple frequency ƒ _0, which corresponds to the ratio of the carrier frequency F ₀ of the input iF signal to the stroboscopic factor equal to (4⋅N-3) where N - number of strobe intervals, the frequency ƒ ₀ is located in the first interval, a F ₀ - N-th frequency interval. 2. The method according to p. 1, characterized in that at a given sampling frequency, the decomposition of discrete samples into quadrature components is simplified, the amplitude of the reference signal at this sampling frequency takes integer values: 1, 0 and -1, while for generating amplitude samples in common mode channel to the reference input of the multiplier receives a cyclically repeating sequence: 1, 0, -1 and 0, and for the formation of discrete amplitude samples in the quadrature channel at the same time comes cyclically repeating sequentially st: 0, -1, 0 and 1. 3. The method according to p. 2, characterized in that the difference between the amplitude samples in the quadrature channels from the true values due to different read times is compensated by a linear approximation. 4. A device for converting an analog signal to an inverter F ₀ down to a digital quadrature code containing an analog-to-digital converter (ADC) and two multipliers (UMN), the information inputs of the first and second multipliers are connected to the output of the ADC, a digital local oscillator with digital control ( TsGTsU), the outputs of which are connected to the corresponding reference inputs of the multipliers (UMN), the clock inputs of the TsTsU and ADC are combined and the clock frequency is fed to them, and the IF input receives a signal to the inverter, characterized in that a subtractor (CAL), a delay line per clock (LZT) and two adders (SUM), while the LZT output is connected to the first input of the first SUM, and the second input of the first SUM and the LZT input are connected to the output of the first UMN, the output of the second UMN is connected to the first the input of the second adder and the subtracting input VCH, and the output of the first SUM is connected to the second input of the second SUM and the subtracting input VCH, while the outputs of the second SUM and VCH are the outputs of the device.

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