JPH08148579A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To drastically improve integration by eliminating an unneeded part of a CMOS integrated circuit as much as possible. CONSTITUTION: The ground in a CMOS inverter in SOI structure is taken from a semiconductor substrate. SiO2 film 3 is formed on the surface of n-type semiconductor substrate (ground potential) where Al electrode 2 for grounding is formed on an inverse side and pMOS transistor and nMOS transistor are formed on the SiO2 film 3. A gate 4 consists of polysilicon and drain regions 6 and 9 and source regions 7 and 8 are formed by introducing impurity by self- alignment utilizing a side wall 5. The source region 9 of the nMOS transistor is commonly used by two nMOSs and is electrically connected to the substrate 1 by a conductor layer 10 for filling a through hole 15 and a diffusion layer 11 for connection, thus securing grounding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a highly integrated SR having a CMOS structure.
The present invention relates to a semiconductor device suitable for use in an AM, a gate array, etc., and a manufacturing method thereof.

[0002]

2. Description of the Related Art An example of a circuit having a CMOS structure is shown in FIG.
~ (C).

(A) is a common-mode buffer formed by connecting a CMOS inverter formed by MOS transistors M1 and M2 and a CMOS inverter formed by M3 and M4. Further, (b) shows an SRAM memory cell, and this memory cell has MOS transistors M5 and M6.
And a CMOS inverter composed of MOS transistors M7 and M8 are cross-coupled. Also, (c) is Bi-
An input buffer circuit used in an input stage such as an SRAM having a CMOS structure, and a CMOS level conversion circuit (enclosed by a thick dotted line in the drawing) is a MOS transistor M.
It is a buffer circuit using a current mirror composed of 9 to M12.

The basic device structure of such a circuit having a CMOS structure is the same, and FIG. 11 shows an example of a sectional structure of the device. For ease of understanding, an example of connection is shown in the figure, but this is connection when the flip-flop of the memory cell of FIG. 10B is formed.

The illustrated device is a CMOS adopting a so-called double well system, in which n wells 51 and 54 and p wells 52 and 53 are formed in a silicon semiconductor substrate 50, and p ⁺ diffusion is formed on the surface of the n well. Layers 57-59,
66 to 68 are provided, and n ⁺ diffusion layers 60 to 65 are provided on the surface of the p well. These diffusion layers are used as a source (S), a drain (D) and a layer for fixing the well potential (well contact layer). The gate 90 is made of polysilicon, and the field oxide film 56 formed by the LOCOS method is used for element isolation.
Reference numerals 70 to 81 are aluminum (Al) electrodes.

[0006]

The above-mentioned conventional structure of C
The MOS device has the following problems.

(1) Two wells, an n-well and a p-well, are used for element isolation (electrical isolation) and for optimizing the characteristics of each of nMOS and pMOS. Therefore, it is inevitable. To fix the well potential to the well contact layer (diffusion layers 57, 62, 6 in FIG. 11).
3, 68) and extraction electrodes (reference numerals 70 and 7 in FIG. 11).
5, 76, 81) is required, and it is difficult to further reduce the device size. (2) Due to the structure of the device using the well, the existence of the parasitic transistor cannot be avoided, and latch-up is likely to occur in the case of high integration. Therefore, there are many problems in the way of grounding (the ground of the nMOS source).

That is, the most common grounding method in a semiconductor device is to use the substrate as a ground. In this case, the instantaneous current flowing through the substrate causes noise to operate the parasitic transistor. It may lead to instability in the operation of the original CMOS circuit. For this reason, route the thick ground wire to the CMO
Careful design is required, such as connecting to the substrate at a safe place away from the S circuit, and surrounding the substrate portion with a diffusion layer for isolation to form an island. Therefore, the layout design becomes complicated, and a design margin is also required, which increases the layout area.

The same problem occurs not only in the case of grounding,
This also occurs when the power supply voltage is supplied to the pMOS source. That is, even when the substrate is set to the power supply potential and the power supply wiring is connected to the substrate, the same problem occurs.

(3) Further, the drain of the nMOS and the pM
Since the OS field drain is separated by a thick field oxide film formed by the LOCOS method, the occupied area of this part is dominant, and the silicide technology, particularly the salicide technology, is used as the connection technology between the electrode and the diffusion layer. Even if the element is miniaturized by using, the effect cannot be utilized and the degree of integration cannot be improved.

(4) For these reasons, the conventional CMO
In the S device, it was difficult to promote further miniaturization.

The present invention has been made by paying attention to such a problem, and an object thereof is to minimize an element isolation region and to not directly affect the operation of a device such as a contact or a wiring. Area as much as possible, CMO
It is to dramatically improve the degree of integration of the S integrated circuit.

[0013]

A semiconductor device according to the present invention which achieves the above object has a CMOS circuit such as a CMOS inverter having an SOI (Silicon On Insul) circuit.
The source region is grounded or the power supply voltage is supplied to the source region by electrically connecting the source region to a substrate having a desired potential through a through hole provided in the insulating layer. It is characterized by doing so.

Further, the semiconductor device of the present invention is characterized in that a through hole is provided below the source region and the source region and the substrate are connected at the shortest distance.

Also, in the semiconductor device of the present invention, the source regions of the transistors of the same conductivity type are made common, a through hole is provided under the common source region, and the common source region is made to be a through hole. It is characterized in that it is electrically connected to a substrate having a desired potential via the substrate.

The semiconductor device manufacturing method of the present invention is
Forming an insulating layer on the semiconductor substrate; forming a through hole in a part of the insulating layer; forming a silicon layer on the insulating layer and in the through hole; and forming a silicon layer on the silicon layer. A gate region is formed in a part, and impurities are selectively introduced into the silicon layer including the position of the through hole to form a source region and a conductive layer for connecting to the semiconductor substrate through the through hole. , A drain region is formed by selectively introducing an impurity into another region in the silicon layer, thereby forming an SOI (Silicon O
n Insulator) structure of the circuit having a CMOS structure, and a step of forming means for connecting the semiconductor substrate to a ground potential or a power supply potential.

[0017]

[Action]

(1) In the present invention, the CMOS circuit has an SOI structure and is formed on the insulating layer provided on the substrate.
Unlike an ordinary monolithic IC, an SOI structure element is not formed in a common semiconductor substrate, and each element is electrically separated by an underlying insulating layer. Therefore, it is not necessary to separate by a pn junction using a p-well or an n-well as in the conventional device. That is, since the well region and the well contact region are not needed, the element size can be reduced.

(2) Since no well is used, nM
A field oxide film is not required between the OS drain and the pMOS drain, and the device size can be reduced.

(3) Since the CMOS circuit is formed so as to be insulated from the semiconductor substrate, the potential of the semiconductor substrate can be set freely and there is no concern about latch-up. Taking advantage of this, the substrate is fixed to the ground potential or the power supply potential, a through hole (opening portion) is provided in a part of the insulating layer as necessary, and a conductor layer (wiring) is provided through the through hole. By connecting to the source region where the potential needs to be fixed, it is possible to easily pull out the ground or power.

(4) Further, a wiring for connecting the substrate and the source region is provided by providing a through hole under the source region (that is, by making the source region and the through hole two-dimensionally overlap each other). Ground wiring and power wiring are not required at all, and further compactification is possible.

(5) Further, by making the source regions of the MOS transistors of the same conductivity type common, the size can be further reduced.

(6) The semiconductor device of the present invention is SPE.
By combining a technique for growing a Si film on an insulating layer using a technique (Si solid-phase crystal growth technique) and a technique for forming a source and a drain by self-alignment of a silicon gate MOS transistor in a monolithic IC , Can be manufactured.

[0023]

Embodiments of the present invention will now be described with reference to the drawings.

(Embodiment 1) FIG. 9 is a sectional view showing the structure of a first embodiment of a semiconductor device according to the present invention. In the semiconductor device of this embodiment, the ground in the CMOS inverter having the SOI structure is obtained from the semiconductor substrate. The device structure is as follows.

A SiO ₂ film 3 is formed on the front surface of an n ^-- type semiconductor substrate (at ground potential) 1 having a ground Al electrode 2 formed on the back surface, and p is formed on the SiO ₂ film 3.
A MOS transistor and an nMOS transistor are formed. The gate 4 is made of polysilicon, and the drain regions 6 and 9 and the source regions 7 and 8 are formed by introducing impurities by self-alignment using the sidewalls 5, respectively.

The surfaces of the drain regions 6 and 9 and the source regions 7 and 8 are silicidized to form a silicide layer 12 in order to secure a good connection with the Al electrode 13. Further, the drains 7 and 8 are commonly used. Reference numeral 14 is a protective film (BPSG). The source region 9 of the nMOS transistor is electrically connected to the substrate 1 by the conductor layer 10 filling the through hole 15 and the connecting diffusion layer 11. The ground is secured by this. The through hole 15 is formed immediately below the source region 9. Therefore, the ground wiring routed in a plane is minimal, and in principle, it is completely unnecessary.

Further, the CMOS inverter has an SOI structure, so that a well is not required for element isolation,
It is also possible to directly connect the drain of the pMOS and the drain of the pMOS.

As described above, the device of this embodiment has no wasted area, and the scale-down effect using the silicide technique is actualized as it is, and an extremely high degree of integration can be obtained. Also, there is no concern about latch-up due to noise.

(Embodiment 2) FIG. 1 is a sectional view showing a structure of a second embodiment of a semiconductor device of the present invention in comparison with a conventional example. In this embodiment, two sets of CMOS circuits are made compact. This embodiment is shown on the upper side, and the conventional example shown in FIG. 11 is shown on the lower side. As is clear from the figure, the effect of scale-down according to this embodiment is remarkable.

The basic structure is the same as that of the first embodiment. The features of the present invention are that the sources of two nMOSs are shared (that is, the n ⁺ type source region 9 is a common source), and that the source regions 9 are shared. By connecting to the substrate 1 by the conductor layer 10 and the connecting diffusion layer 11, two nMOs are formed.
That is, the source of S is grounded at once.

By making the sources common, further scale down is possible. Further, since the through hole 15 is formed immediately below the source 9 as in the first embodiment, no extra ground wiring is required.

(Embodiment 3) FIG. 8 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention. In this embodiment,
The common source region 33 of the two pMOS transistors is connected to the p ⁻ substrate 29, thereby supplying the power supply voltage. The configuration is the same as that of the second embodiment shown in FIG.

(Embodiment 4) Next, an example of a method of manufacturing the semiconductor device (lateral MOSFET) of the present invention shown in FIG. 1 will be described with reference to FIGS.

First, the SiO ₂ film 3 is formed on the n-type Si single crystal substrate 1 by a process such as thermal oxidation (FIG. 2).

Next, a part of the SiO ₂ film 3 is removed by photolithography, RIE (reactive ion etching) or the like to form an opening 20 (FIG. 3). Then S
A Si film 21 is simultaneously grown on the SiO ₂ film 3 and the Si single crystal substrate 1 by PE (si solid phase crystal growth method) technology or the like (FIG. 4).

Next, a part of the crystal-grown Si film 21 is removed by photolithography and RIE or the like to perform element isolation, and then a gate oxide film 22 is formed by a process such as thermal oxidation. A polysilicon film to be a gate electrode is formed by a process such as CVD. This is processed by photolithography and RIE or the like to form the gate polysilicon electrode 4 (FIG. 5).

Next, formation of an insulating film by CVD and RIE
The sidewalls 5 are formed on both sides of the gate electrode 22 by processing by. Then, the side wall 5 is used as a positioning mask to perform ion implantation by self-alignment to form high-concentration impurity regions 6 and 7 to be source and drain regions. Then, by the salicide process, the surface of the gate electrode 22 and the source / source
The surfaces of the drain regions 6 and 7 are simultaneously silicidized to form a silicide layer 12 (FIG. 6).

Next, the Al electrode 1 is formed by a normal process.
3 and an interlayer insulating film (BPSG) 12 are formed to complete the device (FIG. 7).

The preferred embodiment of the present invention (that is,
However, the present invention is not limited to this, and various modifications can be made. For example, the present invention can be used in a gate array or SRAM having a Bi-CMOS structure. In this case, a CMOS circuit can be formed extremely compactly without being affected by a bipolar transistor having a high driving capability, and not only device miniaturization but also performance improvement can be achieved.

Further, not all the CMOSs have the SOI structure, but only the particularly required portion may have the SOI structure. In addition, by stacking CMOS ICs to which the present invention is applied by a semiconductor chip bonding technique or the like,
A high-density three-dimensional IC can be manufactured.

[0041]

As described above, the present invention is a CMOS
A CMOS structure circuit such as an inverter has an SOI structure,
The source region of the MOS transistor, which is connected to the ground or the power supply potential, is electrically connected to the substrate, and the following effects can be obtained.

(1) The well region and the well contact region as in the conventional device are not required, and the device size can be reduced.

(2) Since no well is used, nM
A field oxide film is not required between the OS drain and the pMOS drain, and the device size can be reduced.

(3) Since the CMOS circuit is formed so as to be insulated from the semiconductor substrate, the potential of the semiconductor substrate can be set freely and there is no concern about latch-up. Taking advantage of this, the substrate is fixed to the ground potential or the power supply potential, a through hole (opening portion) is provided in a part of the insulating layer as necessary, and a conductor layer (wiring) is provided through the through hole. By connecting to the source region where the potential needs to be fixed, it is possible to easily pull out the ground or power.

(4) Further, a through hole is provided below the source region (that is, the source region and the through hole are made to overlap each other in plan view), so that the wiring for connecting the substrate and the source region ( In principle, ground wiring and power wiring are completely unnecessary. Since there is no extra part, the result of microfabrication technology is revealed as it is,
Therefore, further downsizing is possible.

(5) Further, by making the source regions of the MOS transistors of the same conductivity type common and connecting the common source regions to the substrate, it is possible to make the device even more compact.

(6) The semiconductor device of the present invention is SPE
By combining a technique for growing a Si film on an insulating layer using a technique (Si solid-phase crystal growth technique) and a technique for forming a source and a drain by self-alignment of a silicon gate MOS transistor in a monolithic IC It can be manufactured.

(7) Due to these effects, it is possible to reduce the element isolation region and the regions such as contacts and wirings that do not directly affect the operation of the device as much as possible.
The degree of integration of the MOS integrated circuit can be dramatically improved.

[0049]

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a device structure of an embodiment of a semiconductor device of the present invention in comparison with a conventional example.

2 is a cross-sectional view showing a first step of a manufacturing process of the semiconductor device of FIG.

FIG. 3 is a cross-sectional view showing a second step of the manufacturing process of the semiconductor device of FIG.

FIG. 4 is a cross-sectional view showing a third step of the manufacturing process of the semiconductor device of FIG.

5 is a cross-sectional view showing a fourth step of the manufacturing process of the semiconductor device of FIG.

FIG. 6 is a cross-sectional view showing a fifth step of the manufacturing process of the semiconductor device of FIG.

7 is a cross-sectional view showing the final step of the manufacturing process of the semiconductor device in FIG.

FIG. 8 is a sectional view showing a device configuration of another embodiment of the semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing the device structure of another embodiment of the present invention.

10A to 10C are diagrams each showing an example of a circuit having a CMOS configuration.

FIG. 11 is a device sectional view showing a configuration of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Al electrode 3 Surface oxide film (SiO ₂ film) 4 Polysilicon gate 5 Sidewall 6,9 Source region 7,8 Drain region 10 Conductor layer 11 Connection diffusion layer 12 Silicide layer 13 Al electrode 14 Protective film 15 Through hole 21 Silicon film 22 Gate oxide film 30,33 Source region 31,32 Drain region

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/786 (72) Inventor Koichi Mitsushima Koji-cho, Aichi-gun, Aichi Prefecture No. 1 Toyota Central Research Institute Co., Ltd. (72) Inventor Susumu Sugiyama No. 41 Yokomichi Nagakute Town, Aichi-gun, Aichi Prefecture

Claims (4)

[Claims] 1. A circuit having a CMOS structure such as a CMOS inverter is provided with an SOI (Silicon On Insulator).
r) structure, and the source region is grounded or the power supply voltage is supplied to the source region by electrically connecting the source region to a substrate having a desired potential through a through hole provided in the insulating layer. A semiconductor device characterized in that 2. An SOI (Silicon On Insul) comprising an insulating layer formed on a semiconductor substrate, a silicon layer formed on the insulating layer, and source and drain regions provided in the silicon layer.
a circuit having a CMOS structure is constructed, a through hole is provided in the insulating layer located below the source region of the circuit having the CMOS structure, and the source region is provided with the through hole through the through hole. A semiconductor device, which is electrically connected to a semiconductor substrate, and the semiconductor substrate is connected to a ground potential or a power supply potential. 3. An SOI (Silicon On Insul) in which an insulating layer is formed on a semiconductor substrate, a silicon layer is further formed on the insulating layer, and source and drain regions are provided in the silicon layer.
A circuit having a CMOS structure is constructed, and the circuit having the CMOS structure is composed of a plurality of pMOS transistors and nMOS transistors.
The source regions of the transistors of the same conductivity type are shared, and a through hole is provided in the insulating layer located below the shared source region, and the shared source region is the through hole. A semiconductor device, wherein the semiconductor substrate is electrically connected to the semiconductor substrate via a semiconductor substrate, and the semiconductor substrate is connected to a ground potential or a power supply potential. 4. A step of forming an insulating layer on a semiconductor substrate, a step of forming a through hole in a part of the insulating layer, and a step of forming a silicon layer on the insulating layer and in the through hole. A gate region is formed in a part of the silicon layer, and an impurity is selectively introduced into the silicon layer including the position of the through hole to connect the source region and the through hole to the semiconductor substrate for connection. And a layer is formed, and an impurity is selectively introduced into another region in the silicon layer to form a drain region, whereby an SOI (Silicon On) is formed.
A method of manufacturing a semiconductor device, comprising: a step of forming a circuit having a CMOS structure having an Insulator structure; and a step of forming means for connecting the semiconductor substrate to a ground potential or a power supply potential.