JPH08147991A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To speed up the pre-charge operation of a common data line CD00 and a dummy bit line DB00 in a mask ROM and the like to speed up a current sense circuit of a sense amplifier. CONSTITUTION: In a mask ROM and the like providing a sense amplifier including a transfer gate T1 provided between a noninversion input node SAIT and an inversion input node SAIB of a differential amplifier circuit DSA1 and DSA2 as an equalizing means, a P channel MOSFET P5 and P6 having a comparatively large conductance are provided in parallel with a MOSFET P3, P4, P7 and P8 of a current sense circuit CS1 and CS2. These MOSFET are made to be in ON-state simultaneously with the transfer gate T1 and selectively. Thereby, pre-charge operation of a common data line CD00 and a dummy bit line DB00 is performed at a high speed without affecting to logic threshold levels of the current sense circuit CS1 and CS2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a mask ROM (read only memory) including a pair of current sense circuits and a differential amplifier circuit for receiving an output signal thereof, and speeding up and lowering voltage thereof. The technology is particularly effective for use in.

[0002]

2. Description of the Related Art For example, a MOSFET for selectively retaining storage data of logic "0" or "1" by selectively implanting impurities into its channel.
(Metal oxide semiconductor field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor.) A so-called NAND (NAND) provided with a memory array in which memory cells are arranged in series in a grid pattern. ) Type mask ROM. These mask ROMs include a current sense circuit that converts a read current output from a designated memory cell of a memory array to a bit line into a voltage signal, and a sense amplifier that receives an output signal of the current sense circuit.

[0003]

Prior to the present invention, the inventors of the present application have proposed a unit sense amplifier SAU as shown in FIG.
, And designed a mask ROM including such a sense amplifier. In the figure,
The unit sense amplifier SAU00 of the sense amplifier includes a pair of current sense circuits CS3 and CS4 and three differential amplifier circuits DSA1 to DSA3 coupled in two stages. Of these, the current sense circuit CS3 is connected to the power supply voltage VCC.
And P-channel MOSFETs P3 and P4 and an N-channel MOSFET N8 provided in series between the common data line CD00 and the common data line CD00. These MOSFETs
Is turned on selectively on condition that the internal control signal CEY20 is at low level and the N-channel MOSFET N6 is not turned on, and the common data line CD00
Is precharged to a predetermined level, and a minute read current obtained from a memory cell coupled to a designated bit line of the memory array via a common data line CD00 is applied to a voltage signal at a commonly coupled drain of MOSFETs P4 and N8. That is, it is converted into a non-inverted signal SAIT (here, a so-called non-inverted signal or the like which is selectively brought to a high level when it is set to an effective level is indicated by adding T to the end of the name. The same applies hereinafter). To do.

Similarly, the current sense circuit CS4 has P-channel MOSFETs P7 and P8 provided in series between the power supply voltage VCC and the dummy bit line DB00.
And N-channel MOSFET N9. These MOSFETs are selectively turned on under the condition that the internal control signal CEY20 is at a low level and the N-channel MOSFET NA is not turned on, precharge the dummy bit line DB00 to a predetermined level, and dummy from the memory array. A small reference read current obtained via the bit line DB00 is applied to the MOSFETP.
A voltage signal, that is, an inverted signal SAIB (where a so-called non-inverted signal, etc., which is selectively brought to a low level when it is brought to a valid level) is added to the end of the name of the voltage signal, that is, an inverted signal SAIB at the commonly coupled drains of 8 and N9. Attached and expressed.
The same applies below).

On the other hand, the differential amplifier circuits DSA1 and DSA2
Is a non-inverted signal output from the current sense circuits CS3 and CS4 when the output signal of the inverter V3 is at a high level, that is, the internal control signal DY2 and the predecode signal Y20 are both at a high level. The SAIT and the inverted signal SAIB are first amplified to a predetermined level. In addition, the differential amplifier circuit DSA3 also receives the high level of the output signal of the inverter V3 to be selectively operated, and the inverted signal SADB and the non-inverted signal SADT output from the differential amplifier circuits DSA1 and DSA2.
Expand the level difference of. The output signal SAO0 of the differential amplifier circuit DSA3 is taken into the output latch circuit OL including the clocked inverters CV1 and CV2 and the inverter V8 according to the internal control signal DY3, that is, the internal control signal LH1 and the inverted internal control signal LH1B, and then,
Output data bus DOB via bus driver BD1 that is selectively brought into a transmission state according to predecode signal Y20
Sent to 0.

By the way, the read current obtained through the common data line CD00 and the dummy bit line DB00 is set to an extremely small value, and the current sense circuits CS3 and CS3 are connected.
Since the MOSFETs P3, P4 and N8 and P7, P8 and N9 that compose S4 are designed to have a large resistance value, that is, a small conductance so that a voltage signal of a predetermined amplitude can be obtained based on the minute current as described above. ,
The precharge operation of the common data line CD00 and the dummy bit line DB00 by these MOSFETs is correspondingly delayed. To deal with this, the current sense circuit C
The S3 and CS4 are selectively turned on in response to the low level of the internal control signal CEY20, so that the P-channel MOSFETs PG and PH are turned on and the N-channel MOSFETs NN and NR are not turned on. Type precharge MOSFET NM
And NT are provided so that the common data line CD0
The precharge operation of 0 and the dummy bit line DB00 is accelerated.

However, the inventors of the present application have encountered the following problems in an attempt to reduce the operating power supply voltage of the mask ROM having the above sense amplifier. That is, the MOSFETs NM and NT additionally provided to the unit sense amplifier SAU00 of the mask ROM are MOSFETs.
Similar to TP3, P4 and N8 or P7, P8 and N9, the common data line C is provided during the read current sensing operation by the current sense circuits CS3 and CS4.
D00 or dummy bit line DB00. Then, one logic threshold circuit is configured with the corresponding MOSFET NN or NR, and the common data line CD0
Since it acts to determine the precharge level of 0 or the dummy bit line DB00, its conductance cannot be made too large in view of the relatively large resistance values of the common data line CD00 and the dummy bit line DB00. Therefore, from the time when the precharge time of the common data line and the dummy bit line, that is, the internal control signal CEY20 is set to the low level, until the level of the common data line CD00 and the dummy bit line DB00 reaches a predetermined level at which the sensing operation can be started. As shown in FIG. 8, the time te2 becomes longer as the operating power supply becomes lower in voltage, the sensing operation of the current sense circuits CS3 and CS4 becomes slower, and the shortening of the cycle time of the mask ROM is a constraint. As a result, the lowering of the voltage is restricted as a result.

An object of the present invention is to speed up the precharge operation of the common data line and the dummy bit line in the mask ROM and the like, and speed up the sense operation of the current sense circuit of the sense amplifier. Another object of the present invention is to accelerate the cycle time of a mask ROM or the like and promote a reduction in the operating power supply voltage.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a pair of current sense circuits each including a P-channel type first MOSFET which is provided between the power supply voltage of the circuit and its output node and has a relatively small conductance, and its non-inverting and inverting input nodes are Differential amplifier circuit which is respectively coupled to the output node of the current sense circuit and is selectively operated according to a predetermined internal control signal, and equalizing switch means provided between the non-inverting and inverting input nodes of the differential amplifier circuit. Mask ROM provided with sense amplifier including
Etc., the first MO forming the current sense circuit
P-channel type second and third MOSFETs having a relatively large conductance are provided in parallel with the SFET, and these MOSFETs are turned on simultaneously with the equalizing switch means and selectively.

[0011]

According to the above means, the precharge operation of the common data line and the dummy bit line can be speeded up and the time required for the precharge can be shortened without affecting the logic threshold level of the current sense circuit. ,
By speeding up the sense operation of the current sense circuit of the sense amplifier, speeding up the cycle time of mask ROM etc.,
It is possible to promote lowering of the operating power supply voltage.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a mask RO to which the present invention is applied.
FIG. 2 shows a block diagram of an example of an M (semiconductor memory device), and FIG. 2 shows a block diagram of an example of the memory array MARY and the peripheral portion included in the mask ROM of FIG. Further, FIG. 3 shows the memory array MAR of FIG.
A block diagram of an embodiment of the unit memory array MAU00 included in Y is shown, and in FIG. 4, the cell block group CBG0 included in the unit memory array MAU00 of FIG.
A circuit diagram of one embodiment is shown. Based on these figures, the outline of the configuration and operation of the mask ROM of this embodiment will be described first. The circuit elements forming each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. Further, the following description regarding the unit memory arrays will be given by taking the unit memory array MAU00 of FIG. 3 as an example, but other unit memory arrays MAU01 to MAU.
Since U03 to MAUF0 to MAUF3 have the same configuration as this, it should be analogized. In the following circuit diagrams, the MOSFET with an arrow attached to its channel (back gate) portion is a P-channel type MOSFET, and is shown separately from the N-channel MOSFET without an arrow. Further, the N-channel MOSFET in which the black-painted portion is provided in the channel portion is a so-called depletion type, which is shown separately from the enhancement-type MOSFET in which the black-painted portion is not provided.

In FIG. 1, the mask ROM of this embodiment
Has a memory array MARY, which occupies most of the surface of the semiconductor substrate, as its basic constituent element. In this embodiment, the mask ROM has a so-called x16 bit structure and is not limited in particular, and 16 data output terminals D are provided.
0 to DF (here, the tenth and subsequent serial numbers of the data output terminals and the like, which are provided in excess of nine, are indicated by the letters A to Z. The same applies hereinafter). In addition, as shown in FIG. 2, the memory array MARY is actually divided into four unit memory arrays MAU00 to MAU03 to MAUF0 to MAUF3, four corresponding to the data output terminals D0 to DF, respectively. The Y switches YS and the sense amplifiers SA corresponding to these unit memory arrays are provided in four units, four unit Y switches YSU00 to YSU03 to YSUF0 in total.
YSUF3 and unit sense amplifiers SAU00-SA
It is divided into U03 to SAUF0 to SAUF3.

Each of the unit memory arrays MAU00 to MAUF3 of the memory array MARY is not particularly limited, but as represented by the unit memory array MAU00 of FIG. 3, 128 cell blocks CB00 to CB03 to CB03 in the bit line direction. It is divided into CB310 to CB313, and each of these cell blocks is combined with four cells to form 32 cell block groups CB.
G0 to CBG31 are configured. For the cell block groups CBG0 to CBG31, 16-bit word line selection signals WG00 to WG from the left X address decoder XD.
G0F to WG310 to WG31F are respectively supplied, and a cell block selection signal BS of 8 bits in total is supplied.
00R ~ BS03R ~ BS310R ~ BS313R
And BS00L to BS03L to BS310L to
BS313L is supplied respectively. Of these, the word line selection signals WG00 to WG0F to WG310 to WG
31F indicates the corresponding four cell blocks CB00 to CB
03 to CB310 to CB313, respectively, and cell block selection signals BS00R to BS03R.
To BS310R to BS313R and BS00L
-BS03L to BS310L to BS313L correspond to the corresponding cell blocks CB00 to CB03 to CB31.
One bit is supplied to each of 0 to CB313.

The word line selection signals WG00 to WG0F to WG310 supplied from the X address decoder XD to the cell block groups CBG0 to CBG31.
~ WG31F is set to a high level like power supply voltage VCC when it is in a non-selected state, and is alternatively set to a low level like ground potential VSS when it is in a selected state. Also, cell block selection signals BS00R to BS03
R to BS310R to BS313R and BS00
L to BS03L to BS310L to BS313L are
When it is in the non-selected state, it is set to the low level of the ground potential VSS, and when it is in the selected state, the power supply voltage V is alternatively.
CC high level. In this embodiment, the mask ROM has its operating power source lowered and the power source voltage VC
C is a positive potential having a relatively small absolute value, such as + 3V.

Here, each of the cell block groups CBG0 to CBG31 of the unit memory array MAU00 is arranged parallel to the horizontal direction of the drawing as represented by the cell block group CBG0 of FIG.
Book word lines W000 to W00F to W030 to W0
3F, and 64 bit lines B000 to B0063 arranged in parallel in the vertical direction and one dummy bit line DB00. Between the bit line and the dummy bit line and the ground potential VSS (second power supply voltage), two enhancement type and depletion type select MOSFETs alternately arranged and an enhancement type or depletion type are selectively provided. Two unit cell blocks, each of which is formed by serially connecting 16 memory cells MC, are arranged on either side of each bit line or dummy bit line. As a result, the cell block groups CBG0 to CB
Each of G31 has a storage capacity of substantially 64 × 64 × 2 bits, that is, a so-called 8 kilobit. Further, the unit memory arrays MAU00 to MAUF
Each of the 3 has a storage capacity of 8 kilo × 32, that is, a so-called 256 kilo bit, and is a mask ROM.
Has a storage capacity of 256 kilo × 64, that is, a so-called 16 megabit. As described above, the unit memory arrays MAU00 to MAU03 to MAUF0 to
Since the MAU F3 corresponds to the data output terminals D0 to DF by fours, the mask ROM has a so-called 16 bit ×
It has a word structure of 1 megabit.

The gates of the two selection MOSFETs of each unit cell block forming the cell blocks CB00 to CB03 of the cell block group CBG0 have corresponding cell block selection signals BS00R to BS03R or BS0.
The word lines W000 to W00F to W030 to which the gates of the 128 memory cells MC in each row are commonly coupled to 0L to BS03L in a predetermined combination.
W03F is a word line selection signal WG0 corresponding to four lines.
0 to WG0F to WG30 to WG3F are commonly connected. Furthermore, the bit lines B000 to B0063 and the dummy bit line DB00 shared by the 32 cell block groups CBG0 to CBG31 of the unit memory array MAU00 and the dummy bit line DB00 consist of a predetermined number of series MOSFETs that are constantly turned on. Circuit BLC00
Is coupled to the ground potential VSS via the, and the level when stable is the ground potential VSS, that is, 0V.

In this embodiment, the memory array MAR
The memory cell forming each unit cell block of Y has a logic “0” according to the amount of impurities implanted into the channel.
Alternatively, it is composed of an N-channel MOSFET which selectively holds the stored data of "1". That is, the MOSFET with a small amount of impurities implanted into the channel becomes a so-called enhancement type memory cell, which holds the storage data of logic "0", and the MOSFET with a large amount of impurities implanted into the channel is a depletion type memory cell. Thus, the stored data of logic "1" is held. Needless to say, the depletion type memory cell is turned on even when the gate potential thereof is the ground potential VSS, that is, 0V, but the enhancement type memory cell is not turned on when the gate potential thereof is 0V.

From the above, the unit memory array MA
U00 cell blocks CB00 to CB03 to CB3
10 to CB313, corresponding cell block selection signals BS00R to BS03R to BS310R to BS31.
3R or BS00L to BS03L to BS310
By selectively setting L to BS313L to the high level, the two select MOSFETs and 16 memory cells of the unit cell block in which the bit lines B000 to B0063 and the dummy bit line DB00 are arranged on the right or left side thereof It is coupled to the ground potential VSS via MC. At this time, the 16 memory cells MC forming each unit cell block have corresponding word lines W000 to W00F to W030 to W03F, that is, a word line selection signal WG0.
When 0 to WG0F are set to the high level non-selection level, they are turned on regardless of the held data, but when the corresponding word line selection signal is set to the low level selection level, selection is performed according to the held data. And the read current is selectively passed through the corresponding bit lines B000 to B0063.

Returning to the explanation of FIG. The X address decoder XD is supplied with 13-bit internal address signals X0 to XC from the X address buffer XB. The X address buffer XB has address input terminals AX0 to AX.
The X address signals AX0 to AXC are supplied via C and the internal control signal C from the timing generation circuit TG.
E1 is supplied. The internal control signal CE1 is normally at a low level, and when the mask ROM receives the low level of the chip enable signal CEB and is brought into a selected state,
It is selectively set to a high level at a predetermined timing.

The X address buffer XB is a mask ROM
Address input terminals AX0 to A when
13-bit X address signal A supplied via XC
X0 to AXC are taken in according to the internal control signal CE1, and internal address signals X0 to XC are formed based on these X address signals and supplied to the X address decoder XD. Further, the X address decoder XD decodes the internal address signals X0 to XC to generate corresponding cell block selection signals BS00R to BS03R to BS310.
R to BS313R and BS00L to BS03L to BS310L to BS313L are alternatively set to the high level, and corresponding word line selection signals WG00 to W are selected.
G0F to WG310 to WG31F are alternatively set to low level. The internal address signals X0 to XC formed by the X address buffer XB are also supplied to the address transition detection circuit ATD.

Next, the bit lines B000 to B0063 to BF30 to BF363 and the dummy bit lines DB00 to DBF3 which form the unit memory arrays MAU00 to MUF3 of the memory array MARY and the dummy bit lines DB00 to DBF3 correspond to the unit Y switch YS corresponding to the lower part of the figure. Y
These units Y are connected to SU00 to YSUF3.
Common data line CD0 alternatively through a switch
0 to CDF3, that is, one input terminal of the corresponding unit sense amplifier SAU00 to SAUF3 of the sense amplifier SA. The unit of the Y switch YS includes Y switch YSU00 to YSUF3, and the Y address decoder YD outputs 64-bit bit line selection signals YS0 to YS.
63 is commonly supplied, and the Y address decoder YD is supplied with the 8-bit internal address signals Y0 to Y7 from the Y address buffer YB. The Y address buffer YB is supplied with the Y address signals AY0 to AY7 via the address input terminals AY0 to AY7, and the internal control signal CE is supplied from the timing generation circuit TG.
1 is supplied.

The Y address buffer YB is a mask ROM
Address input terminals AY0 to AY
8-bit Y address signal AY supplied via Y7
0 to AY7 are taken in according to the internal control signal CE1, and internal address signals Y0 to Y7 are formed based on these Y address signals and supplied to the Y address decoder YD. The Y address decoder YD decodes the 6-bit internal address signals Y2 to Y7 supplied from the Y address buffer YB, and selectively sets the corresponding bit line selection signals YS0 to YS63 to the high level. , The remaining 2-bit internal address signals Y0 to Y1 are decoded, and the corresponding predecode signals Y20 to Y23 are decoded.
Is alternatively set to the high level. The internal address signals Y0 to Y7 are also supplied to the address transition detection circuit ATD. Further, the bit line selection signals YS0 to YS63 are Y
Unit of switch YS Y switch YSU00 to YSU
The predecode signals Y20 to Y2 are commonly supplied to F3.
3 is a unit sense amplifier SAU00 of the sense amplifier SA
To SAUF3 are commonly supplied.

On the other hand, the unit Y switch YS of the Y switch YS
SU00 to YSUF3 are unit memory arrays MAU
00 to MAU F3 bit lines B000 to B0063
Through 64 provided corresponding to BF30 to BF363
Each includes a number of switch MOSFETs. One of these switch MOSFETs corresponds to the corresponding bit line B00 of the corresponding unit memory array MAU00 to MAUF3.
0 to B0063 to BF30 to BF363, respectively, and the other is commonly coupled to the corresponding common data lines CD00 to CDF3. Also, each switch MO
The corresponding bit line selection signal YS is applied to the gate of the SFET.
0 to YS63 are commonly supplied. As a result, the switch MOSFETs forming the unit Y switches YSU00 to YSUF3 are selectively turned on when the corresponding bit line selection signals YS0 to YS63 are set to the high level, and the unit memory array MAU0 is selected.
The corresponding bit lines of 0 to MAU F3 and the common data lines CD00 to CDF3 are selectively connected. Unit Y switches YSU00 to Y
SUF3 is the dummy bit lines DB00 to DBF3 of the corresponding unit memory arrays MAU00 to MAUF3.
Are directly connected to the other input terminals of the corresponding unit sense amplifiers SAU00 to SAUF3 of the sense amplifier SA.

The address transition detection circuit ATD is supplied with internal address signals X0 to XC from the X address buffer XB, internal address signals Y0 to Y7 from the Y address buffer YB, and internal control from the timing generation circuit TG. The signal CE1 is supplied. The internal control signal CE1 is selectively set to the high level in response to the low level change of the chip enable signal CEB as described above.

The address transition detection circuit ATD includes an internal control signal CE1, that is, a chip enable signal CEB and internal address signals X0 to XC, that is, X address signals AX0 to A.
XC and internal address signals Y0 to Y7, that is, Y address signals AY0 to AY7 are monitored for level changes, and when the logical level of any bit thereof is inverted, the output signal thereof, that is, address transition detection signal ATDS, is temporarily held for a predetermined period. To high level. Address transition detection signal ATDS output from address transition detection circuit ATD
Are supplied to the timing generation circuit TG.

The common data lines CD00 to CDF3 are
Unit sense amplifier SAU0 corresponding to sense amplifier SA
0 to one of the input terminals of SAUF3. Corresponding dummy bit lines DB00 to DBF3 are coupled to the other input terminals of these unit sense amplifiers, respectively. Unit of sense amplifier SA Sense amplifier SAU
00 to SAUF3 are commonly supplied with internal control signals CE1 and DY1 to DY3 from the timing generation circuit TG, and predecode signals Y20 to Y23.
Are unit sense amplifiers SAU00 to SAUF0 to SA
16 combinations of U03 to SAUF3 are commonly supplied.

Here, each of the unit sense amplifiers SAU00 to SAUF3 constituting the sense amplifier SA has a pair of current sense circuits CS1 as described later.
And CS2 and three current mirror type differential amplifier circuits DSA1 and DSA2 and DSA3 coupled in two stages.
And an output latch circuit OL for receiving the output signal of the differential amplifier circuit DSA3. Of these, the current sense circuit C
S1 and CS2 are selectively activated by setting the internal control signal CE1 to the high level and the corresponding predecode signals Y20 to Y23 to the high level, and corresponding common data lines CD00 to CDF3 and dummy bits. The lines DB00 to DBF3 are precharged to a predetermined level, and a minute read current output via these common data lines or dummy bit lines is converted into a predetermined voltage signal. In addition, the differential amplifier circuit DSA1
~ DSA3 is a voltage signal output from the current sense circuits CS1 and CS2 when the internal control signal DY2 is at a high level and the corresponding predecode signals Y20 to Y23 are at a high level. And the difference is amplified and transmitted to the output latch circuit OL. Further, the output latch circuit OL selectively receives and holds the output signal of the differential amplifier circuit DSA3 in response to the low level change of the internal control signal DY3, and at the same time, outputs the data output buffer O via the output data buses DOB0 to DOBF.
Output to B. The more specific structure and operation of the sense amplifier SA will be described later in detail.

The data output buffer OB includes 16 unit circuits provided corresponding to the data output terminals D0 to DF. These unit circuits include an output data bus DOB
4 unit sense amplifiers SAU00 to SAU03 to SA corresponding to the sense amplifier SA via 0 to DOBF
The output signals of UF0 to SAUF3 are predecode signals Y2
The signals are selectively transmitted according to 0 to Y23, and the internal control signal DY4 is commonly supplied from the timing generation circuit TG. The output terminal of each unit circuit of the data output buffer OB is coupled to the corresponding data output terminal D0 to DF.

Each unit circuit of the data output buffer OB is
When the internal control signal DY4 is set to a high level, it is selectively brought into a transmission state, and the corresponding unit sense amplifiers SAU00 to SAU03 to SAUF0 of the sense amplifier SA are set.
The read data selectively output from the SAUF3 is sent to the outside of the mask ROM via the data output terminals D0 to DF. When the internal control signal DY4 is at low level, the data output terminals D0 to DF are in a so-called high impedance state.

The timing generation circuit TG is provided with a chip enable signal CEB which is externally supplied as a start control signal.
Also, the above various internal control signals are selectively formed based on the output enable signal OEB and the address transition detection signal ATDS supplied from the address transition detection circuit ATD, and are supplied to each part of the mask ROM.

FIG. 5 shows a circuit diagram of an embodiment of the unit sense amplifier SAU00 included in the sense amplifier SA of the mask ROM of FIG. Further, FIG. 6 shows a signal waveform diagram of one example in the read mode of the unit sense amplifier SAU00 and related parts of FIG.
Based on these figures, the unit sense amplifiers SAU00 to SAU00 constituting the sense amplifier SA of the mask ROM of this embodiment are formed.
Specific configurations and operations of SAU03 to SAUFO to SAUF3 and their features will be described. The following description of the unit sense amplifiers SAU00 to SAUF3 will be made by taking the unit sense amplifier SAU00 of FIG. 5 as an example, but the other unit sense amplifiers SAU01 to SAU01 to
Since SAU03 to SAUFO to SAUF3 have the same configuration as this, it should be analogized. In addition, FIG.
In the burst mode, after the mask ROM is selected, the chip enable signal CEB is kept at the low level and the read operation for a plurality of addresses is continuously performed, and the predecode signals Y20 to Y20 are used.
23 is alternately and sequentially set to a high level every cycle in accordance with the change of the Y address signals AY0 to AY7.

In FIG. 5, each of the unit sense amplifiers SAU00 to SAUF3 forming the sense amplifier SA has a pair of current sense circuits CS1 (first current sense circuit) as represented by the unit sense amplifier SAU00 of FIG. Sense circuit) and CS2 (second current sense circuit), and three so-called current mirror type differential amplifier circuits DSA1 to DSA3. Of these, the input node of the current sense circuit CS1 is coupled to the corresponding common data line CD00,
The second input node is coupled to the dummy bit line DB00. As described above, the common data line CD00 is selectively connected to the bit lines B000 to B0063 of the corresponding unit memory array MAU00 of the memory array MARY through the unit Y switch YSU00 of the Y switch YS, and the dummy bit line DB00 is a unit memory array MAU00
Directly connected to the dummy bit line of.

The current sense circuit CS1 has a power supply voltage V
Two P-channel (first conductivity type) MOSFs provided between CC (first power supply voltage) and its output node
It includes ETP3 and P4 (first MOSFET) and an N-channel MOSFET N8 provided between its output node and its input node, that is, common data line CD00. Of these, MOSFETs P3 and P4 are constantly turned on because their gates are coupled to the ground potential VSS. Further, the gate of the MOSFET N8 is
Power supply voltage VCC via P-channel MOSFET P2
Coupled to two N-channel MOSFE
TN6 and N7 and another N-channel MOSF provided in parallel with these MOSFETs N6 and N7
Ground potential VSS (second power supply voltage) via ETN5
Is combined with The gates of MOSFETs N6 and N7 are
An internal control signal CEY20 is supplied to the input node of the current sense circuit CS1, that is, the common data line CD00, and the gates of the MOSFETs P2 and N5. The MOSFETs P3 and P4 are connected to the common data line CD0.
It is designed to have a relatively large resistance value, that is, a relatively small conductance, because it is necessary to convert a minute read current output via 0 into a voltage signal having a predetermined amplitude. In addition, the internal control signal CEY20 is
D) The output signal of the gate NA1 is fed to the inverters V1 and V2
, The internal control signal CE1 is set to the high level and the corresponding predecode signal Y20 is set to the high level, and is selectively set to the low level.

Similarly, the current sense circuit CS2 includes two P-channel MOSFETs P7 and P8 (first MO transistor) provided between the power supply voltage VCC and its output node.
SFET) and the output node and its input node, that is, the N-channel M provided between the dummy bit line DB00.
And OSFET N9. Of these, MOSFET P7
The gates of P8 and P8 are constantly turned on by coupling their gates to the ground potential VSS. In addition, MOSFE
The gate of TN9 is coupled to the power supply voltage VCC via a P-channel MOSFET P9, and also has two N-channel MOSFETs NA and NB and their MOSFs.
Another N channel M provided in parallel with ET
It is coupled to ground potential VSS via OSFET NC. The gates of the MOSFETs NA and NB are input nodes of the current sense circuit CS2, that is, the dummy bit line DB.
00, and the internal control signal CEY20 is supplied to the gates of the MOSFETs P9 and NC. MO
The SFETs P7 and P8 are designed to have a relatively large resistance value, that is, a relatively small conductance because it is necessary to convert a minute reference read current output via the dummy bit line DB00 into a voltage signal of a predetermined amplitude. .

In this embodiment, the current sense circuit CS1 further includes a P-channel MOSFET P5 (second MOSFET) provided between the power supply voltage VCC and its output node, that is, the commonly coupled drains of MOSFETs P4 and N8. Current sense circuit CS2
Is a power supply voltage VCC and its output node, that is, MOSFE
A P-channel MOSFET P6 (third MOSF) provided between the drains of TP8 and N9 commonly connected
ET) is included. Also, the current sense circuits CS1 and C
A transfer gate T1 which is a pair of P-channel and N-channel MOSFETs and serves as an equalizing switch means is provided between the output nodes of S2. Of these, the inverted internal control signal EQ1B is commonly supplied to the gates of the MOSFETs P5 and P6 and the P-channel MOSFET that constitutes the transfer gate T1, and the N-channel MOSF that constitutes the transfer gate T1.
An internal control signal EQ1 is supplied to the gate of ET.
The MOSFETs P5 and P6 are, as will be described later,
The current sense circuits CS1 and CS are temporarily turned on during the equalization period of the unit sense amplifier SAU00.
Since there is no risk of affecting the logic threshold level of 2, the common data line CD00 and the dummy bit line D
It is designed to have a relatively large conductance so that the precharge operation of B00 can be performed as fast as possible.

Here, the internal control signal CE1 is selectively set to the high level in response to the low level of the chip enable signal CEB. Further, as shown in FIG. 6, the predecode signal Y20 is a 2-bit Y address signal AY0.
And AY1 are set to a corresponding combination, that is, both are set to a high level to be selectively set to a high level, and the internal control signal CEY20 is selectively set to a low level in response to the high levels of the internal control signal CE1 and the predecode signal Y20. To be done. On the other hand, the internal control signal EQ1 and the inverted internal control signal EQ1B are selectively set to a high level or a low level when the internal control signal DY1 (second internal control signal) is set to an effective level, that is, a low level. As is apparent from FIG. 6, DY1 is the X address signals AX0 to AXC and the Y address signal AY.
0 to AY7 are changed from address ADA to address ADB, and output signal ATDS of address transition detection circuit ATD
After being set to the high level, it is set to the low level for a predetermined period.

The current sense circuits CS1 and CS2 of the unit sense amplifier SAU00 are set when the internal control signal CEY20 is set to the high level by setting the mask ROM in the non-selected state or selecting the predecode signal Y20 while keeping the predecode signal Y20 at the low level. Then, the MOSFETs N5 and NC are turned on, the MOSFETs P2 and P9 are turned off, and the MOSFETs N8 and N9 are both turned off. In addition, P-channel MO forming MOSFETs P5 and P6 and transfer gate T1
The SFET is turned off in response to the high level of the inverted internal control signal EQ1B, and the N-channel MOSFET forming the transfer gate T1 is also turned off in response to the low level of the internal control signal EQ1. As a result, the current sense circuits CS1 and CS2 are both rendered inactive, and the common data line CD00 and the dummy bit line DB0
It has no effect on 0. At this time, the Y address signals AY2 to AY7 of the unit memory array MAU00 are provided to the common data line CD00 and the dummy bit line DB00.
The bit line and the dummy bit line designated by are connected selectively, but as described above, the unit memory array MA
The bit line and the dummy bit line forming U00 are connected to the ground potential V via the corresponding bit line leak circuit BLC00.
Since it is coupled to SS, the initial level VD1 of the common data line CD00 and the dummy bit line DB00 is the ground potential VS.
S, that is, 0V.

On the other hand, the mask ROM outputs the predecode signal Y.
When the internal control signal CEY20 is set to the low level by bringing 20 into the selected state while keeping the high level, the MOSFETs N5 and NC are turned off and the MOSFETs P2 and P9 are turned on in the current sense circuits CS1 and CS2. The MOSFETs N8 and N9 are turned on. Further, a P-channel MOSFET which receives the low level of the inverted internal control signal EQ1B and constitutes the MOSFETs P5 and P6 and the transfer gate T1.
Is turned on, and the N-channel MOSFET forming the transfer gate T1 is turned on in response to the high level of the internal control signal EQ1. As a result, the common data line CD00 becomes the MOSFET of the current sense circuit CS1.
It is precharged via TP2, P3, P4 and N8 and P5, the dummy bit line DB00 is precharged via MOSFETs P7, P8 and N9 and P6 of the current sense circuit CS2, and the outputs of the current sense circuits CS1 and CS2. The nodes, that is, the non-inverting and inverting input nodes of the differential amplifier circuits DSA1 and DSA2 are equalized to the same potential, that is, the power supply voltage VCC via the MOSFETs P5 and P6 and the transfer gate T1.

As described above, the MOSFETs P5 and P6 provided in the current sense circuits CS1 and CS2 of this embodiment are selectively turned on when the internal control signal DY1, that is, the inverted internal control signal EQ1B is set to the low level, and are in common. Data line CD00 or dummy bit line DB
00 acts as a precharge means for raising the voltage to a predetermined potential, and the output nodes of the current sense circuits CS1 and CS2, that is, the differential amplifier circuits DSA1 and DSA1 and D2.
It also acts as an equalizing means for keeping the non-inverting and inverting input nodes of SA2 at the same potential. Further, the internal control signal DY1 is temporarily set to the low level immediately before the internal control signal DY2 described later is set to the high level and the differential amplifier circuits DSA1 to DSA3 are set to the operating state, and the MOS
Since the FETs P5 and P6 are turned on, the basic functions of the current sense circuits CS1 and CS2, that is, the current-voltage conversion operation and the logic threshold level thereof are not affected. Therefore, in this embodiment, the MOSFET
The conductance of P5 and P6 is made as large as possible to speed up the precharge operation of the common data line CD00 and the dummy bit line DB00, and the current sense circuit CS
Since the sense operation of 1 and CS2 can be speeded up, the cycle time of the mask ROM can be speeded up, and the lowering of the operating power supply voltage can be promoted.

When the equalizing period ends, the internal control signal DY
1, that is, when the inverted internal control signal EQ1B is returned to the high level, the current sense circuits CS1 and CS2 receive M
OSFETs P5 and P6 and transfer gate T
1 is turned off, but the internal control signal CEY20 is kept at the low level, so that the MOSFETs P2, P3, and
The precharging operation of the common data line CD00 and the dummy bit line DB00 by P4 and N8 and MOSFETs P7, P8, P9 and N9 is continuously performed. Then, the common data line CD00 and the dummy bit line DB00
Has a predetermined potential VP1, that is, the current sense circuit C
When the logic thresholds of S1 and CS2 are reached, MO
SFETs N6 and N7 and NA and NB are turned on and MOSFETs P2, P3 and N8 and MO
The precharge operation by the SFETs P7, P8 and N9 is also stopped. Therefore, this time, the level of the common data line CD00 starts to gradually decrease at a speed according to the data held in the selected memory cell of the unit memory array MAU00, and the level of the dummy bit line DB changes to the unit memory array MAU0.
It begins to gradually decrease at a speed corresponding to the conductance of the dummy cell of 0.

Here, the level of the dummy bit line DB00 is set to the unit memory array M as shown by the dotted line in FIG.
The speed at which the level of the common data line CD00 drops relatively slowly because the selected memory cell of AU00 holds the data of logic "0", and the unit memory array MAU0
Since the selected memory cell of 0 holds the data of logic "1", the level of the common data line CD00 drops at a speed almost intermediate between the level at which the level of the common data line CD00 drops relatively fast. Therefore, the level of the dummy bit line DB00 can be a reference level for determining whether the data held in the selected memory cell of the unit memory array MAU00 is logical "0" or "1".

Next, the differential amplifier circuit DSA1 of the unit sense amplifier SAU00 includes a pair of N-channel type differential MO.
Includes SFETND and NE. These differential MOSFE
The drain of T is a P-channel load MOSFET P
It is coupled to the power supply voltage VCC via A and PB, and its commonly coupled source is an N-channel MOSFET NF.
Is coupled to the ground potential VSS via. Load MOSFE
TPA and PB are current mirror coupled and act as a so-called active load. In addition, MOSFETN
F is an inverter V3 for the output signal of the NAND gate NA2
When the inversion signal by (1), that is, the internal control signal SA1 (first internal control signal) is set to the high level, it is selectively turned on and acts as a drive MOSFET. further,
The output signal of the current sense circuit CS1, that is, the non-inverted internal signal SAIT is supplied to the gate of the differential MOSFET ND, and the output signal of the current sense circuit CS2, that is, the inverted internal signal SAI is supplied to the gate of the differential MOSFET NE.
B is supplied.

Similarly, the differential amplifier circuit DSA2 of the unit sense amplifier SAU00 includes a pair of N-channel type differential M circuits.
Includes OSFETNG and NH. These differential MOSF
The drain of ET is a corresponding P-channel load MO
It is coupled to the power supply voltage VCC through SFETPC and PD, and its commonly coupled source is an N channel MOS.
It is coupled to the ground potential VSS through FETNI. The load MOSFETs PC and PD are current mirror coupled,
Acts as an active load. In addition, MOSFETN
When the internal control signal SA1 is set to the high level, I is selectively turned on and acts as a drive MOSFET. Furthermore, the output signal of the current sense circuit CS1, that is, the non-inverted internal signal SAIT is supplied to the gate of the differential MOSFET NG, and the output signal of the current sense circuit CS2, that is, the inverted internal signal SAIB is supplied to the gate of the differential MOSFET NH. It

On the other hand, the differential amplifier circuit DSA3 of the unit sense amplifier SAU00 includes a pair of N-channel type differential MO.
Includes SFET NJ and NK. These differential MOSFE
The drain of T is a corresponding P-channel load MOS
It is coupled to the power supply voltage VCC through FETPE and PF, and its commonly coupled source is an N channel MOS.
It is coupled to the ground potential VSS through the FET NL. The load MOSFETs PE and PF are current mirror coupled,
Acts as an active load. In addition, MOSFETN
L also selectively turns on when the internal control signal SA1 is set to a high level, and acts as a drive MOSFET. Further, the output signal of the differential amplifier circuit DSA1, that is, the inverted internal signal SADB is supplied to the gate of the differential MOSFET NJ, and the output signal of the differential amplifier circuit DSA2, that is, the non-inverted internal signal SADT is supplied to the gate of the differential MOSFET NK. Supplied. Between the gates of the differential MOSFETs NJ and NK, a transfer gate T2, which is selectively brought into a transmission state when the inverted internal control signal EQ1B is set to low level and the internal control signal EQ1 is set to high level, is provided as an equalizing switch means. To be

The predecode signal Y20 is supplied to one input terminal of the NAND gate NA2, and the internal control signal DY2 is supplied to the other input terminal.
Here, the internal control signal DY2 is set to the high level for a predetermined period after the internal control signal DY1 is returned to the high level, as shown in FIG.
And the high level of the predecode signal Y20, the output signal of the NAND gate NA2 is selectively set to low level, and the internal control signal SA1 is selectively set to high level. When the internal control signal SA1 is set to the high level and the differential amplifier circuits DSA1 to DSA3 are simultaneously activated, the non-inverted internal signal SAIT and the inverted internal signal SAI output from the current sense circuits CS1 and CS2.
In B, a level difference according to the data held in the selected memory cell of the unit memory array MAU00 starts to occur. This level difference is first amplified to a predetermined level by the differential amplifier circuits DSA1 and DSA2, which are the first-stage amplifier circuits, and then these differential amplifier circuits DSA1 and DSA1 and DSA2.
The differential amplifier circuit DSA3 in the subsequent stage that receives the output signal of A2, that is, the inverted internal signal SADB and the non-inverted internal signal SADT
Is amplified by the output signal, that is, the internal control signal S
AO0 is selectively changed from the equalization level, that is, VCC / 2 toward the power supply voltage VCC or the ground potential VSS.

The output signal of the differential amplifier circuit DSA3, that is, the internal signal SAO0 is supplied to the input terminal of the clocked inverter CV1 forming the output latch circuit OL. An output signal of the inverter V6, that is, the inverted internal control signal LH1B is supplied to the control terminal of the clocked inverter CV1, and the output signal is supplied to the input terminal of the inverter V8. The inverter V8 is cross-coupled with the clocked inverter CV2 which receives the output signal of the inverter V7, that is, the internal control signal LH1 at its control terminal, and has a latch form. The output terminal of the inverter V8, that is, the input terminal of the clocked inverter CV2 is the inverter V9.
Via the input terminal of the bus driver BD1 and the output terminal of the bus driver BD1 is connected to the corresponding output data bus DOB0. The predecode signal Y20 is supplied to the control terminal of the bus driver BD1. The internal control signal DY is connected to the input terminal of the inverter V7.
3 is supplied. Further, as shown in FIG. 6, the internal control signal DY3 is set to the low level almost at the same time as the internal control signal DY2 is set to the high level, and the internal control signal DY2 is set to the high level before being returned to the low level. Returned to the level. Furthermore, the output data bus DOB0 is commonly coupled to the output terminals of a similar bus driver BD1 that constitutes the unit sense amplifiers SAU01 to SAU03.

From these facts, the internal control signal DY2, that is, SA1 is set to the high level, and the differential amplifier circuits DSA1 to DSA1.
The output signal SAO0 of the differential amplifier circuit DSA3 that is selectively changed from the equalization level VCC / 2 to the high level or the low level by the operation of the DSA3.
Is transmitted to the bus driver BD1 via the clocked inverter CV1 and the inverter V8 forming the output latch circuit OL while the internal control signal DY3, that is, LH1 is at a low level, and then to the output data bus DOB0. When the internal control signal DY3, that is, LH1 is set to the high level, the internal control signal DY3 is taken into the latch circuit including the inverter V8 and the clocked inverter CV2 and held until the internal control signal DY3 is set to the next low level. . Output latch circuit OL to bus driver BD1
Read data (ADB) output to the output data bus DOB0 via the internal control signal DY4, that is, DOC.
Is set to the high level, the data output buffer OB
Is output from the corresponding unit circuit to the outside of the mask ROM via the data output terminal D0.

As described above, the mask ROM of this embodiment
Is 4 corresponding to each bit of the data output terminals D0 to DF.
64 unit sense amplifiers SAU provided in total
00 to SAUF3, each of these unit sense amplifiers includes a pair of current sense circuits CS1 and CS2, and three differential amplifier circuits DSA1 to DSA3 coupled in two stages. Each of the current sense circuits CS1 and CS2 is provided between the power supply voltage VCC and its output node, that is, the corresponding common data line or dummy bit line, and is output via the common data line or dummy bit line. P-channel MOSFETs P3 and P4 which convert a minute read current into a voltage signal and act as a precharge means for a common data line or a dummy bit line.
And P7 and P8, each unit sense amplifier is
The internal control signal DY1 provided between the output nodes of the current sense circuits CS1 and CS2, that is, the internal control signal EQ1
And a transfer gate T1 which functions as an equalizing switch means by being selectively turned on according to the inverted internal control signal EQ1B.

In this embodiment, the current sense circuits CS1 and CS2 further include MOSFETs P3 and P4.
And P7 and P8, respectively, and P-channel MOSFETs P5 and P6 provided in parallel with each other and receiving the inverted internal control signal EQ1B at their gates. These MOS
The FETs P5 and P6 are selectively turned on in response to the low level of the inverted internal control signal EQ1B, act as precharge means for the corresponding common data line or dummy bit line, and are non-inverted of the differential amplifier circuits DSA1 and DSA2. Also, it acts as an equalizing means for making the inverting input node the same potential. That is, in the mask ROM of this embodiment, while acting as a precharge means for the corresponding common data line or dummy bit line, the mask ROM is subjected to current-voltage conversion, which is the basic function of the current sense circuits CS1 and CS2, and its conductance is changed. MOSFETs P3 and P that cannot be made relatively large
4 and P7 and P8 in parallel form exclusively for mask RO
The MOSFETs P5 and P6 are provided which are selectively turned on only during the equalizing period of M and whose conductance can be sufficiently increased without affecting the basic functions of the current sense circuits CS1 and CS2. By this, the differential amplifier circuit DSA1
, And the equalization processing of the non-inverting and inverting input nodes of the DSA2 and the precharge operation of the common data line and the dummy bit line are accelerated, and the required time te1 is set to the conventional mask ROM shown in FIGS. It can be shortened sufficiently in comparison. As a result, the sense operation of the current sense circuits CS1 and CS2 of the sense amplifier SA can be sped up, the cycle time of the mask ROM or the like can be sped up, and the lowering of the operating power supply voltage can be promoted.

The operational effects obtained by the above-described present embodiment are as follows. That is, (1) a pair of current sense circuits each including a P-channel type first MOSFET that is provided between the power supply voltage of the circuit and its output node and has a relatively small conductance, and its non-inverting and inverting inputs. A differential amplifier circuit whose nodes are respectively coupled to the output nodes of these current sense circuits and are selectively operated according to a predetermined internal control signal, and an equalizer provided between the non-inverting and inverting input nodes of the differential amplifier circuit. In a mask ROM or the like having a sense amplifier including a switch means for switching, a P-channel type second and third MOSFET having a relatively large conductance in parallel with the first MOSFET forming the current sense circuit are provided. Provide and select these MOSFETs at the same time as the equalizing switch means By turning on the logically on state, without affecting the logic threshold level of the current sense circuit,
The effect that the common data line and the dummy bit line can be precharged within a short time is obtained.

(2) According to the above item (1), it is possible to speed up the sensing operation of the current sense circuit of the sense amplifier. (3) The mask ROM according to the above (1) and (2)
It is possible to obtain the effect that the cycle time of the above can be shortened and the lowering of the operating power supply voltage can be promoted.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the mask ROM can have any bit configuration such as x8 or x32 bits, and its storage capacity can also be set arbitrarily. Further, the block configuration of the mask ROM and the names, applications, combinations, etc. of the start control signal and the internal control signal are not restricted by this embodiment. 2 and 3, the division method of the memory array MARY and the peripheral portion thereof can take various forms, and the division method of the cell blocks and the combination method of the cell blocks as a cell block group can be arbitrarily set. FIG.
In the above, each cell block group may have an arbitrary configuration, and the word line selection signal sharing method may be arbitrarily selected. In FIG. 5, the current sense circuits CS1 and CS2 that form the unit sense amplifier SAU00 and the like are shown in FIG.
The conventional precharge circuit by the N-channel MOSFETs NM and NT can be included as they are. Also,
The unit sense amplifiers SAU00 to SAUF3 can include an arbitrary number of differential amplifier circuits, and their combination is also arbitrary. Furthermore, the unit sense amplifier SAU00
The specific circuit configuration, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like can adopt various embodiments. In FIG. 6, the effective level and timing relationship of each internal control signal is not limited to this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the mask ROM which is the field of application which is the background of the invention has been described. However, the present invention is not limited to this and, for example, similar currents are used. The present invention can be applied to various memory integrated circuits including a sense circuit and a differential amplifier circuit, a logic integrated circuit device including such a memory integrated circuit, and the like. The present invention can be widely applied to a semiconductor memory device including at least a current sense circuit and a differential amplifier circuit receiving an output signal thereof, and a device and a system including such a semiconductor memory device.

[0055]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a pair of current sense circuits each including a P-channel type first MOSFET which is provided between the power supply voltage of the circuit and its output node and has a relatively small conductance, and its non-inverting and inverting input nodes are Differential amplifier circuit which is respectively coupled to the output node of the current sense circuit and is selectively operated according to a predetermined internal control signal, and equalizing switch means provided between the non-inverting and inverting input nodes of the differential amplifier circuit. Mask RO with sense amplifier including
In M and the like, the first M that constitutes the current sense circuit
P-channel type second and third MOSFETs having a relatively large conductance are provided in parallel with the OSFET, and these MOSFETs are turned on simultaneously with the equalizing switch means and selectively. As a result, the common data line and the dummy bit line can be precharged within a short time without affecting the logic threshold of the current sense circuit, so that the sense operation of the current sense circuit of the sense amplifier can be speeded up and the mask ROM, etc. It is possible to speed up the cycle time of and reduce the operating voltage of the power supply.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a mask ROM to which the present invention is applied.

2 is a block diagram showing an embodiment of a memory array and a peripheral portion included in the mask ROM of FIG.

FIG. 3 is a block diagram showing an example of a unit memory array MAU00 included in the memory array of FIG.

4 is a circuit diagram showing an embodiment of a cell block group CBG0 included in the unit memory array MAU00 of FIG.

5 is a circuit diagram showing an example of a unit sense amplifier SAU00 included in the sense amplifier of FIG.

FIG. 6 is a signal waveform diagram showing an embodiment in a read mode of the unit sense amplifier SAU00 and related parts of FIG.

FIG. 7 is a circuit diagram showing an example of a unit sense amplifier SAU00 included in a sense amplifier of a mask ROM developed by the inventors of the present application prior to the present invention.

8 is a signal waveform diagram showing an example in a read mode of the unit sense amplifier SAU00 and a related portion of FIG.

[Explanation of symbols]

MARY ... Memory array, XD ... X address decoder, XB ... X address buffer, YS ... Y switch, SA ... Sense amplifier, YD ... Y address decoder, YB ... Y address Buffer, ATD
..Address transition detection circuit, OB ... Data output buffer, DOB0-DOBF ... Output data bus, TG
... Timing generator circuit. MAU00 to MAU03 to MAUF0 to MAUF3 ... Unit memory array,
YSU00 to YSU03 to YSUF0 to YSUF3
... Unit Y switch, SAU00 to SAU03 to SAUF0 to SAUF3 ... Unit sense amplifier, B0
00 to B0063 to BF30 to BF363 ... Bit line, DB00 to DB03 to DBF0 to DBF3
... Dummy bit lines, CD00 to CD03 to CD
F0 to CDF3 ... Common data line. BLC00 ...
Bit line leak circuit, CBG0 to CBG31 ... Cell block group, CB00 to CB03 to CB31
0-CB313 ... Cell block, BS00R-BS
31R, BS00L to BS31L ... Cell block selection signals, WG00 to WG0F to WG310 to WG3
1F ... Word line selection signal, W000 to W00F to W030 to W03F ... Word line. YS0 to YS6
3 ... Bit line selection signal, DSA0 to DSA3 ...
Differential amplifier circuit, OL ... Output latch circuit. P1-PH
... P-channel MOSFETs, N1 to NT ... N
Channel MOSFET, V1 to V9 ... Inverter, CV1 to CV2 ... Clocked inverter, BD
1 ... Bus driver, NA1 to NA2 ... NAND gate, T1 to T3 ... Transfer gate.

Claims (3)

[Claims] 1. A first MOSFET and a second MOSFET each including a first MOSFET of a first conductivity type, which is provided between a first power supply voltage and its output node and has a relatively small conductance.
Current sense circuit and its non-inverting and inverting input nodes are respectively coupled to the output nodes of the first and second current sense circuits, and are selectively operated in accordance with the first internal control signal. And a first MOSFET forming the above-mentioned first and second current sense circuits
And second MOSFETs of the first conductivity type which are provided in parallel with each other and have a relatively large conductance and which are temporarily turned on immediately before the differential amplifier circuit is put into operation. A semiconductor memory device comprising a sense amplifier. 2. The equalizing switch means provided between the non-inverting and inverting input nodes of the differential amplifier circuit and selectively turned on in response to an effective level of a second internal control signal. 2. The first and second MOSFETs are selectively turned on in response to an effective level of the second internal control signal. Semiconductor memory device. 3. The semiconductor memory device is a mask ROM including a bit line and a dummy bit line, the first ROM comprising:
The input node of the current sense circuit is connected to a designated bit line of the memory array via a common data line, and the input node of the second current sense circuit is connected to the dummy bit line. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is present.