JPH08147236A - Transfer controller - Google Patents

Abstract

PURPOSE: To reduce the occupying time of a common bus by using a cache memory and a buffer memory while switching them by judging whether DMA transfer from an input/output device is performed for long data or short data corresponding to its request source ID. CONSTITUTION: When a DMA request is performed from an input/output device 3 to perform a data transfer request for a short data length to an ID identifying circuit 15 inside a transfer controller 1, the ID identifying circuit 15 judges the data transfer request for the short data length corresponding to the sent request source ID and selectors 13 and 14 instruct the selection of the side of a cache memory 11. At the cache memory 11, the transfer data are collected for the unit of a block and transferred through the selector 13 and a system bus 400 to a memory 2. In response to the DMA request from an input/output device 4 to perform a data transfer request for the long data length, the ID identifying circuit 15 performs an instruction so that the selectors 13 and 14 can select the side of a buffer memory 12 and each time the buffer memory 12 receives data for a write unit, those data are sent to the memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer control device for controlling transfer between a plurality of common input / output buses in an information processing system.

[0002]

2. Description of the Related Art Conventionally, there is a technique of connecting a common bus with a connecting line without any buffer when transferring between at least two common buses. With this technique, the independence of the operation of the common bus itself could not be maintained.

To solve this problem, a technique has been proposed in which a common bus is connected via a buffer. An example of this is disclosed in Japanese Patent Laid-Open No. 62-1057. In the transfer control device described in this publication, a request signal is generated and given to the transfer control circuit in order to obtain the bus use right of the common bus.

[0004]

In the technique of connecting the common buses via the buffer, when the data transfer request is repeatedly issued from the device connected to the common bus,
A memory access request is generated via the common bus for each transfer request even with continuous addresses.

Therefore, there is a problem that the traffic on the common bus is not improved.

An object of the present invention is to provide a transfer control device which reduces the occupation time of the common bus.

Another object of the present invention is to improve the throughput for memory.

Another object of the present invention is to provide a transfer control device which improves traffic on a common bus.

Another object of the present invention is to provide a transfer control device which improves the throughput of the system.

[0010]

A first transfer control device of the present invention is a device connected to a plurality of common buses including a common bus to which a plurality of data transfer requesting devices are connected, and the plurality of requesting devices are provided. A request source discriminating means (hereinafter referred to as an ID discriminating circuit) for discriminating a request source device by an ID code given from one of the requesting devices via the common bus, and a data transfer of a long data length by the ID discriminating circuit. If it is determined that the request is from the requesting device, the data is transferred through the buffer memory, and if it is determined that the request is from the device requesting the data transfer of the short data length, the data is transferred through the cache memory. Thus, the selection means (hereinafter referred to as a selector) for selecting one of the buffer memory and the cache memory is included.

According to a second transfer control device of the present invention, in the first transfer control device, the selector is connected to each of the plurality of common buses, and the buffer memory and the cache memory are provided between the plurality of selectors. Is connected in parallel.

A third transfer control device of the present invention is the second transfer control device, the data transfer request device is an input / output device, and the input / output device is connected to the plurality of common buses. A memory for exchanging data with at least one of the buffer memory and the cache memory is connected to the common bus which does not exist.

In a fourth transfer control device of the present invention, in the first transfer control device, one of the plurality of data transfer request devices outputs a data transfer request having a long data length, and the plurality of data transfer requests are issued. Another one of the devices outputs a data transfer request having a short data length.

A fifth transfer control device of the present invention is the third transfer control device.
In the above transfer control device, the data transfer between the cache memory and the memory is performed in block units.

A sixth transfer control device of the present invention is the third transfer control device, wherein the buffer memory receives the data for each write unit to the memory each time the data is received from the request device. Characterized by sending to memory.

A seventh transfer control device of the present invention is the third transfer control device.
In the transfer control device, the buffer memory reads the continuous data after the address received from the requesting device from the memory and sends it to the requesting device, and if the buffer memory has a space, the preceding reading is performed from the memory. It is characterized by

[0017]

An embodiment of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, a transfer control device 1 according to an embodiment of the present invention includes a common bus 1 for connecting a memory 2.
Is connected to the system bus 400. Further, the device 1 is an input / output local bus connecting the input / output device 3 requesting the transfer of a small amount of data, that is, a short length of data, and the input / output device 4 requesting the transfer of a large amount of data, that is, a long length of data. It is also connected to 500.

A transfer control device 1 which is an embodiment of the present invention
Is a cache memory 11, a buffer memory 12, a selector 13 on the system bus side arranged and connected between the cache memory 11 and the buffer memory 12 and the system bus 400 to select either the cache memory or the buffer memory, and the cache. A selector 14 on the input / output local bus side which is arranged / connected between the memory 11 and the buffer memory 12 and the input / output local bus 500 to select either the cache memory or the buffer memory, and a direct memory access (DMA) request. Request source ID for identifying the request source device
It includes an ID identification circuit 15 that identifies the requesting device by a code and outputs the result of the determination to the signal line 101 as a bus selection signal.

One of the characteristics of one embodiment of the present invention is that the ID identification circuit 15 is responsive to a data transfer request of a short data length from the input / output device 3 and the ID identification circuit 15 is supplied via the signal line 101 to the bus. A selection signal instructs selectors 13 and 14 to select the cache memory 11 side. As a result, data having a short data length can be output to the input / output device 3, the input / output local bus 500, the selector 14, and the cache memory 1.
1, selector 13, system bus 400 and memory 2
One embodiment of the present invention controls the transfer to be performed by the following route.

Another feature of one embodiment of the present invention is that the ID identification circuit 15 is supplied through the signal line 101 in response to a long data length data transfer request from the input / output device 4. Instructing the selectors 13 and 14 to be selected on the buffer memory 12 side by the bus selection signal. As a result, data having a long data length can be output to the input / output device 4, the input / output local bus 500, the selector 14, the buffer memory 12,
One embodiment of the present invention controls transfer by the route of the selector 13, the system bus 400 and the memory 2.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, I in the transfer control device 1 from the input / output device 3 which makes a data transfer request of a short data length.
A DMA request is made to the D identification circuit 15. In response to this DMA request, the ID identification circuit 15 determines that the DMA request is a data transfer request with a short data length based on the request source ID code sent. Based on the result of this determination, the ID identifying circuit 15 sends a signal to the line 101 so that the selectors 13 and 14 select the cache memory 11 side.

In the cache memory 11, the transfer data is collected for each cache line corresponding to the block unit of the set associative system, for example. Therefore, when data having a short data length is transferred from the input / output device 3 several times and collected in cache line units, the data is transferred from the cache memory 11 to the memory 2 via the selector 13 and the system bus 400. Therefore, writing from the cache memory 11 to the memory 5 and reading from the memory 5 to the cache memory 11 are performed in block units.

The ID identifying circuit 15 in the transfer control device 1 receives a D from the input / output device 4 which requests a data transfer of a long data length.
The MA request is made. ID in response to this DMA request
The identification circuit 15 receives the request source ID code D
It is determined that the MA request is a data transfer request with a long data length. Based on the result of this determination, the ID identification circuit 15 sends a signal to the line 101 so that the selectors 13 and 14 select the buffer memory 12 side.

When the DMA request from the input / output device 4 which makes a data transfer request of a long data length is a memory write request, each time the buffer memory 12 receives from the input / output device 4 data of the writing unit to the memory 2. Then, the data is sent to the memory 2.

If the DMA request from the input / output device 4 is a memory read request, continuous data after the address received from the input / output device 4 is read from the memory 2,
While the read data is sent to the input / output device 4, the preceding read from the memory 2 is performed as long as the buffer memory 12 has a free space.

[0028]

The transfer control device of the present invention is provided with both a cache memory and a buffer memory, and judges whether the DMA transfer from the input / output device is long data or short data based on its requester ID and determines the cache memory and the buffer. By switching and using the memory, it is possible to suppress the number of times of memory access as much as possible, reduce the occupied time of the system bus and the input / output local bus that are common buses, improve the traffic, and improve the throughput for the memory. As a result, the present invention can also improve the throughput of the system.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Transfer Control Device 2 Memory 3 I / O Device 4 I / O Device 11 Cache Memory 12 Buffer Memory 13 System Bus Side Selector 14 I / O Local Bus Side Selector 15 ID Identification Circuit 101 Signal Line 400 System Bus 500 I / O Local Bus

Claims (3)

[Claims] 1. A device connected to a plurality of common buses including a common bus to which a plurality of data transfer requesting devices are connected, wherein one requesting device of the plurality of requesting devices passes through the common bus. A request source discriminating unit that discriminates the request source device based on the given ID code, and if the request source discriminating unit discriminates the request from the device that makes the data transfer request of the long data length, the plurality of the plurality of units are transmitted via the buffer memory. The buffer memory and the buffer memory are configured to transfer data between the common buses and transfer the data between the plurality of common buses via a cache memory if it is determined that the request is from a device that requests a data transfer with a short data length. A transfer control device comprising: a selection unit that selects either one of the cache memories. 2. The plurality of selecting means are connected to each of the plurality of common buses, and the buffer memory and the cache memory are connected in parallel between the plurality of selecting means. Item 1. The transfer control device according to item 1. 3. The data transfer requesting device is an input / output device, and a common bus to which at least one of the plurality of common buses is not connected is connected to at least one of the buffer memory and the cache memory. 3. The transfer control device according to claim 2, further comprising a memory connected to and from which data is transferred.