JPH08146087A - Inspection apparatus for electronic circuit - Google Patents

Abstract

PURPOSE: To provide an inspection apparatus capable of inspecting an electronic circuit to be tested by the comparison of output data regardless of the time lag between the outputs of a standard electronic circuit and the electronic circuit to be tested. CONSTITUTION: The same data is given to a standard electronic circuit 2 and an electronic circuit 3 to be tested from a control signal/input data generator 1, and instruction to start processing is given. The standard electronic circuit 2 and the electronic circuit 3 to be tested process data in internal timing to output data. The output data are written in first and second FIFO memories 4, 5 by the writing clocks independently formed by first and second writing clock forming devices 7, 8. The data written in the first and second FIFO memories 4, 5 are read by the same reading clock formed by a reading clock forming device 9 to be compared and judged by an output data comparator 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit inspection apparatus for inspecting the operation of an electronic circuit under test by comparing the output of the electronic circuit under test with the output of a standard electronic circuit.

[0002]

2. Description of the Related Art Conventionally, when an electronic circuit is tested, an electronic circuit to be tested (electronic circuit under test) is compared with a standard. There are roughly two comparison methods. One method is to apply an input to the electronic circuit under test from a signal generator and compare the output signal with expected data prepared in advance in the inspection apparatus for determination. With this method, expected data must be prepared in the inspection device, but it requires a great deal of effort to create the expected data, and especially in the case of a circuit that handles large-capacity data such as image data, a huge amount of data is required. There is a problem that expected data must be prepared and held in the inspection device.

The other method is to judge by comparing the signals output from the same signals by applying the same signal from the input signal generator to the standard electronic circuit (standard electronic circuit) and the electronic circuit under test. Is. In this method, it is not necessary to prepare expected data, so the inspection device can be simplified. However, in the case of a circuit that operates by the internal oscillation means, the timings of the outputs from the standard electronic circuit and the electronic circuit under test may deviate, and it may be difficult to make a comparison determination. For example, it is difficult to compare the output of a circuit, such as a microcomputer, which receives an instruction, executes it internally, and has a non-constant time to appear at the output with the output of a standard electronic circuit.

As a measuring method of such a circuit having different output timing, for example, there is a method described in Japanese Patent Publication No. 3-9427. In this measuring method, it is considered to control the clock input to the device and synchronize the outputs of the standard and the device under test for comparison.
However, in the case of a circuit that operates by internal oscillation means, in order to synchronize the output signals of the standard electronic circuit and the electronic circuit under test, the internal oscillation means must be disabled and a controlled clock must be input. I won't. Further, in order to create a clock with an arbitrary phase, it is necessary to change the oscillation speed, which is technically difficult.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic circuit inspecting apparatus capable of inspecting an electronic circuit under test by comparing output data regardless of a time difference between outputs of a standard electronic circuit and an electronic circuit under test. It is intended to provide.

[0006]

According to a first aspect of the present invention, there is provided a standard electronic circuit as a standard in an electronic circuit inspection device for inspecting the operation of an electronic circuit under test, and the standard electronic circuit. First storage means provided at a subsequent stage of the circuit and having an output written therein at a timing according to the operation of the standard electronic circuit; and at a timing provided at a subsequent stage of the electronic circuit under test according to the operation of the electronic circuit under test. It is characterized in that it has a second storage means to which an output is written, and a comparison means for sequentially reading and comparing the contents from the first storage means and the second storage means with the same read clock.

According to a second aspect of the present invention, in the electronic circuit inspecting apparatus according to the first aspect, the writing from the standard electronic circuit to the first storage means is started and the electronic circuit under test is started. It has a read clock generation means for detecting the start of writing to the second storage means and generating a read clock equal to or slower than the clock of the slower circuit according to the detection, and generated by the read clock generation means. The contents are sequentially read from the first storage means and the second storage means by the generated clock, and the comparison means performs the comparison.

[0008]

According to the present invention, the same data is given to the standard electronic circuit and the electronic circuit under test, and the output from the standard electronic circuit is written in the first storage means at a timing according to the operation of the standard electronic circuit, The output from the test electronic circuit is written in the second storage means at a timing according to the operation of the electronic circuit under test. Then, the contents are sequentially read from the first storage means and the second storage means by the same read clock and compared by the comparison means. As a result, the time difference between the outputs of the standard electronic circuit and the electronic circuit under test can be absorbed by the first storage means and the second storage means, and comparison can be performed at the same timing. Therefore, it is possible to easily inspect, for example, a circuit operated by an internal oscillation means or a circuit in which a time required from input to output changes, without preparing a huge amount of expected data which is conventionally required. be able to.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first inspection apparatus for electronic circuits according to the present invention.
It is a block diagram showing an embodiment of the. In the figure, 1 is a control signal / input data generator, 2 is a standard electronic circuit, 3 is an electronic circuit under test, 4 is a first FIFO memory, and 5 is a second F circuit.
IFO memory, 6 is an output data comparator, 7 is a first write clock generator, 8 is a second write clock generator, and 9 is a read clock generator.

It is assumed that the standard electronic circuit 2 and the electronic circuit under test 3 have the same structure and are self-propelled circuits having an oscillator inside. The response time for external control and data input is not constant. The control signal / input data generator 1 generates a start signal of operation and data to be input for a test, and the standard electronic circuit 2 and the electronic circuit under test 3
To enter.

The output of the standard electronic circuit 2 is sequentially written in the first FIFO memory 4 in accordance with the clock generated by the first write clock generator 7. The output of the electronic circuit under test 3 is sequentially written in the second FIFO memory 5 according to the clock generated by the second write clock generator 8. The first FIFO memory 4 and the second FIFO memory 5 are read clock generators 9.
According to the clock of, the data written previously is sequentially read. The output data comparator 6 has a first FIFO.
The data read from the memory 4 and the second FIFO memory 5 are compared, and the determination result is output.

The first write clock generator 7 is responsive to the synchronization signal output from the standard electronic circuit 2 for the first FI.
A write clock for the FO memory 4 is generated. Similarly,
The second write clock generator 8 is connected to the electronic circuit under test 3
A write clock for the second FIFO memory 5 is generated according to the synchronization signal output from the. The read clock generator 9 generates a read clock. This read clock needs to be the same as or slower than the slower clock of the standard electronic circuit 2 or the electronic circuit under test 3.

Next, an example of the operation in one embodiment of the electronic circuit inspection apparatus of the present invention will be described. First, the same data is supplied from the control signal / input data generator 1 to the standard electronic circuit 2 and the electronic circuit under test 3, and a control signal instructing the processing of the data is supplied. The standard electronic circuit 2 and the electronic circuit under test 3, which have been instructed to process the data, process the data at internal timings, and start output of data at different timings. First write clock generator 7
And the second write clock generator 8 detects the synchronization signal output when the output of the data from the standard electronic circuit 2 and the electronic circuit under test 3 starts, and independently generates the write clock, and respectively generates the first write clock. To the first FIFO memory 4 and the second FIFO memory 5. Standard electronic circuit 2
The data output from the electronic circuit under test 3 is used as the first FIFO memory 4 and the second FIFO in the subsequent stage of both circuits.
Data is written to the O memory 5 by the write clocks generated by the first and second write clock generators 7 and 8.

The read clock generator 9 generates a read clock and outputs the read clock to the first and second FIFO memories 4 and 5.
Give to. Based on this read clock, the first
And the data is output from the second FIFO memories 4 and 5. The output data comparator 6 compares the data output from the first and second FIFO memories 4 and 5 and makes a determination.

As described above, the outputs from the standard electronic circuit 2 and the electronic circuit under test 3 which operate independently are written in the first and second FIFO memories 4 and 5 at the write clocks corresponding to the respective operations. Be done. Then, the data is read by the same read clock.
As a result, the time difference between the outputs can be absorbed without changing the clocks inside the standard electronic circuit 2 and the electronic circuit under test 3, and the comparison can be performed even if there is a speed difference between the two circuits.

FIG. 2 is a block diagram showing the second embodiment of the electronic circuit inspection apparatus according to the present invention. In the figure, the same parts as those in FIG. 10
Is a first input data generator, 11 is a second input data generator, 12 is a control signal generator, 13 is an image processing standard circuit, and 14 is an image processing circuit under test. In this embodiment, an example in which an image processing circuit is used as the standard electronic circuit and the electronic circuit under test is shown. Of course, other circuits may be used.

The first input data generator 10 outputs the input data to the image processing standard circuit 13 in response to a request for the input data from the image processing standard circuit 13. The second input data generator 11 outputs the input data to the image processing circuit under test 14 in response to the request for the input data from the image processing circuit under test 14. The control signal generator 12 supplies the image processing standard circuit 13 and the image processing circuit under test 14 with
Instruct image processing. The read clock generator 9 selects a synchronizing signal of a circuit whose data output is delayed among the image processing standard circuit 13 and the image processing circuit under test 14 and generates a reading clock based on the selected synchronizing signal.

Next, the second electronic circuit inspection device of the present invention
An example of the operation in this embodiment will be described. The control signal generator 12 instructs the image processing standard circuit 13 and the image processing circuit under test 14 to perform image processing. The image processing standard circuit 13 and the image processing circuit under test 14 each process data at internal timing, and request input data from the first or second input data generators 10 and 11 as required. . First and second input data generators 10, 1
1, the image processing standard circuit 13 and the image processing circuit under test 1
Data is output in accordance with the synchronization signal output from 4. Image processing standard circuit 13, image processing circuit under test 14
Will take in the data output from the first and second input data generators 10 and 11 as input data and perform processing.

The image processing standard circuit 13 and the image processing circuit under test 14 output the processing result together with the synchronization signal. The synchronization signal is input to the first and second write clock generators 7 and 8, respectively, and the write clock is generated and input to the first and second FIFO memories 4 and 5. The image data output from the image processing standard circuit 13 and the image processing circuit under test 14 are respectively written in the write clock generator 7,
First, second, based on the write clock generated in
Are written in the FIFO memories 4 and 5.

The read clock generator 9 monitors the synchronizing signals output from the image processing standard circuit 13 and the image processing circuit under test 14, and when it is confirmed that the image data is output from both circuits, the The read clock is output to the first and second FIFO memories 4 and 5.
FIG. 3 is an explanatory diagram of the timing of the read clock. For example, it is assumed that the image processing standard circuit 13 starts output before the circuit under test 14 for image processing. At the time when the image processing standard circuit 13 starts outputting, the circuit under test 14 for image processing has not started outputting yet, and therefore does not output the read clock. After that, when the image processing circuit under test 14 starts output, the output of the read clock is started as shown in FIG.

The output data comparator 6 can obtain the image data output from the image processing standard circuit 13 and the image processing circuit under test 14 at the same timing and compare the two output data. Based on the comparison result, the test result of the image processing circuit under test 14 can be obtained.

In the above-described operation example, the read clock should not exceed the timing at which the output data of the image processing standard circuit 13 and the image processing circuit under test 14 is written. That is, the read clock must end at the time when the writing of the output data of the image processing standard circuit 13 and the image processing circuit under test 14 ends or after that. The read clock speed needs to be a speed that satisfies this condition.

In the above-described operation example, the read clock generator 9 includes the image processing standard circuit 13 and the image processing circuit under test 1.
The synchronization signal of each circuit is used as a means for knowing that the data has been output from 4. Any method may be used as long as it is known that the data is output from each circuit, and for example, an empty signal output from the first and second FIFO memories 4 and 5 may be used. Alternatively, it is also possible to use the write clocks output from the first and second write clock generators 7 and 8.

In each of the above-described examples, the comparison operation of the output data comparator 6 is explained as being completed by the time when the next data is read by the read clock. It is possible that the processing speed of the circuit in the subsequent stage is slower than that of the above. In such a case, it is possible to input a timing signal for slow processing to the read clock generator 9 and generate a read clock in consideration of the processing speed of these signals. As a result, the first and second FIFO memories can also absorb the speed difference between the standard electronic circuit and the electronic circuit under test and the circuit in the subsequent stage.

In each of the above-mentioned examples, the output from the standard electronic circuit and the electronic circuit under test is started in response to the synchronizing signal, but the clock signal corresponding to each data is not output. As described. Therefore, the first and second write clock generators generate the write clock based on the synchronization signal. The output data may be generated according to the internal clocks of the standard electronic circuit and the electronic circuit under test, and in such a case, a circuit capable of extracting the internal clocks of the standard electronic circuit and the electronic circuit under test. For example, the write clock can be generated according to the internal clock.

In some electronic circuits, a clock signal may be output together with the output of individual output data. In such a case, the write clock generators 7 and 8 may not be used, and the timing signal may be directly input to the first and second FIFO memories 4 and 5.

The first and second FIFO memories 4 and 5 are
Other storage means can be substituted. For example, various storage means such as a 2-port memory, a normal semiconductor memory, a mass storage device, etc. can be used. When these storage means are used, the first and second write clock generators 7 and 8 generate the write address together with the write clock, and the read clock generator 9 produces the read address together with the read clock. Just configure it.

[0028]

As is apparent from the above description, according to the present invention, even in the circuit operated by the internal oscillation means, the standard electronic circuit is irrespective of the time difference between the outputs of the standard electronic circuit and the electronic circuit under test. The inspection can be performed by comparison with. This has the effect that the electronic circuit under test can be tested in real time without preparing a large amount of expected data.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of an electronic circuit inspection device of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the electronic circuit inspection device according to the present invention.

FIG. 3 is an explanatory diagram of a read clock timing.

[Explanation of symbols] 1 ... Control signal / input data generator, 2 ... Standard electronic circuit,
3 ... Electronic circuit under test, 4 ... First FIFO memory, 5 ...
Second FIFO memory, 6 ... Output data comparator, 7 ... First write clock generator, 8 ... Second write clock generator, 9 ... Read clock generator, 10 ... First
Input data generator, 11 ... Second input data generator,
12 ... Control signal generator, 13 ... Image processing standard circuit, 14
… Image processing circuit under test.

Claims (2)

[Claims] 1. An electronic circuit inspecting apparatus for inspecting an operation of an electronic circuit under test, wherein a standard electronic circuit as a standard and an output provided at a subsequent stage of the standard electronic circuit at a timing according to an operation of the standard electronic circuit And a second storage means which is provided in a subsequent stage of the electronic circuit under test and whose output is written at a timing according to the operation of the electronic circuit under test, the first storage means, and An inspection apparatus for an electronic circuit, comprising comparison means for sequentially reading the contents from the second storage means by the same read clock and comparing the contents. 2. It is detected that the standard electronic circuit starts writing to the first storage means and that the electronic circuit under test starts writing to the second storage means, and whichever is slower according to the detection. It has a read clock generation means for generating a read clock which is equal to or slower than the clock of the circuit, and the contents are sequentially outputted from the first storage means and the second storage means by the clock generated by the read clock generation means. 2. The electronic circuit inspection apparatus according to claim 1, wherein the inspection is performed and the comparison is performed by the comparison means.