JPH0814606B2 - Logic circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a logic circuit capable of easily performing a logic function test.

[Technical background of the invention and its problems]

The logic integrated circuit test includes a DC characteristic test for testing the DC characteristic of this circuit, an AC characteristic test for testing the AC characteristic, and a logic function test for testing the logic function. Among them, the logical function test is always performed in the quality judgment test of the mass production line and the acceptance inspection of the user, and it is important how to perform it properly and efficiently.

When conducting a test in a mass production line, conventionally, a method has been adopted in which a needle is directly applied to a semiconductor chip on which a logic integrated circuit is formed to monitor the logic state of a required node. However, it is becoming extremely difficult to accurately pinpoint a node to be monitored by this method for an increasingly fine logic integrated circuit. Furthermore, in recent years, logic integrated circuits are often designed using automatic placement and routing programs, and it is becoming difficult to accurately specify a desired node. As described above, there are many problems in the method of directly monitoring the state of a necessary node by directly applying the needle to the semiconductor chip.

In addition, LSSD (Leve
l Sensitive Scan Design) like a logic integrated circuit, add flip-flops to the registers in the logic circuit, connect these flip-flops in series,
There is a way to monitor register data. However, only data in registers can be monitored by this method. That is, only the result data output from the combinational circuit can be monitored, and if this result data is incorrect, it is difficult to identify from the result data which part of the combinational circuit is defective. There was a problem. This problem was important especially when the combinational circuit was large-scaled.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic circuit that can monitor even nodes in a combinational circuit and can easily perform a logic function test.

[Outline of Invention]

In order to achieve the above object, a logic circuit of the present invention sets a state of each internal node to a combinational circuit having a plurality of internal nodes and a plurality of preselected internal nodes among the plurality of internal nodes in the combinational circuit. A plurality of holding circuits that are respectively connected to each other via a lead wire for monitoring and that simultaneously take in and hold the data signal of each internal node in response to the take-in command, and the data signal read from the holding circuit. A common signal line for transmission, a plurality of gates each inserted between the plurality of holding circuits and the common signal line and opened / closed in response to a command, and a supplied address signal are decoded, An address decoder for operating one gate corresponding to an address designated by the address signal among the plurality of gates, and designated by the address signal. Data of the holding circuit reads from the common signal line, and wherein the.

Example of Invention

A logic circuit according to a first reference example of the present invention is shown in FIG. The function of this logic circuit is basically to perform a logical operation on the input data D _in from the outside and output the operation result to the output data D in.
_It is output as _out . Therefore, this logic circuit has a register 1 for storing the input data D _in , a large-scale combination circuit 3 for performing a logical operation, and a register 2 for storing the output data D _out . A clock signal CK1 for synchronizing the operations is supplied to the registers 1 and 2. This large-scale combination circuit 3 is divided into several small-scale unit combination circuits 4,5, 6, 7 for each function. These unit combination circuits
Internal node N ₁ between the 4, 5, 6, 7, pull the wire from N _2, N _3, the data holding circuit L ₁₁ ~L _1l through the lead _{wire, L 21 ~L 2m, L 31} ~L
Connect to _3n . The data holding circuits L _{11 to} L _1l are connected to the respective bits of the _1- bit internal node N ₁ and are connected to the data holding circuit L _21.
~ L _2m is connected to each bit of the m-bit internal node N ₂ , and the data holding circuits L _{31 to} L _3n are connected to the n-bit internal node N _3.
Is connected to each bit of. These data holding circuit L
_{11 to} L _1l , L _{21 to} L _2m , and L _{31 to} L _3n are connected in series in a shift register shape, and the latch signal φ _L and the data transfer clock DTXCK1 are input to each.

Next, the operation will be described. A latch signal φL, which is a command for taking in data during a logic function test, is output at a predetermined timing for holding data. Then, the logic states of the nodes N _{1 to} N ₃ are held in the data holding circuits L _{11 to} L _3n , respectively.
Then, when outputting the data transfer clock DTXCK1, held data are sequentially transferred to the data holding circuit L ₁₁ in ~L _3n, bit by bit through a common bus B which is a common signal line as a monitor data D _mon output To be done.

As described above, according to this embodiment, the logic state of the internal node in the large-scale combinational circuit can be read out from the outside, and it is possible to know from this data which part in the large-scale combinational circuit is defective. You can

Next, FIG. 2 shows a logic circuit according to a second reference example of the present invention. The present embodiment is characterized in that the data holding circuits L ₁ , L ₂ , L ₃ are configured by registers having the bit widths of the internal nodes N ₁ , N ₂ , N ₃ . The latch signal φ _L and the data transfer clock DTXCK1 are input to the data holding circuits L ₁ , L ₂ , and L ₃ , respectively. Data holding circuits L ₁ , L ₂ , L _{3 are} generated by the latch signal φ _L.
The data held in the monitor data D _mon is transferred to the data holding circuits L _{1 to} L ₃ by the data transfer clock DTXCK1.
As a result, a plurality of bits are simultaneously read out via the common bus B. As described above, according to the present embodiment, the test data is read simultaneously for every plural bits, so that the data can be read in a short time.

A logic circuit according to the first embodiment of the present invention is shown in FIG. In this embodiment, the data holding circuit L _{11 for} each 1 bit is used.
~ L _1l , L ₂₁ ~ L _2m , L ₃₁ ~ L _3n Tri-state buffers T ₁₁ ~ T _1l , T ₂₁ ~
Provide T _2m , T _{31 to} T _3n . These tristate buffers
The control signals T _{11 to} T _3n are input from the decoder 8. The decoder 8 decodes the input address signal AD that specifies the held data of the node to be monitored, and outputs the control signal to the tristate buffer of the data holding circuit specified by the address. As a result, the data of the designated data holding circuit is transferred to the monitor data D via the common bus B.
Output as _mon . In the present embodiment, since an arbitrary data holding circuit can be directly designated by the address signal AD, the test data can be read out more efficiently than when the data shown in FIGS. 1 and 2 are sequentially shifted and output. You can

Next, a logic circuit according to the second embodiment of the present invention is shown in FIG. In this embodiment, the data holding circuits L ₁ , L ₂ and L ₃ are configured by registers having the bit widths of the internal nodes N ₁ , N ₂ and N ₃ , and the tri-state buffers T ₁ , T ₂ and T ₃ also have the same structure. Correspondingly, it has a plurality of bit widths. The input address signal AD is decoded by the decoder 8, and the decoded signal is input to each tristate buffer T ₁ , T ₂ , T ₃ .
The tri-state buffer of the data holding circuit designated by the address signal AD is brought into the connected state and is output as the monitor data D _mon of a plurality of bits via the common bus B. As described above, in the present embodiment, arbitrary test data can be directly designated collectively in units of a plurality of bits, so that efficient and high-speed reading can be performed.

Although the data held in the data holding circuit is read by various methods in the above-described embodiments, the data may be read by any method without being limited to the above method. It goes without saying that the data holding circuit may be provided for the registers other than the internal node.

〔The invention's effect〕

As described above, according to the logic circuit of the present invention, a plurality of nodes inside the combinational circuit can be simultaneously and reliably monitored at arbitrary timings. Moreover, it is easy to monitor because only arbitrary data is selected from the monitor data of each node acquired at the same time and output to the outside via the common bus (common signal line), and the number of IC package terminals is small. Complete. Therefore, when evaluating a logic circuit having a large-scale combinational circuit, if this combinational circuit is subdivided into appropriate units and the nodes between them are monitored, efficient failure analysis can be performed with a small number of test vectors. The logic function test can be performed easily.

[Brief description of drawings]

1 is a circuit diagram of a logic circuit according to a first reference example of the present invention, FIG. 2 is a circuit diagram of a logic circuit according to a second reference example of the present invention, and FIG. 3 is a first embodiment of the present invention. 4 is a circuit diagram of a logic circuit according to the present invention, and FIG. 4 is a circuit diagram of a logic circuit according to a second embodiment of the present invention. 1 ... Register, 2 ... Register, 3 ... Combination circuit,
4,5,6,7 …… Unit combination circuit, 8 …… Decoder, N _{1 to} N ₃
...... Internal node, L _{1 to} L ₃ ,, L _{11 to} L _1l , L _{21 to} L _2m , L _{31 to} L _3n
...... Data holding circuit, T _{1 to} T ₃ , T _{11 to} T _1l , T _{21 to} T _2m , T ₃₁ to
T _3n …… Tri-state buffer, B …… Common bus, D _in
...... Input data, D _out …… Output data, D _mon …… Monitor data, CK1 …… Clock signal, φ _L …… Latch signal, DTXCK1 …… Data transfer clock signal.

Claims (1)

[Claims] 1. A combinational circuit having a plurality of internal nodes, and a plurality of internal nodes selected from among a plurality of internal nodes inside the combinational circuit via a lead wire for monitoring the state of each internal node. A plurality of holding circuits that are connected to each other and that simultaneously take in and hold the data signals of the internal nodes in response to the take-in command; and common signal lines that transmit the data signals read from the holding circuits, respectively. A plurality of gates inserted between the plurality of holding circuits and the common signal line to open and close in response to a command; and an address signal supplied to decode the address signal among the plurality of gates. An address decoder for operating one gate corresponding to an address designated by the address signal, and a data signal of the holding circuit designated by the address signal. It reads from the serial common signal line, a logic circuit, characterized in that.