JPH08139596A - Phase comparator and pll circuit - Google Patents

Abstract

PURPOSE: To quickly acquire synchronization in the case of forming a PLL circuit by discriminating whether or not phase differences detected by first and second signal comparison means are within the range of ±π and selectively outputting the phase difference within the range of ±π. CONSTITUTION: A first phase comparator 22 compares first reference signals R1 and fluctuation signals V and outputs phase delay signals U1 and advance signals D1 for the phase difference. Also, reference signals R are shifted for πby a phase shifter 23, the signals and the signals V are compared in a second phase comparator 24 and the delay signals U2 and the advance signals D2 are outputted. A first discrimination device 25 outputs discrimination signals Q1 when the signals U1 and D1 exceed the range of ±π and a second discrimination device 26 outputs the discrimination signals Q2 when the signals U2 and D2 exceed the range of ±π to an output switching device 27. The switching device 27 outputs the signals U1 and D1 as the delay signals U and the advance signals D when the signals Q2 are inputted and outputs the signals U2 and D2 as the signals U and D when the signals Q1 are inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase comparator and a PLL.
(Phase Locked Loop) circuit.

[0002]

2. Description of the Related Art A conventional phase comparator detects a phase difference by comparing a fluctuation signal with a reference signal and detects the phase difference when the phase of the fluctuation signal is ahead of the phase of the reference signal. And outputs the phase difference when the phase of the fluctuation signal is delayed with respect to the phase of the reference signal as a phase delay signal.

A PLL circuit formed by using such a phase comparator inputs the output of the phase comparator to a VCO (Voltage Controlled Oscillator) which is a voltage controlled oscillator, and compares the output of this VCO with the phase comparison. To return to the vessel.
Therefore, the frequency of the output signal of the VCO is synchronized with the frequency of the input signal of the phase comparator.

The phase comparator as described above is classified into a memory type having a storage element and a non-memory type having no storage element. For example, as shown in FIG. 17, a digital memory type phase comparator 1 includes input sections 2 and 3 for a reference signal R and a fluctuation signal V and an output section 4 for a phase delay signal U and a phase advance signal D. , 5 and are formed by a combination of a large number of NAND gates 6 to 14. In this case, the RSs functioning as a storage element are formed by the NAND gates 7 and 8 and the NAND gates 9 and 10 connected in a loop.
Flip-flops F1, F2 are formed.

In such a structure, as shown in FIG. 18A, when the fluctuation signal V is delayed from the reference signal R, the phase advance signal D is not generated but the phase delay signal U is generated, As shown in FIG. 18B, when the fluctuation signal V is ahead of the reference signal R, the phase advance signal D is generated without generating the phase delay signal U.

Therefore, as shown in FIG. 19, a charge pump 15 and an LPF (Low Pass Filter) 16 which is a loop filter are connected to the phase comparator 1 as described above, and the phase delay output from the phase comparator 1 is delayed. When the signal U and the phase lead signal D are converted into an analog voltage by the charge pump 15 and then filtered by the LPF 16, the characteristics of the output voltage and the phase difference are as shown in FIG. In this case, the phase comparator 1 determines that the output voltage and the phase difference are “−2π
Since it has a linear relationship in the range of up to + 2π ″, it functions as a frequency comparator.

The memory type phase comparator 1 as described above is
The range in which the phases can be compared characteristically is as wide as "-2π to + 2π", but if the comparison operation becomes unstable due to a disturbance such as noise, this unstable state causes the RS-flip-flop F1,
Continue long term for F2. On the other hand, in the non-memory type phase comparator, even if the operation becomes unstable due to the disturbance, the unstable state ends early because there is no storage element, but the range in which the phases can be compared is “−π / 2 to + π”. It is as narrow as / 2 ".

Therefore, the PLL circuit using the memory type phase comparator can be synchronized even when the phase difference of the signal frequency is large, but the PLL circuit using the non-memory type phase comparator is It is difficult to synchronize from the state where the phase difference of the signal frequency is large.

More specifically, the PLL circuit synchronization process includes a frequency pulling process and a phase pulling process. In the case of a PLL circuit using a non-memory type phase comparator, the frequency pull-in is performed by the DC component when the phase difference output largely fluctuates due to delay and advance, so that it takes time to synchronize and the reference signal It may be accidentally drawn into higher frequencies. In the case of the PLL circuit using the memory type phase comparator, the function as the frequency comparator shortens the synchronization time and prevents the higher frequency of the reference signal. However, as mentioned above, the memory type phase comparator becomes unstable when the operation becomes unstable due to disturbance.
Since this continues for a long time, the PLL circuit using such a phase comparator also remains in an unstable state for a long time.

For example, in a memory type phase comparator,
As shown in FIG. 21A, when one of the reference signals R drops out, the next reference signal R and the fluctuation signal V are synchronized, the phase delay signal U is no longer output, and the phase advance signal D is output. Sometimes. Similarly, as shown in FIG. 21B, when one spike noise is generated in the reference signal R, this spike noise and the next fluctuation signal V are synchronized with each other, and the phase advance signal D is not output and the phase delay is delayed. The signal U may be output.

That is, a PLL circuit using a memory type phase comparator and a PL circuit using a non-memory type phase comparator
The L circuit has contradictory advantages and disadvantages. A PLL circuit that solves such a problem is disclosed in
-70124 gazette. The PLL circuit disclosed in this publication has a memory-type phase comparator and a non-memory-type phase comparison switchably, and a memory-type phase comparator having a wide phase comparison range in an initial state where a phase difference of signal frequencies is large. After the phase comparator is selected and its synchronization acquisition is completed, a non-memory type phase comparator resistant to disturbance is selected.

[0012]

The PLL circuit of the above publication uses memory type and non-memory type phase comparators separately.

However, since the memory type and non-memory type phase comparators have different output characteristics, if they are simply switched, the operation of the PLL circuit becomes unstable due to the high voltage difference between the outputs.

Therefore, the PLL disclosed in the above publication.
The circuit uses delay elements to match the characteristics of the non-memory type phase comparator with the characteristics of the memory type phase comparator, but this requires fine circuit adjustment such as gain adjustment. Is. Therefore, in the PLL circuit of the above publication, it is actually difficult to match the output characteristics of the memory type and non-memory type phase comparators, and the productivity is poor.

Further, the memory type phase comparator 1 should function as a frequency comparator because it has a wide phase comparison range as described above. However, as shown in FIG. 22, the frequency is the same and the phase is "π". Assuming reference signals R and R'which are different from each other, the output forms of the phase lead signal D and the phase delay signal U are different for the same fluctuation signal V. This means that even if the phase comparator 1 normally outputs the phase difference between the reference signal R and the fluctuation signal V, this output does not necessarily become the frequency comparison result.

Further, the PLL circuit using such a phase comparator 1 is fed back and synchronized so that the phase difference converges to a stable point. That is, the frequency f of the reference signal R
_When there is a difference between _r and the free running frequency (output frequency when the control voltage is “0”) f _{0 of} the VCO, the phase error δθ during synchronization is converted into the voltage δV. Further, since the voltage .DELTA.V moves the oscillation frequency of the VCO just delta] f, as shown in FIG. 20, the phase difference becomes _{δV = K θ δθ δf = K} f δV f r = f 0 + δf becomes stable point, the The PLL circuit is synchronized in this state. In the above equation, K _θ is a gain coefficient obtained by combining the phase comparator 1 and the LPF, and K _f is VC.
It is a gain coefficient of O.

The fact that the output signals U and D of the phase comparator 1 differ depending on the phases of the reference signals R and R'as described above means that the output results differ depending on the initial state. Even if the phase difference between the reference signal R and the fluctuation signal V is large, the memory-type phase comparator 1 forcibly pulls this in to the stable point, but in that case, the synchronization relationship is broken once before pulling in. Therefore, it took time to acquire the synchronization.

Further, although the synchronization acquisition of the PLL circuit using the phase comparator 1 like this also takes time, the PLL
In the case of the circuit, not only the phase comparator but also the LPF and the like are factors that determine the time required for the synchronization acquisition. For this reason, the PLL circuit is designed in consideration of the balance between responsiveness and stability. For example, when the rotation speed of the drive motor is controlled by the PLL circuit, the responsiveness of the mechanical system is slower than that of the electrical system, Since the drive motor and the drive mechanism have inertia, the feedback control of the PLL circuit may vibrate around the stable point and may not converge. In such a case, the PLL is sacrificed in response to prevent vibration.
Since the circuit is designed, the drive motor pickup will be reduced.

In order to solve the above-mentioned problems, it has been proposed to provide another feedback loop for the rotation speed of the drive motor, or to reverse the feedback control or brake it before the stable point. . However, this complicates the structure of the control system and reduces productivity and reliability.

[0020]

According to the first aspect of the present invention,
A signal output means for outputting a first reference signal and a second reference signal whose phases are different by "π" is provided, and a first signal comparison means for comparing the first reference signal and the fluctuation signal to detect a phase difference is provided. A second signal comparing means for detecting the phase difference by comparing the second reference signal and the fluctuation signal is provided, and the phase difference detected by the first signal comparing means and the second signal comparing means is “± π ”
Provided with a result determination means for determining whether or not it is within the range of
An output switching means for selectively outputting the phase difference in the range of ". +-.. pi." Is provided according to the result of this discrimination.

According to a second aspect of the present invention, in the first aspect of the invention, the first reference signal is a logic signal having a duty ratio of 50 (%), and the signal output means inverts the first reference signal by a knot circuit. Then, the second reference signal is generated.

According to a third aspect of the present invention, the signal output means for outputting the reference signal is provided, and the signal generation means for generating the second fluctuation signal whose phase is shifted by "π" using the fluctuation signal as the first fluctuation signal is provided. A first signal comparing means for comparing the reference signal with the first fluctuation signal to detect a phase difference, and a second signal comparing means for comparing the reference signal with the second fluctuation signal to detect a phase difference A result discriminating unit for discriminating whether or not the phase difference detected by the first signal comparing unit and the second signal comparing unit is within the range of “± π” is provided, and the range of “± π” is determined by the discriminating result. The output switching means for selectively outputting the phase difference of one of the two is provided.

The invention according to claim 4 is provided with a charge pump for converting the output signal of the phase comparator according to claim 1, 2 or 3 from digital to analog, and a loop filter for filtering the output signal of this charge pump. A voltage-controlled oscillator that generates an output signal of an oscillation frequency corresponding to the output voltage of the loop filter is provided, and the output signal of the voltage-controlled oscillator is divided by an even number and then output as a fluctuation signal to the phase comparator. A frequency divider is provided.

According to a fifth aspect of the present invention, a charge pump for converting the output signal of the phase comparator according to the first, second or third aspect from digital to analog is provided, and a loop filter for filtering the output signal of the charge pump is provided. A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the output voltage of the loop filter is provided, and the output signal of the voltage-controlled oscillator is divided by an odd number and then output as a fluctuation signal to the phase comparator. A frequency divider is provided and the output signal of the voltage controlled oscillator is used as the first output signal and the phase is "π".
Provided with a signal converting means for generating a second output signal shifted by only, when the phase comparator outputs a phase difference by the first reference signal, selectively outputs the first output signal, the phase comparator Is provided with an output selection means for selectively outputting the second output signal when the phase difference is output by the second reference signal.

According to a sixth aspect of the invention, a charge pump for converting the output signal of the phase comparator according to the first, second or third aspect from digital to analog is provided, and a loop filter for filtering the output signal of the charge pump is provided. A motor driver that outputs drive power corresponding to the output voltage of this loop filter is provided, and a drive motor that is driven by the drive power output by this motor driver is provided, and the rotation speed of this drive motor is detected to respond. The speed detecting means for outputting the fluctuation signal to the phase comparator is provided.

According to a seventh aspect of the present invention, there is provided signal output means for outputting a first reference signal and a second reference signal whose phases are different by "π", and the fluctuation signal and the first reference signal are compared with each other. A first phase comparator that outputs a phase difference is provided, and a second phase comparator that outputs a phase difference by comparing a fluctuation signal and a second reference signal is provided. And an output switching means for selecting one of the output signals of the charge pump and a charge pump for converting the output signal selected by the output switching means from digital to analog, and a loop filter for filtering the output signal of the charge pump. A voltage-controlled oscillator for generating an output signal of an oscillation frequency corresponding to the output voltage of the loop filter, and a fluctuation signal corresponding to the output signal of the voltage-controlled oscillator is supplied to the first phase comparator and the A signal feedback means for outputting to the second phase comparator and a selection control means for changing the selection of the output switching means when the output voltage of the loop filter exceeds a preset reference voltage "± Vs" range. Provided.

According to an eighth aspect of the present invention, a signal output means for outputting a first reference signal and a second reference signal whose phases are different from each other by "π" is provided, and the fluctuation signal and the first reference signal are compared with each other. A first phase comparator that outputs a phase difference is provided, and a second phase comparator that outputs a phase difference by comparing a fluctuation signal and a second reference signal is provided. And an output switching means for selecting one of the output signals of the charge pump and a charge pump for converting the output signal selected by the output switching means from digital to analog, and a loop filter for filtering the output signal of the charge pump. A motor driver that outputs drive power corresponding to the output voltage of the loop filter, and a drive motor that is driven by the drive power output by the motor driver. A speed detecting means for detecting the rotation speed and outputting a corresponding fluctuation signal to the first phase comparator and the second phase comparator is provided, and the output voltage of the loop filter is a reference voltage “± Selection control means is provided for changing the selection of the output switching means when the range of Vs "is exceeded.

[0028]

According to the first aspect of the present invention, when the signal output means outputs the first reference signal and the second reference signal whose phases are different from each other by "π", the first signal comparing means causes the first reference signal and the fluctuation signal to be output. And the second signal comparison means compares the second reference signal and the fluctuation signal to detect the phase difference, these phase differences are in the range of “± π”. The result discriminating unit discriminates whether or not the output is present, and the output discriminating unit selectively outputs the phase difference in the range of “± π” according to the discriminant result, so that the first reference signal and the second reference signal are The phase difference is detected depending on the phase closer to the fluctuation signal.

According to a second aspect of the present invention, the first reference signal is a logic signal having a duty ratio of 50 (%), and the signal output means inverts the first reference signal by the knot circuit to generate the second reference signal. By doing so, the second reference signal is simply generated from the first reference signal.

According to a third aspect of the present invention, the signal output means outputs the reference signal and the signal generating means generates the second fluctuation signal whose phase is shifted by "π" using the fluctuation signal as the first fluctuation signal. Since the first signal comparison means detects the phase difference by comparing the reference signal and the first fluctuation signal, the second signal comparison means detects the phase difference by comparing the reference signal and the second fluctuation signal, Whether or not these phase differences are within the range of “± π” is determined by the result determination means, and the output switching means selectively outputs the phase difference within the range of “± π” based on this determination result. The phase difference is detected depending on which of the first fluctuation signal and the second fluctuation signal is closer in phase to the reference signal.

According to a fourth aspect of the present invention, a charge pump converts the output signal of the phase comparator according to the first, second or third aspect from digital to analog, and the output signal is filtered by a loop filter to output the output voltage. When the voltage-controlled oscillator generates an output signal with an oscillation frequency corresponding to, the output signal of this voltage-controlled oscillator is divided by an even number and then output as a fluctuation signal to the phase comparator, so that synchronous acquisition is achieved. It is completed quickly due to the characteristics of the phase comparator.

According to a fifth aspect of the present invention, a charge pump converts the output signal of the phase comparator according to the first, second or third aspect from digital to analog, and the output signal is filtered by a loop filter to output the output voltage. When the voltage-controlled oscillator generates an output signal with an oscillation frequency corresponding to, the frequency-divider output signal is output as a fluctuation signal to the phase comparator after the frequency divider divides the frequency by an odd number. When the output signal of the voltage controlled oscillator is used as the first output signal to generate the second output signal whose phase is shifted by "π",
The output selection means selectively outputs the first output signal when the phase comparator outputs the phase difference by the first reference signal, and the phase comparator outputs the phase difference by the second reference signal. In some cases, by selectively outputting the second output signal, the synchronization acquisition is quickly completed due to the characteristics of the phase comparator.

According to a sixth aspect of the present invention, the charge pump converts the output signal of the phase comparator according to the first, second or third aspect from digital to analog, and the output signal is filtered by a loop filter to output the output voltage. When the drive motor is driven by this drive power, the speed detection means outputs a fluctuation signal corresponding to the rotation speed of the drive motor to the phase comparator. The synchronization acquisition is completed quickly due to the characteristics of the phase comparator.

According to a seventh aspect of the present invention, when the signal output means outputs the first reference signal and the second reference signal whose phases are different by "π", the first phase comparator causes the fluctuation signal and the first reference signal. Since the phase difference is output by comparing with, the second phase comparator outputs the phase difference by comparing the fluctuation signal and the second reference signal, and the first phase comparator and the second phase comparator When the output switching means selects one of the output signals, the charge pump converts the selected output signal from digital to analog, the loop filter filters this output signal, and the output signal of the oscillation frequency corresponding to this output voltage. Since the voltage-controlled oscillator is generated, the signal feedback means outputs a fluctuation signal corresponding to this output signal to the first phase comparator and the second phase comparator as a fluctuation signal, but the selection control means,
When the output voltage of the loop filter exceeds the range of the preset reference voltage "± Vs", the selection of the output switching means is changed, so that the proper phase comparator can be easily selected and the synchronous acquisition can be completed quickly. It

In the eighth aspect of the invention, when the signal output means outputs the first reference signal and the second reference signal whose phases are different from each other by "π", the first phase comparator causes the fluctuation signal and the first reference signal. Since the phase difference is output by comparing with, the second phase comparator outputs the phase difference by comparing the fluctuation signal and the second reference signal, and the first phase comparator and the second phase comparator When one of the output signals is selected by the output switching means, the charge pump converts the selected output signal from digital to analog, the loop filter filters the output signal, and the motor driver drives in response to the output voltage. When power is output and the drive motor is driven by this drive power, the speed detection means outputs a fluctuation signal corresponding to the rotation speed of the drive motor to the phase comparator. By force voltage to change the selection of the output switching means to exceed the range of a preset reference voltage "± Vs", captured synchronization proper phase comparator is selected simply is completed quickly.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. First, the phase comparator 17 of this embodiment
As shown in FIG. 1, it has input sections 18 and 19 for the reference signal R and the fluctuation signal V, and output sections 20 and 21 for the phase delay signal U and the phase lead signal D. The input section 18 of the reference signal R has a first phase comparator 2 which is a first signal comparing means.
2 and the phase shifter 23 are connected to each other, and the second phase comparator 2 which is the second signal comparing means is connected to the phase shifter 23.
4 are connected.

The phase shifter 23 outputs the second reference signal R2 by using the input reference signal R as the first reference signal R1 and shifting its phase by "π". Therefore, the reference clock (not shown) connected to the input unit 18 of the reference signal R and the phase shifter 23 cause the first reference signal R1 and the second reference signal R2 to differ in phase by "π". Signal output means for outputting is formed.

A first discriminator 25 is connected to the output section of the first phase comparator 22 for outputting the phase lag signal U1 and the phase lead signal D1 and the input section 18 of the first reference signal R1. The second discriminator 26 is connected to the output part of the phase delay signal U2 and the phase advance signal D2 of the second phase comparator 24 and the output part of the second reference signal R2 of the phase shifter 23. These discriminators 25 and 26 are respectively provided with a reference signal R.
If the input signals U and D exceed the range of ". +-.. pi." Based on 1 and R2, the discrimination signals Q1 and Q2 are output. Therefore, as a result discrimination means, the phase difference detected by the phase comparators 22 and 24 is detected. Determines whether is within the range of “± π”.

The phase comparators 22 and 24 output the phase delay signals U1 and U2 and the phase advance signals D1 and D2, and the discriminators 25 and 26 output the discrimination signals Q1 and Q2. An output switch 27, which is an output switching means, is connected, and the output switch 27 is connected to the output units 20 and 21 of the phase delay signal U and the phase advance signal D. The output switcher 27 selectively outputs one of the signals from the phase comparators 22 and 24 as the phase delay signal U and the phase advance signal D from the output units 20 and 21 according to the determination signals Q1 and Q2. Among the phase differences detected by the phase comparators 22 and 24, the phase difference in the range of “± π” is selectively output.

The output switch 27 is formed by an existing digital switching circuit such as a switching circuit and a multiplexer. In addition, the phase comparator 22,
24 is formed as a structure similar to the phase comparator 1 described above as a conventional example, and has the output characteristics shown in FIG. 20, respectively.

In such a configuration, the phase comparator 17
When the reference signal R and the fluctuation signal V are input to the input units 18 and 19 of the, the first phase comparator 22 compares the first reference signal R1 and the fluctuation signal V, and detects the phase difference between them. U1
And a phase lead signal D1 is output. Also, the reference signal R
Is shifted by “π” by the phase shifter 23 and converted into the second reference signal R, the second phase comparator 24
The second reference signal R2 is compared with the fluctuation signal V, and the phase difference is output as the phase delay signal U2 and the phase advance signal D2.

Then, the first discriminator 25 outputs the discrimination signal Q1 to the output switch 27 when the signals U1 and D1 which are the phase differences exceed the range of "± π", and the second discriminator 26 determines the position. When the signals U2 and D2, which are the phase difference, exceed the range of “± π”, the determination signal Q1 is output to the output switch 27. Then
When the discrimination signal Q2 is input, the output switching device 27 outputs the output signals U1 and D1 of the first phase comparator 22 as the phase delay signal U and the phase advance signal D from the output units 20 and 21, and discriminates them. When the signal Q1 is input, the output signals U2 and D2 of the second phase comparator 24 are output from the output units 20 and 21 as the phase delay signal U and the phase advance signal D.

Therefore, the phase comparator 17 of the present embodiment is
The two reference signals R1 and R2 whose phases are different by “π” are compared with the fluctuation signal V, and one of the phase differences in the range of “± π” is selectively output, so that the phase difference is small. Since the synchronization acquisition is performed by the combination, this synchronization acquisition can be completed quickly.

That is, the phase comparators 22 and 24 of the phase comparator 17 of the present embodiment each have one stable point as shown in FIG. 20, but the phases of the reference signals R1 and R2 are Since the difference is only "π", the phase comparator 17 of the present embodiment is different.
As a result, as shown in FIG. 2, it has two stable points separated by "π".

Therefore, when a PLL circuit (not shown) is formed by using the phase comparator 17 of this embodiment, this PL circuit is used.
Since the L circuit converges the phase difference to the closer one of the two stable points, the synchronization acquisition can be completed quickly. Since the output signals of the two phase comparators 22 and 24 switched by the phase comparator 17 of the present embodiment have the same output characteristics and are digital, the operation of the PLL circuit becomes unstable even if they are simply switched. There is no such thing.

In the phase comparator 17 of the present embodiment, it has been shown that the two phase comparators 22 and 24 in which the phase of the reference signal R differs by "π" are selectively switched. However, the present invention is not limited to this. The present invention is not limited to the above embodiment, and further, third and fourth phase comparators (not shown) in which the phase of the reference signal R differs by "π / 2" are provided, and these four phase comparators are compared. It is also possible to selectively switch the vessels. in this case,
Since the switching order of the four phase comparators is important, use an up-down counter, shift register, etc.
As shown in, it is desirable to switch sequentially in the order in which stable points continue.

Next, a second embodiment of the present invention will be described below with reference to FIGS. Regarding the phase comparator 28 shown in the present embodiment, the same parts as those of the phase comparator 17 described as the first embodiment are designated by the same names and reference numerals, and detailed description thereof will be omitted.

First, in the phase comparator 28 of this embodiment, as shown in FIG. 6, the reference signal R has a duty ratio of 50 (%).
Since it is a logical signal composed of a square wave, when it is inverted, it becomes a signal of the same waveform with a phase difference of "π".
As shown in FIG. 4, one knot circuit 29 is provided between the input unit 18 of the reference signal R and the second phase comparator 24. The knot circuit 29 and a reference clock (not shown) are connected to each other. Thus, signal output means for outputting the first reference signal R1 and the second reference signal R2 is formed.

Further, the first discriminator 30 which is the result discriminating means.
5A, as shown in FIG. 5A, an AND gate 31 that receives the phase delay signal U1 and the first reference signal R1, an inverter 32 that inverts the first reference signal R1, an output of this inverter 32 and a phase advance. It is formed by an AND gate 33 which receives the signal D1 as an input, and an OR gate 34 which receives the outputs of these AND gates 31 and 33 and outputs a discrimination signal Q1. As shown in FIG. 5B, the second discriminator 35, which is the result discriminating means, has the same structure as the first discriminator 30, but the signals thereof are U2, R2, D2 and Q2. Therefore, the determination signals Q1 and Q2 are expressed as Q1 = U1 * R1 + D1 * R2 Q2 = U2 * R2 + D2 * R1 (R2 = inversion R1) by the following logical expression.

Further, as shown in FIG. 4, the output switch 36, which is the output switching means, includes a switching circuit 37 interposed between the phase comparators 22 and 24 and the output units 20 and 21, and the discriminators 30 and 35. Low-active RS-connected to
And a flip-flop 38. This R
Since the S-flip-flop 38 generates the selection signal Q from the discrimination signals Q1 and Q2 and outputs it to the switching circuit 37, the switching circuit 37 outputs one of the phase comparators 22 and 24 according to the input selection signal Q. The output signals U and D are selectively output.

In such a configuration, as shown in FIG. 6, when the reference signal R and the fluctuation signal V are input to the input sections 18 and 19 of the phase comparator 28, the first phase comparator 22 becomes
The first reference signal R1 and the fluctuation signal V are compared, and the phase difference is output as the phase delay signal U1 and the phase advance signal D1. Further, since the reference signal R is inverted by the knot circuit 29 and converted into the second reference signal R, the second phase comparator 2
Reference numeral 4 compares the second reference signal R2 with the fluctuation signal V and outputs the phase difference as a phase delay signal U2 and a phase advance signal D2.

Then, the first discriminator 30 outputs the discrimination signal Q1 to the output switching device 36 when the signals U1 and D1 which are the phase differences exceed the range of "± π", and the second discriminator 35 judges the position. When the signals U2 and D2, which are the phase difference, exceed the range of “± π”, the determination signal Q1 is output to the output switch 36.

The first discriminator 30 will be described in more detail as an example. As shown in FIG. 6A, even if the phase delay signal U1 is in the range of “± π” when the first reference signal R1 is “L”, as shown in FIG. One reference signal R
If 1 is output up to the time of "H", it is not within the range of "± π". Similarly, the phase lead signal D1 is
As shown in FIG. 6C, when the first reference signal R1 is “L” and is in the range of “± π”, the first reference signal R1 is “L” as shown in FIG. 6D. If it is output up to the time of "H", it will not be in the range of "± π".

Therefore, "Q1 = U1.R1 + D1.R"
By outputting the discrimination signal Q1 as "2", the discrimination signal Q1 is output when one of the phase delay signal U1 and the phase advance signal D1 exceeds the range of "± π".

Since the output signals of the AND gates 31 and 33 have a relationship of = U1 · R1 = D1 · R2, the phase difference between the first reference signal R1 and the fluctuation signal V is in the range of “± π”. "= R1""in case
= R2 ", and the determination signal Q1 is" Q1 = + = R1.
+ R2 = 1 ”. That is, the determination signal Q1 is output as“ H ”when the phase difference is not within the range of“ ± π ”,
When the phase difference is in the range of "± π", it is output as "L".

When the discrimination signals Q1 and Q2 are output from the discriminators 30 and 35 to the output switch 36 as described above, when the discrimination signal Q1 is "H" and the discrimination signal Q2 is "L", this is The input RS-flip-flop 38 outputs the selection signal Q of "H" to the switching circuit 37, so that the switching circuit 37 to which the selection signal Q of "H" is input outputs the first phase comparator 22. Signal U
1, D1 are selectively output from the output units 20 and 21 as the phase delay signal U and the phase advance signal D.

Similarly, when the discrimination signal Q1 is "L" and the discrimination signal Q2 is "H", the RS-flip-flop 38 to which this is inputted outputs the selection signal Q of "L" to the switching circuit 37. The switching circuit 37 to which the selection signal Q of “L” is input causes the second phase comparator 24
The output signals U2 and D2 are selectively output from the output units 20 and 21 as the phase delay signal U and the phase advance signal D.

Since the RS-flip-flop 38 is a set / reset type, even if one of the determination signals Q1 and Q2 is continuously input, the output signal "H, L" of the selection signal Q is output.
Does not switch.

As described above, the phase comparator 28 of the present embodiment.
Are two reference signals R1 and R whose phases differ by "π".
2 and the fluctuation signal V are compared, and “± π” of the phase difference is compared.
Since the one in the range is selectively output, it is possible to quickly complete the synchronization acquisition with a combination having a small phase difference. Therefore, using the phase comparator 28 of this embodiment,
When the L circuit (not shown) is formed, the PLL circuit converges the phase difference to the closer one of the two stable points, so that the synchronization acquisition can be completed quickly.

Moreover, in the phase comparator 28 of this embodiment,
Since the reference signal R is a logic signal composed of a square wave with a duty ratio of 50 (%), this reference signal R is referred to as the first reference signal R.
If the number is 1, the second reference signal R2 having a phase difference of "π" can be generated by inverting the value. Therefore, the one knot circuit 29 generates the second reference signal R2 from the first reference signal R1, and the phase comparator 17 has a simple structure and good productivity.

In the phase comparator 28 of this embodiment, the discriminators 30 and 35 output the discrimination signals Q1 and Q2 by the logic circuit, but in reality, the discrimination signal Q is delayed due to the delay of the circuit operation.
There is a possibility that an "L" pulse may be erroneously output to 1 and Q2. In such a case, if capacitors (not shown) are provided at the outputs of the discriminators 30 and 35, the discrimination signals Q1 and Q
It is possible to prevent the "L" pulse from being erroneously output to 2.

Further, in the phase comparator 28 of the present embodiment, two AND gates 31 and 33, one inverter 32 and one OR gate 34 are used to: Q1 = U1.R1 + D1.R2 Q2 = U2.R2 + D2.R1 Although the discriminators 30 and 35 for realizing the above logical expression are formed as the result discriminating means, the present invention is not limited to the above embodiment. For example, another logic circuit that realizes a similar logical expression, or a circuit that sequentially detects the edges of the first reference signal R1, the second reference signal R2, the phase delay signal U, and the phase advance signal D to determine the phase difference. , Phase delay signal U and phase advance signal D
The result discriminating means can also be realized by a circuit or the like that discriminates that the phase difference exceeds the range of “± π” from the output time of the.

Further, in the phase comparator 28 of the present embodiment, the discriminators 30 and 35 have the inverter 32, but the knot circuit 29 provided in the input section 18 can be used instead. . In this case, like the phase comparator 39 shown as the third embodiment in FIG. 7, the discrimination circuits 40 and 41 which are the result discrimination means of the phase comparator 39 are provided with two AND gates 31 and 33 and one OR gate. And the knot circuit 29 provided in the input section 18.
Are connected to the AND gate 33.

Next, a fourth embodiment of the present invention will be described below with reference to FIG. First, the PLL circuit 4 of this embodiment
2 has the phase comparator 28 described above as the second embodiment of the present invention. The output section 20 of the phase comparator 28,
A charge pump 43 is connected to the charge pump 21, and the charge pump 43 has a loop filter LPF4.
4 are connected. A motor driver 45 is connected to the LPF 44, and a drive motor 46 is connected to the motor driver 45. This drive motor 46
A rotation angle sensor 47, which is a speed detecting means for detecting the rotation speed, is connected to the rotation angle sensor 47.
Is the input portion 19 of the fluctuation signal V of the phase comparator 28.
It is connected to the. The rotation angle sensor 47 is, for example, an FG (Frequency Generator) or a rotary encoder (both not shown).

In such a configuration, the PL of this embodiment is
The L circuit 42 rotationally drives the drive motor 46 at a rotation speed synchronized with the frequency of the reference signal R.

More specifically, when the charge pump 43 converts the output signals U and D of the phase comparator 28 from digital to analog, the LPF 44 filters this output signal. Next, since the motor driver 45 outputs drive power corresponding to this output voltage, the drive motor 46 is rotationally driven by this drive power. At this time, since the rotation angle sensor 47 feeds back the fluctuation signal corresponding to the rotation speed of the drive motor 46 to the phase comparator 28 as the fluctuation signal V, the phase comparator 28 outputs the fluctuation signal V and the reference signal R. To the charge pump 43 as the phase delay signal U and the phase advance signal D.

As described above, the PLL circuit 42 feedback-controls the drive motor 46 to the rotation speed synchronized with the frequency of the reference signal R to drive the rotation, but the phase comparator 28
, As described above, completes the synchronization acquisition quickly.
Even with the L circuit 42, the rotation speed of the drive motor 46 can be quickly stabilized.

When the rotation speed of the drive motor 46 is controlled by such a PLL circuit 42, the mechanical system is slower in response than the electric system, and the drive motor 46 and the drive mechanism (not shown) have inertia. In order to satisfactorily control the rotation speed, it is preferable to brake the control before it converges on the stable point. The phase comparator 28 of the PLL circuit 42 of the present embodiment switches the two stable points as described above to quickly complete the synchronization acquisition, but such stable point switching brakes the control being executed. Therefore, the rotation speed of the drive motor 46 can be quickly converged to the stable point, and the feedback control of the PLL circuit 42 is prevented from oscillating around the stable point.

Since the change in the rotation speed of the drive motor 46 causes vibration and noise and also shortens the life of the mechanical system, it is extremely difficult to quickly stabilize the rotation speed of the drive motor 46 as described above. preferable. The PL of this embodiment is
When the phase difference between the reference signal R and the fluctuation signal V falls within the range of “± π”, the L circuit 42 functions thereafter similarly to the conventional PLL circuit.

Next, a fifth embodiment of the present invention will be described below with reference to FIGS. 9 to 11. P shown in this embodiment
Regarding the LL circuit 48 and the phase comparator 49, the above-mentioned PL
The same parts as those of the L circuit 42 and the phase comparator 28 have the same names and reference numerals, and detailed description thereof will be omitted.

First, in the PLL circuit 48 of this embodiment, as shown in FIG. 9, the phase comparator 49 and the charge pump 4 are provided.
3, LPF 44, motor driver 45, drive motor 46
Are sequentially connected, and the rotation angle sensor 47 connected to the drive motor 46 is feedback-connected to the phase comparator 49. Further, the output of the LPF 44 is also feedback-connected to the phase comparator 49.

As shown in FIG. 10, the phase comparator 49 also has an input section 50 for receiving the output voltage of the LPF 44 as the discrimination signal Q in addition to the input sections 18, 19 for the signals R and V. . The input section 50 is connected to a voltage comparison circuit 52 which is a selection control means of the output switch 51, and the voltage comparison circuit 52 is connected to a switching circuit 37 which is an output switch means of the output switch 51. There is.

The voltage comparison circuit 52 outputs the selection signal Q to the switching circuit 37 when the output voltage of the LPF 44 exceeds the range of the preset reference voltage "± Vs". Therefore, the phase comparator 49 of this embodiment is not provided with the discriminators 30 and 35.

In such a configuration, the PL of this embodiment is
The L circuit 48 rotationally drives the drive motor 46 at a rotation speed synchronized with the frequency of the reference signal R. At this time, the phase comparator 4
9 selects the phase comparators 22 and 24 that output the phase delay signal U and the phase advance signal D, and this selection is performed by the LPF 4
It controls according to the output voltage of 4. That is, as shown in FIG. 11, since the relationship between the signal phase difference of the phase comparators 22 and 24 and the output voltage is linear, the output voltage is the reference voltage “± V.
If it is in the range of "s", the signal phase difference is also in the range of "± π".

Therefore, in the PLL circuit 48 of this embodiment,
When the output voltage of the LPF 44 is in the range of the reference voltage “± Vs”, the phase difference between the fluctuation signal V and the reference signal R is also “± π”.
, The phase comparator 49 determines that the voltage comparator circuit 5
2 continues to select the switching circuit 37, and LP
When the output voltage of F44 exceeds the range of the reference voltage “± Vs”, it is determined that the phase difference between the fluctuation signal V and the reference signal R exceeds the range of “± π”, and the phase comparator 49 causes the voltage comparison circuit 52 to detect the phase difference. The selection of the switching circuit 37 is changed.

Therefore, the PLL circuit 48 of the present embodiment is
Similar to the PLL circuit 42 described above as the third embodiment,
Since the phase comparator 49 quickly completes the synchronization acquisition, the rotation speed of the drive motor 46 can be quickly stabilized. Moreover, since the switching operation of the phase comparator 49 is performed by the output voltage of the LPF 44, the structure is simple, and the size and weight can be reduced and the productivity can be improved.

In this embodiment, the PLL circuit 4 for controlling the rotation of the drive motor 46 has a structure in which the phase comparator 49 selects the output signals U and D based on the output voltage of the LPF 44.
However, the present invention is not limited to the above embodiment, and the structure in which the phase comparator 49 selects the output signals U and D based on the output voltage of the LPF 44 as described above is provided. It can be provided in a general PLL circuit (not shown) having a voltage controlled oscillator. In such a PLL circuit, the fluctuation signal corresponding to the output signal of the voltage controlled oscillator is fed to the phase comparator 4 by the signal feedback means such as a frequency divider.
9 is output.

Further, the phase comparators 28, 39, 4 described above
9 shows that the reference signal R is used as the first reference signal R1 and is inverted by the knot circuit 29 to generate the second reference signal R2, but the present invention is not limited to the above embodiment. . As shown as a fourth embodiment in FIG. 12, the second fluctuation signal in which the fluctuation signal V is set as the first fluctuation signal V1 and is inverted by the knot circuit 29 serving as a signal generating means to have a phase difference of "π". A phase comparator 53 that produces V2 is also possible.

In this case, the phase comparator 53 functions in the same manner as the phase comparators 28, 39 and 49 described above.
This can be used for the PLL circuits 42 and 48 described above, and can also be used for the PLL circuit (not shown) having the VCO without the drive motor 46. In order to invert the fluctuation signal V to generate the second fluctuation signal V2 as described above, it is necessary to set the duty ratio of the fluctuation signal V to 50 (%).

Next, an eighth embodiment of the present invention will be described below with reference to FIGS. 13 and 14. With respect to the PLL circuit 54 shown in this embodiment, the same parts as those of the PLL circuit 42 described above are denoted by the same names and reference numerals, and detailed description thereof will be omitted.

First, the PLL circuit 54 of this embodiment is shown in FIG.
As shown in FIG. 3, the LPF 44 has a voltage controlled oscillator V
The CO 55 is connected, and the frequency divider 56 connected to the VCO 55 is connected to the input section 19 of the fluctuation signal V of the phase comparator 28. Therefore, the motor driver 4
5, the drive motor 46, and the rotation angle sensor 47 are not provided. The VCO 55 generates an output signal O having an oscillation frequency corresponding to the output voltage of the LPF 44,
The frequency divider 56 is set to divide the output signal O of the VCO 55 by an even number and then output it to the phase comparator 28 as a fluctuation signal.

In such a configuration, the phase comparator 28
When the charge pump 43 converts the output signals U and D of the above from digital into analog and the LPF 44 filters, the VCO 55 generates the output signal O of the oscillation frequency corresponding to this output voltage and outputs it externally. Then this VC
Since the frequency divider 56 divides the output signal O of O55 by an even number and feeds it back to the phase comparator 28 as the fluctuation signal V, the phase comparator 28 calculates the phase difference between the fluctuation signal V and the reference signal R. The phase delayed signal U and the phase advanced signal D are output.

As described above, the PLL circuit 54 outputs the frequency signal synchronized with the reference signal R, but the phase comparator 28 quickly completes the synchronization acquisition as described above.
The PLL circuit 54 can also quickly complete the synchronization acquisition.

In the PLL circuit 54 of this embodiment, V
Since the frequency divider 56 divides the output signal O of the CO 55 by an even number and uses it as the fluctuation signal V of the phase comparator 28, as shown in FIG. 14, the phase comparator 28 uses the first reference signal R1 and the second reference signal R1. The output signal O is the same regardless of whether the output signal U or D is generated by the signal R2. Therefore, since the switching operation of the phase comparator 28 does not affect the output signal O of the PLL circuit 54, the operation of the PLL circuit 54 is stable and the output signal O
Need not be corrected.

Next, a ninth embodiment will be described with reference to FIGS.
It will be described below based on. The PL shown in this embodiment is
Regarding the L circuit 57 and the phase comparator 58, the above-mentioned PLL
The same parts as those of the circuit 54 and the phase comparator 28 have the same names and reference numerals, and detailed description thereof will be omitted.

First, in the PLL circuit 57 of this embodiment, as shown in FIG. 15, the frequency divider 59 frequency-divides the output signal O of the VCO 55 by an odd number and outputs it to the phase comparator 58 as a fluctuation signal. Is set. The output part of the VCO 55 is divided into two parts, one of which is an inverter 6 serving as a signal converting means.
Since 0 is provided, the inverter 60 uses the output signal O of the VCO 55 as the first output signal O1 to generate the second output signal O2 whose phase is shifted by "π".

A switching circuit 61 which is an output selecting means for selectively outputting one of these output signals O1 and O2.
The switching circuit 61 is connected to the output section 62 of the selection signal Q provided in the phase comparator 58. Therefore, the switching circuit 61
When the phase comparator 58 outputs the phase difference according to the first reference signal R1, the phase comparator 58 selectively outputs the first output signal O1, and the phase comparator 58 receives the phase difference according to the second reference signal R2. Is output, the second output signal O2 is selectively output.

In such a configuration, the phase comparator 58
When the charge pump 43 converts the output signals U and D from the digital signal into the analog signal and the LPF 44 filters the signal, the VCO 55 generates the output signal O having the oscillation frequency corresponding to the output voltage. Then, the frequency divider 59 divides the output signal O of the VCO 55 by an odd number, and then the phase comparator 5
The phase comparator 58 outputs the phase difference between the fluctuation signal V and the reference signal R as the phase lag signal U and the phase advance signal D because the phase comparator 58 outputs the fluctuation signal V as feedback signal.

However, the PLL circuit 57 of this embodiment is
Since the frequency divider 59 divides the output signal O of the CO 55 by an odd number to obtain the fluctuation signal V of the phase comparator 58, as shown in FIG. 16, when the phase comparator 58 uses the first reference signal R1. And the case where the second reference signal R2 is used, the phase of the output signal O is different by “π”. Therefore, the output signal O is used as the first reference signal O1 to generate the second reference signal O2 having a phase difference of "π" by the inverter 60, and one of the reference signals O1 and O2 is switched by the switching circuit 61.
Selectively outputs in response to the switching operation of the phase comparator 58, so that the output signal O is always the same.

More specifically, the phase comparator 58 selects one of the first reference signal R1 and the second reference signal R2 for signal output and outputs the selection signal Q of "H" or "L". Therefore, the switching circuit 61 selectively outputs the first output signal O1 when the selection signal Q is "H", and selectively outputs the second output signal O2 when the selection signal Q is "L". .

In the PLL circuits 54 and 57 described above, the phase comparators 28 and 58 have the structure of the second embodiment, but the present invention is not limited to the above-mentioned embodiment, and the above description is given here. It is also possible to provide the phase comparators 17, 39 and 49 described above.

In addition, the phase comparators 17, 28 and 3 described above
Since the output characteristics of the reference numerals 9, 49, and 58 are the same as those of a general memory type phase comparator, they can be treated as a memory type phase comparator. For example, the phase comparator of the present embodiment is combined with the phase comparator (not shown) filed by the applicant as Japanese Patent Application No. 6-209724, and in the initial state, the phase comparator of the present embodiment performs synchronization acquisition. It is possible to complete quickly, and thereafter, maintain good synchronization acquisition by the phase comparator of the above application.

[0093]

According to the first aspect of the present invention, the signal output means for outputting the first reference signal and the second reference signal whose phases are different by "π" is provided, and the first reference signal and the fluctuation signal are compared. A first signal comparing means for detecting a phase difference, and a second signal comparing means for detecting a phase difference by comparing a second reference signal with a fluctuation signal, and a first signal comparing means and a second signal comparing means. The result discriminating means for discriminating whether or not the phase difference detected by the means is within the range of “± π” is provided.
By providing the output switching means for selectively outputting the phase difference in the range of π ″, the phase difference is detected by the one of the first reference signal and the second reference signal that is closer in phase to the fluctuation signal. Therefore, when the PLL circuit is formed, the synchronization acquisition can be completed quickly.

According to the second aspect of the present invention, the first reference signal is a logic signal having a duty ratio of 50 (%), and the signal output means inverts the first reference signal by the knot circuit to generate the second reference signal. By doing so, it is possible to easily generate the second reference signal from the first reference signal with a simple structure,
It can contribute to miniaturization and improvement of productivity.

According to the third aspect of the invention, the signal output means for outputting the reference signal is provided, and the signal generation means for generating the second fluctuation signal in which the fluctuation signal is used as the first fluctuation signal and the phase is shifted by "π" is provided. A first signal comparing means for comparing the reference signal with the first fluctuation signal to detect a phase difference, and a second signal comparing means for comparing the reference signal with the second fluctuation signal to detect a phase difference The result discriminating means for discriminating whether or not the phase difference detected by the first signal comparing means and the second signal comparing means is within the range of “± π” is provided.
By providing the output switching means that selectively outputs the phase difference in the range of π ″, the phase difference is detected by the one of the first fluctuation signal and the second fluctuation signal that is closer in phase to the reference signal. Therefore, when the PLL circuit is formed, the synchronization acquisition can be completed quickly.

The invention according to claim 4 is provided with a charge pump for converting the output signal of the phase comparator according to claim 1, 2 or 3 from digital to analog, and a loop filter for filtering the output signal of this charge pump. A voltage-controlled oscillator that generates an output signal with an oscillation frequency corresponding to the output voltage of this loop filter is provided, and the output signal of this voltage-controlled oscillator is divided by an even number before being output as a fluctuation signal to the phase comparator. Since the frequency divider is provided, the synchronous acquisition can be completed quickly due to the characteristics of the phase comparator, and the switching operation of the phase comparator does not affect the output signal of the PLL circuit, so that no special correction means is required. A PLL circuit with a stable output signal can be obtained.

According to a fifth aspect of the present invention, a charge pump for converting the output signal of the phase comparator according to the first, second or third aspect from digital to analog is provided, and a loop filter for filtering the output signal of the charge pump is provided. Providing a voltage controlled oscillator that outputs a signal with an oscillation frequency corresponding to the output voltage of this loop filter, divides the output signal of this voltage controlled oscillator by an odd number, and then outputs it as a fluctuation signal to the phase comparator. And a signal converting means for generating a second output signal whose phase is shifted by "π" by using the output signal of the voltage controlled oscillator as the first output signal, and the phase comparator outputs the phase difference by the first reference signal. If the phase comparator outputs the phase difference based on the second reference signal, the second output signal is selectively output. By providing the output selection means, the synchronous acquisition can be completed quickly by the characteristics of the phase comparator, and the phase of the output signal of the voltage controlled oscillator changes due to the switching operation of the phase comparator. Since the output signal does not change, a PLL circuit with a stable output signal can be obtained.

According to a sixth aspect of the present invention, a charge pump for converting the output signal of the phase comparator according to the first, second or third aspect from digital to analog is provided, and a loop filter for filtering the output signal of the charge pump is provided. A motor driver that outputs drive power corresponding to the output voltage of this loop filter is provided, and a drive motor that is driven by the drive power output by this motor driver is provided, and the rotation speed of this drive motor is detected to respond. Since the speed detection means for outputting the fluctuation signal to the phase comparator is provided, the synchronous acquisition can be completed quickly by the characteristics of the phase comparator, so that the rotation speed of the drive motor can be stabilized quickly. .

According to a seventh aspect of the present invention, there is provided signal output means for outputting a first reference signal and a second reference signal whose phases are different by "π", and the fluctuation signal and the first reference signal are compared with each other. A first phase comparator that outputs a phase difference is provided, and a second phase comparator that compares the fluctuation signal and the second reference signal and outputs a phase difference is provided. These first phase comparator and second phase comparator And an output switching means for selecting one of the output signals, a charge pump for converting the output signal selected by the output switching means from digital to analog, and a loop filter for filtering the output signal of the charge pump. A voltage controlled oscillator that generates an output signal with an oscillation frequency corresponding to the output voltage of this loop filter is provided, and the fluctuation signal corresponding to the output signal of this voltage controlled oscillator is fed to the first phase comparator and the second phase ratio. If the output voltage of the loop filter is higher than a preset reference voltage, the output switching means selects the first phase comparator, and the output voltage of the loop filter is preset. When the voltage is lower than the reference voltage, the output switching means is provided with the selection control means for selecting the second phase comparator, so that the synchronous acquisition can be completed quickly by the characteristics of the phase comparator, and the switching operation of the phase comparator. Is performed by the output voltage of the loop filter, the structure can be simplified.

According to an eighth aspect of the present invention, there is provided signal output means for outputting a first reference signal and a second reference signal whose phases are different by "π", and the fluctuation signal and the first reference signal are compared with each other. A first phase comparator that outputs a phase difference is provided, and a second phase comparator that compares the fluctuation signal and the second reference signal and outputs a phase difference is provided. These first phase comparator and second phase comparator And an output switching means for selecting one of the output signals, a charge pump for converting the output signal selected by the output switching means from digital to analog, and a loop filter for filtering the output signal of the charge pump. A motor driver that outputs drive power corresponding to the output voltage of the loop filter is provided, and a drive motor that is driven by the drive power output by the motor driver is provided. Providing speed detection means for detecting the rolling speed and outputting the corresponding fluctuation signal to the first phase comparator and the second phase comparator, and switching the output when the output voltage of the loop filter is higher than a preset reference voltage. Means for selecting the first phase comparator, and when the output voltage of the loop filter is lower than the preset reference voltage, the output switching means is provided with the selection control means for selecting the second phase comparator, so that the synchronous capture Can be completed quickly according to the characteristics of the phase comparator, the rotation speed of the drive motor can be stabilized quickly, and the switching operation of the phase comparator is performed by the output voltage of the loop filter, simplifying the structure. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase comparator according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing an output characteristic of a phase comparator.

FIG. 3 is a characteristic diagram showing an output characteristic of a phase comparator of a modified example.

FIG. 4 is a block diagram showing a phase comparator of a second embodiment.

FIG. 5 is a block diagram showing a first discriminator and a second discriminator that are result discriminating means.

FIG. 6 is a time chart showing the relationship of various signals of the phase comparator.

FIG. 7 is a block diagram showing a phase comparator of a third embodiment.

FIG. 8 is a block diagram showing a PLL circuit according to a fourth embodiment.

FIG. 9 is a block diagram showing a PLL circuit of a fifth embodiment.

FIG. 10 is a block diagram showing a phase comparator of a sixth embodiment.

FIG. 11 is a block diagram showing an output characteristic of a phase comparator.

FIG. 12 is a block diagram showing a phase comparator of a seventh embodiment.

FIG. 13 is a block diagram showing a PLL circuit of an eighth embodiment.

FIG. 14 is a time chart showing a relationship between a reference signal R and an output signal O.

FIG. 15 is a block diagram showing a PLL circuit according to a ninth embodiment.

16 is a time chart showing the relationship between the reference signal R and the output signal O. FIG.

FIG. 17 is a circuit diagram showing a conventional phase comparator.

FIG. 18 is a time chart showing the relationship of various signals of the phase comparator.

FIG. 19 is a block diagram showing a state in which a charge pump and an LPF that is a loop filter are connected to the phase comparator.

FIG. 20 is a characteristic diagram showing the output characteristic of the phase comparator.

FIG. 21 is a time chart showing the relationship of various signals of the phase comparator.

FIG. 22 is a time chart showing the relationship of various signals of the phase comparator.

[Explanation of symbols]

17, 28, 39, 49, 53, 58 Phase comparator 22 First signal comparing means 24 Second signal comparing means 25, 26, 30, 35, 40, 41 Result judging means 27, 36, 37 Output switching means 29 Knots circuit,
Signal generation means 42, 48, 54, 57 PLL circuit 43 Charge pump 44 Loop filter 45 Motor driver 46 Drive motor 47 Speed detection means 52 Selection control means 55 Voltage controlled oscillator 56, 59 Frequency divider 60 Signal conversion means 61 Output selection means

Claims (8)

[Claims] 1. A signal output means for outputting a first reference signal and a second reference signal whose phases are different from each other by “π”, and a first for detecting a phase difference by comparing the first reference signal and the fluctuation signal. The signal comparing means, the second signal comparing means for detecting the phase difference by comparing the second reference signal and the fluctuation signal, and the phase difference detected by the first signal comparing means and the second signal comparing means are “ ±
a result discriminating means for discriminating whether or not it is within the range of π ",
A phase comparator comprising: output switching means for selectively outputting the phase difference in the range of "± π" according to the result of this determination. 2. The duty ratio of the first reference signal is 50 (%).
2. The phase comparator according to claim 1, wherein the signal output means inverts the first reference signal by a knot circuit to generate the second reference signal. 3. A signal output means for outputting a reference signal, a signal generating means for generating a second fluctuation signal whose phase is shifted by “π” using the fluctuation signal as a first fluctuation signal, a reference signal and a first fluctuation signal. And a first signal comparison unit that detects a phase difference, a second signal comparison unit that compares a reference signal and a second fluctuation signal to detect a phase difference, the first signal comparison unit, and the first signal comparison unit. The phase difference detected by the two-signal comparison means is "± π"
The phase comparator is characterized by having a result discriminating means for discriminating whether or not it is within the range and an output switching means for selectively outputting the phase difference in the range of "± π" based on the discrimination result. . 4. A phase comparator according to claim 1, 2 or 3, a charge pump for converting an output signal of the phase comparator from digital to analog, and a loop filter for filtering an output signal of the charge pump. A voltage-controlled oscillator that generates an output signal with an oscillation frequency corresponding to the output voltage of this loop filter, and a frequency divider that divides the output signal of this voltage-controlled oscillator by an even number and then outputs it as a fluctuation signal to the phase comparator. P characterized by having
LL circuit. 5. The phase comparator according to claim 1, 2 or 3, a charge pump for converting an output signal of the phase comparator from digital to analog, and a loop filter for filtering an output signal of the charge pump. A voltage-controlled oscillator that outputs a signal having an oscillation frequency corresponding to the output voltage of the loop filter; and a frequency divider that divides the output signal of the voltage-controlled oscillator by an odd number and then outputs it as a fluctuation signal to the phase comparator. , A signal converting means for generating a second output signal whose phase is shifted by "π" using the output signal of the voltage controlled oscillator as a first output signal, and the phase comparator outputs a phase difference according to a first reference signal. Output selection that selectively outputs the first output signal when the phase comparator outputs the phase difference based on the second reference signal. PLL circuit, characterized in that it comprises a means. 6. The phase comparator according to claim 1, 2, or 3, a charge pump for converting an output signal of the phase comparator from digital to analog, and a loop filter for filtering the output signal of the charge pump. A motor driver that outputs drive power corresponding to the output voltage of this loop filter, a drive motor that is driven by the drive power that this motor driver outputs, and the rotation speed of this drive motor are detected to generate a corresponding fluctuation signal. P having a speed detecting means for outputting to the phase comparator.
LL circuit. 7. A signal output means for outputting a first reference signal and a second reference signal whose phases are different from each other by “π”, and a first for outputting a phase difference by comparing the fluctuation signal and the first reference signal. A phase comparator, a second phase comparator that compares the fluctuation signal and the second reference signal and outputs a phase difference, and selects one of the output signals of the first phase comparator and the second phase comparator. Output switching means, a charge pump for converting the output signal selected by the output switching means from digital to analog, a loop filter for filtering the output signal of the charge pump, and an oscillation frequency corresponding to the output voltage of the loop filter. A voltage-controlled oscillator that generates an output signal of the voltage-controlled oscillator, a signal feedback unit that outputs a fluctuation signal corresponding to the output signal of the voltage-controlled oscillator to the first phase comparator and the second phase comparator, and PLL circuit, characterized in that it comprises a selection control means and the output voltage of the loop filter exceeds the range of a preset reference voltage "± Vs" to change the selection of the output switching means. 8. A signal output means for outputting a first reference signal and a second reference signal whose phases are different by “π”, and a first for outputting a phase difference by comparing the fluctuation signal and the first reference signal. A phase comparator, a second phase comparator that compares the fluctuation signal and the second reference signal and outputs a phase difference, and selects one of the output signals of the first phase comparator and the second phase comparator. Output switching means, a charge pump for converting the output signal selected by the output switching means from digital to analog, a loop filter for filtering the output signal of the charge pump, and a drive corresponding to the output voltage of the loop filter. A motor driver that outputs electric power; a drive motor that is driven by the drive electric power that this motor driver outputs;
Speed detection means for detecting the rotation speed of the drive motor and outputting a corresponding fluctuation signal to the first phase comparator and the second phase comparator, and a reference in which the output voltage of the loop filter is preset. A PLL circuit having a selection control means for changing the selection of the output switching means when the voltage exceeds a range of "± Vs".