JPH08139292A - Thin film capacitor and semiconductor memory - Google Patents

Abstract

PURPOSE: To provide a thin film capacitor in which a temperature range in which a dielectric film indicates ferroelectricity is large and the value of a residual polarization is sufficiently large in practice. CONSTITUTION: A thin film capacitor comprises a conductive substrate 5 made of a conductive material having a crystalline structure in which a front surface is the surface (001) of a tetragonal crystal, a dielectric film 3 made of (Ba0.85 Sr0.15 )TiO3 (tetragonal crystal) having a perovskite crystalline structure formed on the substrate 5, and an upper electrode 4 formed on the film 3. The original Curie temperature of the dielectric material is 150 deg.C or lower, and the original lattice constant ad of the dielectric material represented by the a axis length of the perovskite structure and the original lattice constant as of the conductive material represented by by the a axis length of the tetragonal crystal structure satisfy the relation formula of 1.002<=ad /as <=1.015.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor provided with a dielectric film made of a dielectric material having a perovskite type crystal structure or the like, and a semiconductor memory device using the same.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device (ferroelectric memory) using a ferroelectric thin film for a capacitor of a memory cell has been developed, and some have already been put to practical use.
Ferroelectric memory is non-volatile, and the stored contents are not lost even after the power is turned off. Moreover, when the ferroelectric thin film is thin, reversal of remanent polarization is fast, and it is as good as DRAM (volatile memory). It has features such as high-speed writing and reading. Further, since one memory cell can be formed with one transistor and one capacitor, it is suitable for large capacity.

Recently, a technique for operating a ferroelectric memory as a DRAM has also been studied. It does not invert the remanent polarization of the ferroelectric thin film during normal operation and uses it like a capacitor of a DRAM memory cell, and utilizes the remanent polarization of the ferroelectric thin film only before turning off the power of the device. However, it is operated as a non-volatile memory. This technique is an effective method that can avoid the fatigue of the ferroelectric thin film, which is considered to be the biggest problem of the ferroelectric memory, that is, the phenomenon that the ferroelectric thin film deteriorates with repeated polarization inversion.

Here, a ferroelectric thin film suitable for a ferroelectric memory is required to have a large remanent polarization, a small temperature dependence of the remanent polarization, and a small deterioration due to repeated polarization inversion. In addition, DR of ferroelectric memory
In addition to these, when the AM operation is performed, it is necessary that the leak current is small.

At present, lead zirconate titanate (PZT) having a perovskite type crystal structure is generally used as a dielectric material for the above-mentioned ferroelectric thin film. PZT is a solid solution of lead zirconate (PbZrO ₃ ) and lead titanate (PbTiO ₃ ), but a solid solution having a molar ratio of about 1: 1 has a large remanent polarization, and polarization reversal is possible even in a low electric field. Yes, and considered to be particularly good. Further, PZT has a high transition temperature (Curie temperature) of about 300 ° C. between the ferroelectric phase and the paraelectric phase, so that the stored contents are in a temperature range of about 120 ° C. or less where a normal electronic circuit is used. There is little concern about losing heat.

However, it is known that it is more difficult to form a good quality thin film of PZT than before. The first reason is that Pb, which is the main component of PZT, is extremely likely to evaporate at 500 ° C. or higher, and as a result, it becomes difficult to accurately control the composition during film formation. The second reason is that
PZT exhibits ferroelectricity for the first time when it has a perovskite type crystal structure, but depending on the film forming conditions, it is very easy to obtain a pyrochlore type crystal structure that does not exhibit ferroelectricity, instead of the perovskite type crystal structure. That is,
Generally, a temperature of about 500 ° C. or higher is required to form a thin film of PZT having a perovskite type crystal structure, but when the temperature is raised, Pb is evaporated and PZT deviates from a desired composition. The problem arises.

As described above, although it is difficult to form a good quality thin film of PZT with good reproducibility, it is currently the most popular dielectric material used for the ferroelectric thin film of the ferroelectric memory. This is because no suitable dielectric material other than PZT has been found. For example, in dielectric materials other than PZT, barium titanate (BaTiO ₃ ) is used.
Is widely known to exhibit ferroelectricity. Moreover, Pb
Since Ba is less likely to evaporate compared with, it is easy to control the composition in the formation of a BaTiO ₃ thin film, and
In a TiO ₃ thin film, a crystal structure other than a perovskite type crystal structure (for example, a pyrochlore type crystal structure) is rarely formed.

Despite these advantages, the reason why BaTiO ₃ has not been studied so far as a dielectric material used for a ferroelectric thin film of a ferroelectric memory is that the residual polarization is smaller than that of PZT, and the residual polarization is small. The temperature dependence of polarization is large. The cause is BaTiO ₃
The original Curie temperature is relatively low at about 120 ° C. That is, the Curie temperature is a temperature unique to a dielectric material that undergoes a phase transition from a ferroelectric phase to a paraelectric phase, and even a dielectric material exhibiting ferroelectricity does not exhibit ferroelectricity at a temperature higher than the Curie temperature. Therefore, in a ferroelectric memory using BaTiO ₃ as a dielectric material, for some reason, 120
Not only may the memory contents be lost when exposed to high temperatures of ℃ or higher, but electronic circuits are usually used.
Even in the temperature range of about 5 ° C. or less, the temperature dependence of the residual polarization in the capacitor is large and the operation becomes unstable. Therefore, the BaTiO ₃ thin film was conventionally considered not suitable for use as a capacitor of a ferroelectric memory.

On the other hand, in a BaTiO ₃ thin film epitaxially grown on a Pt / MgO single crystal substrate recently,
The phenomenon that the Curie temperature rises to 200 ° C. or higher is observed, “Kenji Iijima et al., Applied Physics, Vol. 62, No. 12 (1993), p. 1250 to 1251 ”. According to this document, the above-mentioned phenomenon occurs because the thin film of BaTiO ₃ is epitaxially grown so as to match the lattice constant of Pt, and the a-axis of the lattice having the perovskite type crystal structure is contracted and the c-axis thereof is extended. Is believed to be. However, the increase in the Curie temperature is observed here because of the extremely thin film thickness of BaTi.
In a thin film of O ₃ , for example, when the film thickness is thicker than 10 nm, the lattice having the perovskite crystal structure tends to return to the original lattice constant of BaTiO ₃ due to the misfit transition, so that the Curie temperature is not significantly increased. I can't expect.

However, it is said that the ferroelectric thin film generally tends to have smaller remanent polarization as the thickness becomes thinner in a region of 1 μm or less. In fact, in the above-mentioned literature, the residual polarization is ^{2 to} ₃ μC / cm ² or less in the BaTiO ₃ thin film having a film thickness of 100 nm or less. Therefore,
Even if a thin film of BaTiO _{3 having} a film thickness of about 10 nm or less could significantly raise the Curie temperature, a practical residual polarization cannot be obtained as a ferroelectric thin film. Therefore, it is still difficult to apply the BaTiO ₃ thin film to the capacitor of the ferroelectric memory.

In addition, in recent years, in conventional DRAMs, in response to the recent high integration, conventional silicon oxides (S
Instead of iO ₂ ) or silicon nitride (Si ₃ N ₄ ),
Use of a dielectric material having a perovskite type crystal structure having a large relative dielectric constant has been studied. That is, here, a dielectric material having a perovskite crystal structure such as strontium titanate (SrTiO ₃ ) or calcium titanate (CaTiO ₃ ) which does not exhibit ferroelectricity (Curia temperature is below room temperature) is used. Therefore, it has been attempted to increase the capacity of the capacitor of the memory cell and reduce the area thereof. However, in the dielectric materials having these perovskite type crystal structures, a large capacitance as expected from the original relative permittivity of the dielectric material is not obtained when thinned, and the temperature dependence of the capacitance is not obtained. However, it has not yet been put into practical use in DRAM.

For example, SrTiO ₃ , BaTiO ₃ , P
It is known that bTiO ₃ , PbZrO _{3 and the} like have a single composition as a bulk material and a relative dielectric constant of 100 to 1000 in mutual solid solution composition.
Widely used in capacitors.

However, these thin films of SrTiO ₃ or the like have a problem that the relative dielectric constant gradually decreases if they are simply thinned to increase the capacitance. For example, in the case of bulk material, the relative dielectric constant is easily over 1000.
In the case of a _1-x Sr _x TiO ₃ , the relative dielectric constant decreases to about 250 when the film thickness becomes 30 nm, so that the SiO ₂ converted film thickness, which represents the charge storage capacity, remains around 0.4 nm. Therefore, when creating a 1 Gbit class DRAM,
If a thin film capacitor using a BaSrTiO ₃ dielectric film is configured in a plane, the amount of accumulated charge is insufficient, and it is necessary to make a three-dimensional shape with an aspect ratio of 2 or more, which is a problem that the fabrication becomes more difficult.

Further, a semiconductor memory device using a ferroelectric thin film, that is, a ferroelectric memory such as FRAM has the same problem. For example, even in the thin film of PbZr _1-x Ti _x O ₃ currently used for FRAM,
As the film becomes thinner, the ferroelectricity tends to be lost,
A film thickness of at least 200 nm is required. However, when such a thick dielectric film is used, high integration is very difficult.

Moreover, in the case of a crystalline dielectric material, as described above, its characteristics particularly depend largely on the crystal structure and composition. Therefore, when using it for the capacitor of the memory cell,
If the crystal structure and composition are not accurately controlled during film formation, the capacitance of the capacitors will vary among memory cells,
The reliability of the semiconductor memory device is impaired. However, so far, regarding a semiconductor memory device using such a crystalline dielectric material for a capacitor of a memory cell, an effective technique for achieving high integration while suppressing the fluctuation of the capacitance of the capacitor between memory cells has been proposed. Not established.

The ferroelectric thin film used here is
High performance is required to realize the function of the ferroelectric memory, such as remanent polarization, coercive electric field, and fatigue resistance. For example, writing / reading of this memory means that the ferroelectric thin film repeatedly accumulates and discharges charges, and at this time, fatigue such as coercive electric field and reduction of remanent polarization is a problem. One of the causes of this fatigue is the pinning of the dielectric domain due to the charge accumulated at the interface between the dielectric thin film and the electrode. If an electrode material with less interface charge generation is used to reduce this pinning, There is a problem that the leak current increases.

On the other hand, in order to reduce the fatigue, an electric field which does not cause polarization reversal at the time of reading information, that is, an electric field less than the coercive electric field is applied to operate the DRAM,
A method of performing nondestructive reading has also been devised, but in this case, the amount of accumulated charge effective for reading information decreases, and it becomes necessary to further increase the capacitance of the capacitor, which is more excellent. A dielectric material with properties would have to be used.

Further, in the ferroelectric memory, when the film thickness of the ferroelectric thin film is reduced in response to the large scale integration,
An increase in leak current becomes a problem. Then, as the film thickness is reduced, the fatigue becomes remarkable. In thin film capacitors that use ferroelectric thin films, there are several reciprocity laws regarding the thickness of the dielectric film, which are small, have large remanent polarization, and have a small leakage current. It was difficult to satisfy all of these characteristics.

[0019]

As described above, a dielectric film having a perovskite type crystal structure conventionally used for a thin film capacitor of a ferroelectric memory or DRAM, etc. is formed by epitaxial growth and thinned. As a result, the Curie temperature can be raised. However, when the film thickness is reduced, the remanent polarization becomes smaller,
Further, when the film is made thin, there is a problem that a large capacitance as expected from the original relative permittivity of the dielectric material is not obtained, and the temperature dependency of the capacitance is insufficient. For this reason, even if a dielectric film having a perovskite type crystal structure is applied to a thin film capacitor, a sufficient effect has not been obtained at present.

That is, the dielectric film having the perovskite type crystal structure has an essential big problem that the dielectric characteristics are deteriorated when it is thinned, and it is a big problem when it is used for a capacitor of a memory cell of a semiconductor memory device. It is a point. Further, when using such a crystalline dielectric material for a capacitor of a memory cell, it is very important to suppress the variation in the capacitance of the capacitor between the memory cells in order to secure the reliability of the semiconductor memory device. It becomes important. Further, in a ferroelectric memory in which remanent polarization is a basic principle of memory, fatigue such as coercive electric field and reduction of remanent polarization is a problem.

The present invention has been made in view of the above circumstances, and an object thereof is, firstly, a dielectric having a perovskite type crystal structure used for a ferroelectric memory or a thin film capacitor of a DRAM. In the film, the Curie temperature is raised above the original Curie temperature of the dielectric material, and the temperature range in which the dielectric film exhibits ferroelectricity is wide, and the value of remanent polarization is large enough for practical use. Moreover, it is to provide a thin film capacitor having good temperature dependence of capacitance.

Another object of the present invention is to use such a dielectric film in a capacitor of a memory cell so that the variation in the capacitance of the capacitor between cells is small and the residual polarization in the capacitor is large. It is an object of the present invention to provide a semiconductor memory device such as a ferroelectric memory that can operate stably and a DRAM that has a large capacity of a capacitor over a wide temperature range and can be highly integrated.

Still another object of the present invention is to provide a semiconductor memory device in which fatigue such as reduction of remanent polarization of a thin film capacitor and reduction of coercive field due to reading of information is reduced.

[0024]

In order to solve the above problems, the present invention employs the following configurations.

That is, the present invention is, firstly, a conductive substrate made of a conductive material having at least a surface having a crystal structure belonging to either a tetragonal (001) plane or a cubic system,
A dielectric film made of a dielectric material having a perovskite type crystal structure belonging to either a tetragonal system or a cubic system epitaxially grown on the conductive substrate, and an upper electrode formed on the dielectric film. In the thin film capacitor including, the original Curie temperature of the dielectric material is 1
At 50 ° C. or lower, the intrinsic lattice constant a _d of the dielectric material expressed by the a-axis length of the perovskite type crystal structure and the conductivity expressed by the a-axis length of either tetragonal or cubic crystal structure materials and natural lattice constant a _s, and satisfies the relationship of _{1.002 ≦ a d / a s ≦} 1.015 ( claim 1).

Further, at least the surface has a tetragonal (00
1) A conductive substrate made of a conductive material having a crystal structure belonging to either a plane or a cubic system, and a perovskite type crystal belonging to either a tetragonal system or a cubic system epitaxially grown on this conductive substrate. In a thin film capacitor comprising a dielectric film made of a dielectric material having a structure, and an upper electrode formed on the dielectric film, the dielectric material has the general formula ABO ₃ (where A is Ba ，
At least one selected from the group consisting of Sr and Ca, B
Is Ti, Zr, Hf, Sn, (Mg _1/3 Nb _2/3 ),
_{(Mg 1/3 Ta 2/3)} , (Zn 1/3 Nb 2/3), (Zn
_1/3 Ta _2/3 ), (Mg _1/2 Te _1/2 ), (Co _1/2 W
_1/2 ), (Mg _1/2 W _1/2 ), (Mn _1/2 W _1/2 ),
(Sc _1/2 Nb _1/2 ), (Mn _1/2 Nb _1/2 ), (Sc
_1/2 Ta _1/2 ), (Fe _1/2 Nb _1/2 ), (In _1/2 N
b _1/2 ), (Fe _1/2 Ta _1/2 ), (Cd _1/3 N
b _2/3 ), (Co _1/3 Nb _2/3 ), (Ni _1/3 N
b _2/3 ), (Co _1/3 Ta _2/3 ), (Ni _1/3 T
a _2/3 ) at least one selected from the group consisting of a _2/3 ) and a dielectric material having a perovskite composition represented by the a-axis length of a perovskite type crystal structure
_d and the tetragonal and cubic any conductive material natural lattice constant a _s expressed by the a-axis length of the crystal structure of the relationship 1.002 ≦ a _d / a _s ≦ 1.015 It is characterized by satisfying the formula (claim 2).

Further, a first electrode, a dielectric film made of a dielectric material having a perovskite type crystal structure belonging to either a tetragonal system or a hexagonal system epitaxially grown on the first electrode, and the dielectric film. In a thin film capacitor including a second electrode formed on a body film, the dielectric film has a thickness of 15 nm or more, and the C-axis length Ce of the dielectric material after epitaxial growth and the C-axis length Ce Corresponding to the original tetragonal C-axis length or hexagonal a-axis Co of the dielectric material before epitaxial growth is Ce / Co
It is characterized by satisfying the relational expression ≧ 1.02 (claim 7).

Here, the following are preferred embodiments of the present invention. (1) The original Curie temperature of the dielectric material is 150 ° C or lower. (2) The conductive substrate is composed of a base material and a thin film of a conductive material formed on the base material. (3) At least the surface of the base material has a crystal structure belonging to either a tetragonal (001) plane or a cubic system. (4) The thickness of the thin film of the conductive material or the thickness of the first electrode formed on the base material is 80 nm or less. (5) The dielectric material is of the general formula (Ba _x Sr _1-x ) TiO
₃ having a perovskite composition represented by (0.30 ≦ x ≦ 0.90). (6) The thickness of the dielectric film is 70 nm or more. (7) The original Curie temperature of the dielectric material is room temperature or lower, and the dielectric film made of this dielectric material exhibits ferroelectricity at room temperature. (8) A semiconductor memory device is configured by arranging memory cells provided with the thin film capacitor according to claim 1, 2 or 7 and a switching transistor connected to the thin film capacitor in a matrix. .

The present invention secondly provides a first electrode, a dielectric film made of a crystal positive dielectric material epitaxially grown on the first electrode, and a second film formed on the dielectric film. A thin film capacitor having electrodes and a switching transistor connected to the thin film capacitor and arranged in a matrix on a silicon substrate in a semiconductor memory device. Through an insulating film having an opening (100)
An oriented silicon layer is grown, and a dielectric film of the thin film capacitor is formed on the (100) oriented silicon layer (claim 12).

In the semiconductor memory device of the present invention, the step of forming an insulating film having a partial opening on the silicon substrate on which the switching transistor is formed, and the opening of the insulating film on the insulating film as a seed ( It may be manufactured by a manufacturing process including a step of growing a (100) oriented silicon layer and a step of epitaxially growing the crystalline dielectric material on the (100) oriented silicon layer.

The preferred embodiments of the present invention are as follows. (1) The dielectric material has a perovskite crystal structure or a layered perovskite crystal structure. (2) The (100) oriented silicon layer is a single crystal silicon film. (3) A single crystal silicon layer grown on a silicon substrate is created by a selective growth method for a silicon substrate, that is, a single crystal silicon is selectively epitaxially grown, or amorphous silicon is selectively grown, and then solid phase growth is performed from the silicon substrate. It should be a single crystal. (4) A barrier layer or a lower electrode layer for preventing mutual diffusion was epitaxially grown between the dielectric film and the (100) oriented silicon layer.

A third aspect of the present invention is the semiconductor memory device according to the eleventh aspect, wherein the dielectric film of the thin film capacitor exhibits ferroelectricity at room temperature, and an electric field higher than a coercive electric field is applied to the dielectric film. By doing so, the interface resistance between the dielectric film and the electrode changes depending on the polarization direction of the dielectric film to write information, and the change in leakage current value when an electric field below the coercive electric field is applied is used. Non-destructive reading of information is performed (claim 13).

The preferred embodiments of the present invention are as follows. (1) The thin film capacitor has a pair of electrodes having substantially different work functions. (2) One electrode is RuO ₂ or ReO ₃ or Pt, I
consists of at least one selected from r, Rh, Os,
One of the electrodes consists of a perovskite type oxide. (3) The dielectric film of the thin film capacitor is Ba _1-x Sr _x TiO 2.
₃ (0.1 ≦ x ≦ 0.9), which is a thin film epitaxially grown on one electrode material. (4) The dielectric film is Ba _1-xy Sr _x RE _y TiO ₃ (0.
1 ≦ x ≦ 0.9, RE is at least one selected from rare earth elements, 0.0001 ≦ y ≦ 0.1), and is a thin film epitaxially grown on one electrode material. (5) Perovskite type oxide ABO ₃ (where A is A in the perovskite crystal structure) is used as at least one of the electrode materials.
At least two kinds selected from alkaline earth metals, rare earth metals and Y, which are site constituent elements, and B represents a B site constituent element, and at least one kind selected from transition metals should be used.

[0034]

In the present invention, firstly, in order to make the Curie temperature higher than the original Curie temperature of the dielectric material, and to make the remanent polarization value and the capacitance sufficiently large for practical use, the dielectric film used in the dielectric film is used. The ratio of the original lattice constant a _{d of the} conductive material to the original lattice constant a _s of the conductive material that is the base of the dielectric film is set in the range of 1.002 ≤ a _d / a _s ≤ 1.015,
The a axis of the lattice having the perovskite type crystal structure is contracted c
A dielectric film having an elongated axis is formed with a sufficient film thickness.

The reason for limiting the value of a _d / a _s to 1.002 or more in the present invention is that the Curie temperature of the dielectric film does not rise above the original Curie temperature of the dielectric material if it is smaller than 1.002. This is because even if it rises, it will be very small. On the other hand, the reason why the value of a _d / a _s is limited to 1.015 or less is that if it is larger than 1.015, a misfit transition occurs during epitaxial growth of a dielectric film on a conductive substrate. The reason is that a sufficiently high Curie temperature cannot be obtained for a thick dielectric film having a thickness of 70 nm or more. The value of a _d / a _s is 1.01.
When it is larger than 5, even if the Curie temperature can be raised for a thin dielectric film having a film thickness of less than 70 nm, the rise is slight. Furthermore, a _d / a _s
If the value of is in the range of 1.002 or more and 1.011 or less,
Since the misfit of the lattice constant is small, the dielectric film having good crystallinity can be easily epitaxially grown regardless of the film forming temperature, which is more preferable.

In the present invention, the conductive substrate is not particularly limited as long as at least the surface is conductive and has a crystal structure belonging to the tetragonal (001) plane or the cubic system. . Therefore, in the case of a cubic crystal structure, the plane orientation is not particularly specified, but a crystal having a crystal structure whose surface belongs to the cubic (100) plane is preferable because a dielectric material can be epitaxially grown on it. . Specifically, for example, a metal such as Pt or N
(Ba _x Sr _1-x ) T whose resistance has been lowered by adding b etc.
A single crystal substrate of a conductive compound having a perovskite type crystal structure such as io ₃ (0 ≦ x ≦ 1) can be used as it is, or a thin film of these conductive materials can be used as an insulating Mg film.
It is also possible to use a substrate formed by a method such as epitaxial growth on a base material such as O (100) single crystal or SrTiO ₃ single crystal. When a thin film of a conductive material such as Pt is formed on a base material such as MgO (100) single crystal to form a conductive substrate, the crystal structure on the surface of the conductive substrate is tetragonal. From the viewpoint of controlling to the (001) plane or the cubic system, at least the surface is (001)
It is preferable to use a substrate having a crystal structure belonging to the plane or cubic system. In addition, a of the crystal structure of the surface of the base material
When the lattice constant represented by the axial length is a _s0 , a _d / a _s0
Values similar to the values of _{a d / a s 1.002 ≦ a} d / a
It is more preferable that the relationship of _s0 ≦ 1.015 is satisfied, because the Curie temperature of the dielectric film is likely to rise.

Further, when a thin film of a conductive material is formed on a base material to form a conductive substrate as described above, the thickness of the thin film of a conductive material is preferably 80 nm or less. That is, by setting the thickness of the thin film of the conductive material to 80 nm or less, even when the thickness of the dielectric film is increased to about 70 nm or more when the dielectric film is epitaxially grown thereon, the dielectric film has a lattice constant of the underlying layer. It is possible to surely maintain a state in which the a-axis of the lattice having the perovskite type crystal structure is contracted and the c-axis of the lattice is expanded by epitaxial growth so as to match with. On the other hand, if the thin film of the conductive material is thick, plastic transition tends to easily occur in the thin film of the conductive material during the growth stage of the perovskite type crystal. Therefore, when the thickness of the thin film of the conductive material exceeds 80 nm, even if the value of the ratio of a _d and a _s is set within a predetermined range, the conductivity of the underlying layer is increased when the dielectric film is epitaxially grown. There is a possibility that the Curie temperature of the dielectric film cannot be made higher than the original Curie temperature of the dielectric material due to a plastic transition in the thin film of the material that matches the lattice constant of the dielectric film. However, if the thin film of the conductive material is too thin, the function as the lower electrode may be impaired. Therefore, the thin film of the conductive material is preferably about 50 nm.

The dielectric material having a perovskite type crystal structure that can be used in the present invention includes barium titanate (BaTiO ₃ ) and strontium titanate (S).
rTiO ₃ ), calcium titanate (CaTiO ₃ ),
Simple perovskite type oxides such as barium stannate (BaSnO ₃ ) and barium zirconate (BaZrO ₃ ), barium magnesium niobate (Ba (Mg _1/3
Nb _2/3 ) O ₃ ), barium magnesium tantalate (Ba (Mg _1/3 Ta _2/3 ) O ₃ ), and other complex perovskite-type oxides, and a plurality of these oxides are simultaneously dissolved. It is needless to say that the above system is exemplified and further, some deviation from the stoichiometric ratio is allowed.

When a dielectric film made of such a dielectric material is epitaxially grown on a conductive substrate, the growth orientation is a tetragonal (001) plane or a cubic system of the dielectric film and the conductive substrate. Are preferably grown so that their (100) planes are parallel to each other. Examples of the method for forming the dielectric film include reactive vapor deposition, rf sputtering, laser ablation, MOCVD, and the like. Sputtering is particularly preferred for forming the. Further, the thickness of the dielectric film is preferably 70 nm or more from the viewpoint of obtaining a sufficient residual polarization or effective dielectric constant when used in a ferroelectric memory, and practically within a range of 70 nm or more and 1 μm or less. Is desired. However, as for the paraelectric dielectric film used for DRAM, etc., even if the film thickness is less than 70 nm, D
It can be sufficiently applied to a capacitor of a RAM memory cell or the like.

The reason why the original Curie temperature of the dielectric material is defined as 150 ° C. or less in the present invention is that the dielectric material whose Curie temperature is not so high raises the Curie temperature by applying the present invention. The effect due to is extremely remarkable, and when the dielectric film showing ferroelectricity is formed by epitaxial growth on the conductive substrate, the polarization axes are sufficiently aligned in the film thickness direction, and as a result This is because a dielectric film with little deterioration can be formed. That is, the present invention is to form a dielectric film in which the a-axis of the lattice having the perovskite type crystal structure is contracted and the c-axis of the lattice is extended as described above. Thus, the difference in the lattice constant between the dielectric film and the underlayer is obtained. By forcibly introducing strain in a predetermined direction into the lattice by utilizing, the Curie temperature rises above the original value of the dielectric material. Here, a dielectric material having a Curie temperature of 150 ° C. or lower generally has a small crystal anisotropy at room temperature, in other words, a small spontaneous strain in the lattice, and therefore the strain forcedly introduced into the lattice is spontaneous in the lattice. It is hardly canceled by the dynamic strain, and the forced strain introduction into the lattice becomes very effective.

However, a dielectric material having a Curie temperature of more than 150 ° C. usually has a large spontaneous strain in the lattice, and when it is epitaxially grown on a conductive substrate, the stress and the reaction at the time of film formation are increased. In order to relax the electric field, 90 ° domains having mutually different directions of spontaneous strain of the lattice are formed in the dielectric film. Therefore, the unidirectional strain forcedly introduced into the lattice may be offset by the spontaneous strain of the multidirectional lattice, and the Curie temperature may be slightly increased. . Further, when 90 ° domains having mutually different directions of the spontaneous strain of the lattice are formed in the dielectric film, an electric field is applied in the film thickness direction of the dielectric film in the domain in which the polarization axis is in the film plane. 90 ° of the grid when applied
Inversion occurs, which causes deterioration due to repeated polarization inversion. Further, since a dielectric material having a Curie temperature of higher than 150 ° C. usually contains Pb and Bi as the main components, it is difficult to suppress the compositional variation due to the evaporation of Pb and Bi during the formation of the dielectric film. It is difficult to simply obtain a good-quality dielectric film. Moreover, the Curie temperature is 1
Since the Curie temperature is sufficiently high for a dielectric material having a temperature of more than 50 ° C., the Curie temperature can be used as it is for the dielectric film without any problem when applied to a capacitor of a memory cell of a semiconductor memory device. The increase in Curie temperature due to is not particularly effective.

Further, as described above, when represented by the general formula ABO ₃ , A is at least one of Ba, Sr and Ca, and B
Is Ti, Zr, Hf, Sn, (Mg _1/3 Nb _2/3 ),
(Mg _1/3 Ta _2/3 ), (Zn _1/3 Nb _2/3 ), (Zn
_1/3 Ta _2/3 ), (Mg _1/2 Te _1/2 ), (Co _1/2 W
_1/2 ), (Mg _1/2 W _1/2 ), (Mn _1/2 W _1/2 ),
(Sc _1/2 Nb _1/2 ), (Mn _1/2 Nb _1/2 ), (Sc
_1/2 Ta _1/2 ), (Fe _1/2 Nb _1/2 ), (In _1/2 N
b _1/2 ), (Fe _1/2 Ta _1/2 ), (Cd _1/3 N
b _2/3 ), (Co _1/3 Nb _2/3 ), (Ni _1/3 N
b _2/3 ), (Co _1/3 Ta _2/3 ), (Ni _1/3 T
a _2/3 ), a dielectric material having a perovskite composition of at least one of a _2/3 ) has a high melting point of 1000 ° C. or higher for each oxide of each constituent metal element, and is a dielectric substance at a temperature of about 600 ° C. Evaporation hardly occurs even when a film is formed, and fluctuations in composition during formation of the dielectric film are suppressed, which is preferable. Moreover, the general formula ABO ₃
In the case of the dielectric film made of a dielectric material having a perovskite composition in which A is at least one of Ba, Sr, and Ca and does not contain Pb or Bi, the ferroelectric film is a nonvolatile semiconductor memory device. When used for a thin film capacitor of body memory, it can sufficiently cope with high-speed operation.

That is, in general, in a ferroelectric memory, a large amount of heat generation due to hysteresis loss due to repeated polarization reversal in the capacitor of the memory cell becomes a problem, especially when performing a high-speed and frequent operation, and a dielectric used for a thin film capacitor is a problem. It is desirable that the thermal conductivity of the conductive material be good. On the other hand, the atomic weights are 40.08, 87.62,
The dielectric material having a perovskite composition containing Ba, Sr, and Ca of 137.3 has an atomic weight of 207.2.
It is known that its specific gravity is smaller than that of the case where Pb of No. 2 or Bi of 208.89 is contained, and generally, the smaller the specific gravity is, the better the thermal conductivity is. If a thin film capacitor is formed using a film, it is possible to sufficiently suppress the influence of heat generation due to repeated polarization inversion.

Further, in the present invention, the original Curie temperature of the dielectric material is slightly lower than room temperature, specifically -150 ° C.
It is particularly preferably applied to a dielectric material having a temperature of not lower than 20 ° C. and not higher than 20 ° C. That is, in such a dielectric material, since the original Curie temperature is room temperature (25 ° C.) or lower, it exhibits paraelectricity as a bulk material. However, by making the film thin, the Curie temperature can be brought close to or higher than room temperature, and as a result, a large relative permittivity or ferroelectricity can be imparted to the dielectric film at room temperature. For example, in the case of BaTiO ₃ having a Curie temperature of 120 ° C. and SrTiO ₃ (Cu _x Sr _1-x ) TiO ₃ having a Curie temperature of about 0 K in absolute temperature, 0.30 is obtained.
When ≦ x ≦ 0.70, the original Curie temperature is slightly lower than room temperature and exhibits paraelectric properties as a bulk material, but the Curie temperature when thinned by increasing the temperature of the conductive substrate is raised above room temperature. Therefore, it is possible to obtain a dielectric film that exhibits ferroelectricity at room temperature.

Incidentally, this general formula (Ba _x Sr _1-x ) Ti
The dielectric material represented by O ₃ is not limited to the composition exhibiting paraelectricity as a bulk material as described above. The point is that its original lattice constant a _d and the underlying conductive material are essential. If it is possible to set the value of the ratio to the lattice constant a _s within the range specified in the present invention, the value of x in the formula exceeds 0.70, and the bulk material has a composition exhibiting ferroelectricity. It doesn't matter. That is, for example, in the case of a conductive substrate in which a Pt thin film is formed on the surface of a base material made of MgO (100) single crystal, the original lattice constant a _s of Pt is 0.392.
It is known to be 31 nm. At this time, BaT
iO ₃ natural lattice constant a _d is 0.3994nm, SrT
iO ₃ is the original lattice constant a _d in 0.3905nm, a _d
/ A _s are 1.018 and 0.995, respectively, and when these dielectric materials are used, the value of a _d / a _s deviates from the range defined by the present invention. However, when represented by the general formula (Ba _x Sr _1-x ) TiO ₃ , 0.30 ≦
dielectric material having a composition of x ≦ 0.90 is because the natural lattice constant a _d has an intermediate value between the BaTiO ₃ and SrTiO _3, conductive having a tetragonal crystal structure or cubic to typical Pt natural lattice constant a _s as sexual material, is satisfied the relationship _{1.002 ≦ a d / a s ≦} 1.015, significantly Curie temperature when epitaxially grown on the conductive substrate To rise.

As described above, the first aspect of the present invention is a thin film capacitor having a ferroelectric thin film used for a ferroelectric memory or the like, in which the Curie temperature is higher than the original value of the dielectric material. Is mainly formed to improve the remanent polarization and the temperature dependence of the remanent polarization, and the present invention provides a thin film capacitor having a paraelectric dielectric film used in DRAMs and the like. May be applied. In this case, since the Curie temperature of the dielectric film rises above the original value of the dielectric material, it is possible to realize a thin film capacitor having a large capacitance and good temperature dependence of the capacitance.

Secondly, in the present invention, in the case of a crystalline dielectric material, in order to solve the problem that the relative dielectric constant and the like decrease when it is thinned, attention is paid to the epitaxial growth film of the dielectric material, and An epitaxial growth film of a dielectric material is formed on the (100) oriented silicon layer selectively grown through the opening of the insulating film.

That is, by using the dielectric film having the perovskite crystal structure epitaxially grown in the memory cell as described above, the effect of increasing the ferroelectricity and the relative permittivity induced by the constraint with the underlying layer can be utilized. Further, since the polarization direction of the perovskite crystal is (100), by orienting in the (100) direction, there is little variation in the capacitance of the capacitors among the memory cells, and a semiconductor memory device having a memory cell suitable for high integration is provided. Can be created in principle.

On the other hand, when a semiconductor substrate on which a switching transistor is actually formed and a thin film capacitor using a perovskite type dielectric material are combined, elements such as Sr, Ba and Pb forming the dielectric film are included in the transistor. Since the diffusion adversely affects the switching operation, it is necessary to form the capacitor at a location separated from the substrate through the insulating layer. What is currently used as an insulating layer is an oxide or nitride of silicon, or a mixture of those oxides or nitrides with phosphorus, boron, etc., all of which is an amorphous film, and therefore, it is on the insulating layer. It is impossible to form a thin film capacitor by forming an epitaxially grown dielectric film. It is also extremely difficult to incorporate the MgO substrate into the silicon device.

The second focus of the present invention is that the (100) plane of silicon used as an integrated circuit substrate has a square lattice arrangement, and platinum (a typical example of the lower electrode) and (100) of many perovskite compounds are used. Since the () plane also has a square lattice arrangement, it is possible to epitaxially grow the perovskite crystal by positively utilizing the silicon (100) plane. Moreover, Si (100) is aligned with (100) of a perovskite crystal such as strontium titanate, which is a typical crystalline dielectric material, at a ratio of approximately square root 2: 1, and the perovskite crystal is in-plane. It is also possible to obtain almost lattice matching by rotating by 45 °. In fact, according to the literature (J.App.Phys.Vol.74, No.2, pp.1366-75,1993), SrTiO 3 is formed on the Si substrate (100) surface via the CaF ₂ (100) surface. that can film epitaxial layer are mixed in ₃ with (100) (110) have been introduced.

Therefore, the present invention has reached the point of introducing the selective growth technique of silicon in order to form the (100) oriented silicon layer on the insulating layer on the silicon substrate. That is, a silicon single crystal or the like grown from a contact hole opened in a part of a silicon substrate covered with an insulating layer is formed up to the top of the insulating layer, and a dielectric material is formed through the obtained (100) oriented silicon layer. The film can be grown epitaxially.

In the present invention, it is not necessary at this time to selectively grow a single crystal silicon layer that does not contain sub-crystal grain boundaries, but a dielectric film can be epitaxially grown thereon to a certain extent (100 ) As long as it is oriented, sub-grain boundaries may be included.
Specifically, the epitaxially grown dielectric film is
In the X-ray diffraction measurement by the 2θ method, the peaks corresponding to (100) and its multiples are (110), (211), (111)
It is sufficient that the (100) orientation is such that the intensity is 5 times or more, preferably 10 times or more with respect to the peaks such as. Further, the half-width of the rocking curve of the (200) peak of the dielectric film measured by X-ray diffraction is preferably 2 ° or less, more preferably 1 ° or less.

In order to form a single crystal silicon layer from a contact hole formed in a part of a silicon substrate, a method of directly growing a single crystal silicon layer on a silicon substrate with respect to a silicon oxide layer, or There is a method in which an amorphous silicon layer is first selectively grown with respect to a silicon oxide layer on a silicon substrate, and then annealing is performed to cause solid phase growth from the interface of the silicon substrate to single crystallize. When forming a memory cell on the single crystal silicon layer, the upper surface of the single crystal silicon layer can be planarized by a chemical mechanical polishing method (CMP) or the like.

In order to avoid mutual diffusion between the single crystal silicon layer and the dielectric film, a metal film or an insulating film having a large barrier property may be sandwiched between the single crystal silicon layer and the dielectric film as a barrier layer. desirable. Examples of the barrier metal film include silicides such as nickel and cobalt which are substantially lattice-matched with silicon, nitrides such as titanium and tungsten, and the like. In the case of silicide, the upper surface of the single crystal silicon layer can be reacted with cobalt, nickel, or the like to form the silicide layer. Examples of the barrier insulating film include fluorides such as calcium and oxides such as cerium and magnesium which are substantially lattice-matched with silicon. However, here, by interposing such a barrier layer, the material and film thickness of the barrier layer can be selected so as not to impair the (100) orientation of the dielectric film as described above. preferable.

Further, the single crystal silicon layer doped with impurities as desired forms a wiring layer (storage node) for electrically connecting one electrode of the switching transistor formed on the substrate and one electrode of the capacitor. Of course, it is possible to combine the functions. In this case, the barrier layer between the single crystal silicon layer and the dielectric film needs to be conductive.

It is also possible to connect one electrode of the switching transistor and one electrode of the capacitor with another wiring separately. In this case, it is possible to remove a part of the single crystal silicon layer once formed.

In the above example, the P used for the lower electrode
By using a dielectric material such as BaSrTiO _{3 having} a slightly larger lattice constant than t, etc. and utilizing the induced ferroelectricity, it is difficult to control the composition during film formation and easily diffuse Pb and Bi in the device. Compared with the case of using a dielectric material which originally exhibits ferroelectricity at a high temperature containing a material such as, there is a great advantage in high integration of a ferroelectric memory such as FRAM.
When a dielectric material containing Pb or the like having a larger remanent polarization value is used, for example, PbTiO ₃ and BaTi are used.
If a solid solution of O _{3 or} the like is used, it is possible to increase the dielectric characteristics by utilizing a slight difference in lattice constant from Pt.

Further, since a single-crystal barrier layer and a base electrode layer can be formed, high-speed diffusion through grain boundaries is suppressed, and diffusion between the dielectric film, the electrode, and the (100) -oriented silicon layer is reduced. be able to.

That is, according to the conventional method, even if the dielectric material having the perovskite crystal structure is used for the capacitor of the memory cell of the semiconductor memory device, the dielectric property is deteriorated when the film is thinned, so that high integration is required. However, according to the method of the present invention, the use of the epitaxial dielectric film can increase the amount of accumulated charge and induce the ferroelectricity by utilizing the restraining action with the underlying film, and further, the memory cell It is possible to reduce the variation in the capacitance of the capacitors between the two and to reduce the mutual diffusion of the dielectric film and the base film, and it is possible to create a highly integrated semiconductor memory device.

Thirdly, in the present invention, in order to solve the problems of fatigue such as the reduction of coercive electric field and residual polarization in the ferroelectric memory, the leak current of the dielectric film, which has been a conventional problem, is positively utilized. However, this leak current is used as an operating principle. This utilizes the fact that the shape of the potential barrier generated at the interface between the dielectric film and the electrode changes depending on the polarization state of the dielectric film. Since it is also possible to perform the read operation, it is possible to realize a non-volatile memory that does not require polarization reversal and has a wide tolerance for fatigue of the dielectric film. Further, since the change in leak current is utilized in reading information, not the charge stored in the dielectric film, the memory performance is not dependent on the charge stored in the capacitor. Therefore, it is possible to use a dielectric material having a small remanent polarization, which has been difficult to use in the conventional ferroelectric memory, and there is an advantage that a wider material can be selected.

Here, the structure of the present invention will be briefly described.
The basic structure of the present invention comprises a portion in which electrodes of metal or conductive solid are provided on both surfaces of a dielectric film. At this time, the dielectric film has a coercive electric field suitable for the operating voltage of the memory,
Further, it is desirable to have a certain degree of conductivity because it has a sufficient remanent polarization and a leak current is used for memory operation.

Here, as the electrode material, it is desirable to use a material having different physical properties above and below the dielectric material, and one of them has a large work function such as a metal or a conductive oxide so as to give a Schottky barrier of high energy. It is desirable to use a conductive solid, a metal having a low work function that gives a low Schottky barrier to the other electrode, a conductive solid, or a conductive oxide having semiconductor characteristics. By using two different kinds of electrode materials as described above, the polarization vs. electric field hysteresis curve (P−E
(Curve) is asymmetric with respect to the polarity of the voltage, and the characteristic is such that the remanent polarization when an electric field is applied to one side and then removed, and the remanent polarization when the electric field is applied to the other side and removed You can That is, a thin-film capacitor having a dielectric constant in the vicinity of 0 bias in one polarization state and a dielectric constant in the other polarization state greatly different can be obtained by such an electrode structure, and this difference in dielectric constant is caused by this semiconductor memory. It is the basis of the operating principle of the device.

Here, the operation of this semiconductor memory device will be described focusing on the electrode interface where the work function has a large value, that is, where a large potential barrier exists. Here, 0
We will compare the properties of this barrier with and without a large dielectric constant near the bias. Incidentally, these two states can be obtained by applying an electric field higher than the coercive electric field. The length of the depletion layer at such an electrode interface is proportional to the 1/2 power of the dielectric constant ε of the dielectric film, and the current flowing through this junction can be roughly described by the tunnel current of this depletion layer. Will be smaller. That is, the current flowing through this junction when the same bias electric field is applied is small in the polarized state that gives a large dielectric constant, and a large current flows in the polarized state that gives a small dielectric constant.

In the semiconductor memory device of the present invention, the current change of the dielectric film-electrode junction due to this polarization state is used for memory reading. The electric field used for reading here is
It is necessary to use a value less than or equal to the coercive electric field of the dielectric film, and on the other hand, in order to improve the operation speed of the memory, it is necessary to apply as large an electric field as possible to obtain a large current. Therefore, in order to adjust the electric conductivity of the dielectric film to an appropriate value for the purpose of increasing the read current, it is possible to add an appropriate impurity such as a rare earth element or Nb to the dielectric film. This impurity addition can be arbitrarily selected according to the operating voltage of the memory, the required operating speed, the configuration of the auxiliary circuit, the coercive electric field of the dielectric film, and the physical properties of the electrodes used, but it is sufficient if the resistance is too high. If a high operating current cannot be obtained and the resistance is too low, a sufficient electric field cannot be applied to the dielectric film, making it difficult to write information due to polarity reversal in the dielectric film.

Now, the electrodes used in this semiconductor memory device will be briefly described. As the electrode material used in the present invention, two kinds of electrode materials having substantially different work functions are preferably used. Here, as the electrode material having a large work function, simple metals such as various noble metals such as Pt, Ir, Rh, and OS, and electrically conductive oxides exhibiting a metallic electronic state such as ReO ₃ and RuO ₂ , Alternatively, a perovskite type oxide exhibiting metallic electric conductivity can be used. On the other hand, for the electrode having a small work function, it is possible to use various semiconductors or various electrically conductive oxides that are so-called strongly correlated metals and have intermediate properties between semiconductors and metals. Here, in this perovskite type oxide, by selecting two or more elements having different valences or ionic radii as the A site constituent elements, the content ratio of the two or more A site constituent elements is substantially changed. Since its work function can be changed to change the Schottky barrier at the interface with the dielectric film, the basic composition and structure are the same on both sides of the dielectric film, but their electrical characteristics differ greatly. The electrodes can be formed, and it becomes possible to reduce the stress applied to the dielectric film and to simplify the manufacturing process of this memory.

Further, in the semiconductor memory device according to the present invention, the reading is non-destructive reading, which is advantageous in terms of fatigue of the dielectric film as compared with the ferroelectric memory using the normal accumulated charge. Since polarization reversal is performed for writing, fatigue of the dielectric film may be a problem. At this time, the interface mismatch between the dielectric film and the electrode and the stress applied to the dielectric film increase this fatigue, which is not desirable, but when the above perovskite-type conductive oxide is used for the electrode, extremely high lattice matching This makes it possible to avoid such problems. Moreover, by further epitaxially growing a dielectric material having a perovskite crystal structure on the electrode having a perovskite crystal structure, it is possible to further improve the interface matching property. Sufficient effects can be obtained by using such materials.

The semiconductor memory device according to the present invention can essentially use various dielectric materials for the dielectric film.
For the above reason, it is desirable that the material has good compatibility with the electrode material. Ba _1-x Sr _x TiO ₃ (BS
It is known that a dielectric film such as (TO) grows epitaxially on a certain kind of electrode. At this time, by appropriately selecting the lattice constant of the electrode, the stress generated by the heteroepitaxy originally causes room temperature at room temperature. It is also known that a dielectric material having a composition that does not exhibit ferroelectricity serves as a dielectric film that exhibits ferroelectricity.

The present inventors have found that when such a dielectric film is used as a constituent element thereof, when a semiconductor memory device for reading information by utilizing a change in leak current is produced, it exhibits extremely good characteristics. . Since the BSTO thin film epitaxially grown on this electrode has a good interface state, it exhibits good fatigue resistance, and although it can be said that it is an optimal dielectric film for such applications, its charge storage amount originally shows ferroelectricity. It cannot be said that it is sufficiently higher than a ferroelectric film using a dielectric material. Therefore, when this dielectric film is used in a conventional ferroelectric memory that discharges accumulated charges to read information, there is a limit in reducing the area of the capacitor portion and achieving high integration.

On the other hand, when a semiconductor memory device that drives a MOS channel by using a leak current that changes according to a change in the polarization direction as described above is formed using this dielectric film, the accumulated charge amount is the element. The performance of the capacitor, and hence the performance of the semiconductor memory device, depends not on the amount of accumulated charge but on the change of the leak current, not on the parameter that directly affects the operation. Therefore, when the epitaxially grown BSTO thin film is used in such a semiconductor memory device, a MOS channel or the like can be driven at high speed with a small element area, and a memory excellent in fatigue resistance can be obtained.

Here, the composition of BSTO can be arbitrarily set depending on the conditions such as the lattice constant of the substrate or the lower electrode on which the epitaxial growth is performed. Further, the electric resistance can be easily reduced by adding an impurity to increase the read current by replacing a part of Ba or Sr with a rare earth element such as Sm. In order to control the electric resistance, in addition to this method of adding impurities, in the case of this substance, oxygen deficiency can be introduced to reduce the electric resistance. The introduction of oxygen vacancies can be performed by controlling the atmosphere during film formation (for example, the oxygen partial pressure during sputtering).

In addition to this, various dielectric materials such as PbTiO ₃ , PLT, and PZT can be used in the semiconductor memory device according to the present invention. Also in this case, addition of various impurities or introduction of cation deficiency is effective for increasing the read current, but it is said that the epitaxial BSTO thin film exhibits the best characteristics from the viewpoint of film formation easiness and fatigue resistance. I can say.

Here, in this BSTO thin film exhibiting ferroelectricity, for example, Pt (200) epitaxially grown on a MgO (200) substrate is used as a lower electrode, and BST is formed on this.
It can be obtained by epitaxially growing O. Further, by forming a conductive oxide having a perovskite type crystal structure having a slightly smaller lattice constant than that of BSTO as a lower electrode and depositing BSTO on the conductive oxide, a BSTO thin film having ferroelectricity epitaxially grown can be obtained.

Various materials can be used as the conductive perovskite type oxide used as the lower electrode. For example, SrTiO ₃ or C added with Nb to give conductivity is used.
It can be selected materials such as a _{1- x} Y _x TiO _3.
Here, the lattice constant of the conductive perovskite type oxide used for the lower electrode is B which is epitaxially grown thereon.
This is an important factor that has a great influence on the dielectric properties of STO thin film, and BSTO epitaxially grown by selecting a substance having a value smaller than the original lattice constant of BSTO.
Ferroelectricity can be obtained by reducing the in-plane lattice constant of and transforming into tetragonal crystal.

In order to obtain better dielectric characteristics such as higher Curie temperature, larger coercive electric field and saturated charge, the lattice mismatch between BSTO and the lower electrode should be increased. However, if this mismatch is too large, BSTO does not grow epitaxially, and a BSTO thin film exhibiting ferroelectricity cannot be obtained. The conductive perovskite type oxide is one of the most preferable ones as the lower electrode material because a substance having a wide lattice constant can be obtained by appropriately selecting the constituent elements.

In the semiconductor memory device according to the present invention, electrodes having different electronic states are bonded to the upper and lower sides of the dielectric film having ferroelectricity to form different interface barriers above and below the dielectric film. The characteristics are obtained. The conductive perovskite oxide can change its electronic state significantly by changing its composition ratio or adding a trace amount of impurities. An electrode having an electronic state can be formed. For example, Ca _0.5 Y _0.5 TiO ₃ having a metal conductivity and a low electric resistivity is used for the lower electrode, and C having a higher electric resistance having a semiconductor-like electric characteristic is used for the upper electrode.
By using a _0.8 Y _0.2 TiO ₃ , asymmetric PE
Capacitors with curves can be obtained. In addition, using conductive perovskite type oxides for both the upper and lower electrodes in this way is very effective in improving the fatigue of the ferroelectric memory, because interface matching with good matching can be obtained. is there.

Further, when the device is operated by utilizing the leakage current, the temperature rise in the capacitor due to Joule heat is a problem. That is, the increase in temperature causes a change in conductivity and dielectric breakdown, which is not preferable for memory operation. In contrast,
The constituent elements of BSTO formed by epitaxial growth are lighter than Pb and Bi, and crystals composed of lighter elements are generally superior in thermal conductivity. Therefore, it is possible to avoid the temperature rise in the capacitor by using BSTO by epitaxial growth.

[0077]

1 (a) and 1 (b) are a plan view and a vertical sectional view showing a structure of a thin film capacitor of the present invention produced in an embodiment, and the present invention will be described below based on the embodiment. .. (Example 1 and Comparative Example 1) First, as shown in FIG. 1, on a MgO (100) single crystal substrate 1 having a smooth surface, (100) -oriented Pt was used as a conductive material for forming a lower electrode 2.
Of the conductive substrate 5 according to the present invention.
And Here, the MgO (100) single crystal substrate 1 as a base material
Has a NaCl-type crystal structure belonging to the cubic system, and the Pt thin film was epitaxially grown on the base material with a film thickness of about 50 nm and had the cubic crystal structure.

Next, a dielectric film 3 having a thickness of about 230 nm (Ba _0.85 Sr _0.15 ) was formed on the obtained conductive substrate 5.
A thin film of TiO ₃ (tetragonal system) or a thin film of BaTiO ₃ (tetragonal system) was formed by the rf magnetron sputtering method, and used as an example and a comparative example, respectively. here,
Pt natural lattice constant a _s are 0.39231nm, (Ba
_0.85 Sr _0.15 ) TiO _{3 has an} original lattice constant a _d of about 0.3.
978nm, c _o is 0.400nm. BaTiO
₃ natural lattice constant a _d is 0.3994nm, c _o is 0.
It is 403 nm. Therefore, the value of a _d / a _s is also be within the range specified in the present invention in a _d / a _s = 1.013 for Example, a a _d / a _s = 1.018 in Comparative Example Is outside the range defined by the present invention.

At this time, the sputtering target was (Ba _0.85 Sr _0.15 ) TiO ₃ sintered body and BaTiO _3.
The unit targets made of ₃ sintered bodies and having a diameter of 4 inches and a thickness of 5 mm were used, the substrate temperature during film formation was 600 ° C., and the sputtering atmosphere was a mixed gas of Ar and O ₂ . Further, the composition of the formed dielectric film was analyzed by the ICP method, and it was confirmed that each of them had a substantially stoichiometric composition.

Finally, these (Ba _0.85 Sr _0.15 ) T
After forming a Ni thin film on the iO ₃ thin film or the BaTiO ₃ thin film by the rf magnetron sputtering method,
100μm × 100μ by photolithography technology
The upper electrode 4 was formed by processing into a shape of m, and the thin film capacitors of Example 1 and Comparative Example 1 were prepared.

Here, the (Ba _0.85 Sr _0.15 ) TiO ₃ thin film or the BaTiO ₃ thin film formed as the dielectric film 3 on the conductive substrate 5 has a perovskite type crystal structure ( 001), (002), (003)
Only the diffraction line from the plane appeared, and it was found that in these dielectric films 3, a perovskite type crystal structure in which the (001) plane was oriented was obtained. From the RHEED observation, it was confirmed that these dielectric films 3 were epitaxially grown on the conductive substrate 5.

Regarding these dielectric films 3, the lattice constant in the c-axis direction of the lattice having the perovskite type crystal structure was determined from the (003) diffraction angle of the X-ray diffraction pattern, and it was formed in Example 1 (Ba _0.85). In the thin film of Sr _0.15 ) TiO ₃ , c _e = 0.417 nm, and the BaT formed in Comparative Example 1 was used.
The thickness of the iO ₃ thin film was about 0.403 nm. That is,
The original c-axis lengths of (Ba _0.85 Sr _0.15 ) TiO ₃ and BaTiO ₃ are about 0.400 nm and 0.403 nm, respectively.
Therefore, in the comparative example, the value is equivalent to the original lattice constant of BaTiO ₃ , that is, c _e / _co = 1.000, whereas in the example, (Ba _0.85 Sr _0.15 ) TiO _{3 is used.}
This means that the c-axis is about 4.2% longer than the original lattice constant. That is, c _e / c _o = 1.042.

The reason why the lattice constant in the c-axis direction in the present example becomes long is that the original lattice constant a _{d of} (Ba _0.85 Sr _0.15 ) TiO ₃ is reasonably larger than the original lattice constant a _s of Pt of the underlying layer. When the dielectric film 3 is epitaxially grown on the underlying Pt thin film, (Ba _0.85 Sr _0.15 ) Ti
O ₃ grows without misfit transition so that it matches the lattice constant of Pt in the in-plane direction, and as a result, the lattice having the perovskite type crystal structure is distorted and the lattice constant shrinks in the in-plane direction. On the other hand, it is considered that the lattice constant was extended in the film thickness direction.

Subsequently, various characteristics of the thin film capacitors of Example 1 and Comparative Example 1 as described above were evaluated. First, Figure 2
FIG. 4 is a characteristic diagram showing temperature dependence of capacitance of the thin film capacitors of Example 1 and Comparative Example 1. However, the capacity was measured here with an AC voltage frequency of 100 kHz and an amplitude of 0.1 V. As shown in FIG. 2, in the thin-film capacitor of Example 1, the capacitance increased as the temperature was raised from room temperature, and the temperature Tmax at which the maximum capacitance value was obtained was about 200 ° C.
Met. This Tmax is a temperature corresponding to the Curie temperature of the bulk material, and is (Ba _0.85 Sr _0.15 ) TiO ₃
Since the original Curie temperature is known to be about 60 ° C., it is clear that the Curie temperature of the dielectric film is higher than the original Curie temperature of the dielectric material in this example.

On the other hand, the thin film capacitor of Comparative Example 1 has a Tma
x is about 12 which is almost the same as the original Curie temperature of BaTiO _3.
It is 0 ° C., and the Curie temperature of the dielectric film is almost unchanged from the original value of the dielectric material. Here, these differences occur because in the present example, misfit transition is less likely to occur in the growth stage of the dielectric film, and as described above, the lattice having the perovskite type crystal structure is kept in a distorted state. In the comparative example, even if the lattice having the perovskite type crystal structure is distorted in the initial state of the growth of the dielectric film, it is expected to return to the original even if the misfit transition occurs during the growth stage of the dielectric film. .

Further, FIGS. 3A and 3B show polarization vs. electric field (PE) hysteresis curves of the thin film capacitors of Example 1 and Comparative Example 1, respectively. However, here, a hysteresis curve was measured at room temperature by applying an alternating voltage of 5 kHz using a Sawyer tower circuit. As is clear from FIG. 3, in both the thin film capacitors of Example 1 and Comparative Example 1, hysteresis clearly appears in polarization in relation to the applied electric field. That is, in the thin film capacitor of the present embodiment, the thin film of (Ba _0.85 Sr _0.15 ) TiO _{3 as} the dielectric film exhibits ferroelectricity, and the residual polarization of the residual polarization obtained from the hysteresis curve of FIG. The size was about 0.11 C / m ^2, which was a practically sufficient value. On the other hand, FIG.
The magnitude of remanent polarization in the thin film capacitor of Comparative Example 1 obtained from the hysteresis curve of (b) is about 0.06 C /
m ² .

Further, FIG. 4 shows the temperature dependence of the remanent polarization. In FIG. 4, the vertical axis represents the remanent polarization Pr (2
Represents the ratio of remanent polarization Pr (T) at T ° C. to (0 ° C.), where the solid line in the figure is the temperature dependence of the remanent polarization of the thin film capacitor of Example 1, and the broken line is the temperature of the remanent polarization of the thin film capacitor of Comparative Example 1. It is a dependency. As shown in the figure, in the thin film capacitor of the present example, the temperature dependence of the remanent polarization is also significantly improved as compared with the thin film capacitor of the comparative example. As described above, in Example 1, the Curie temperature of the dielectric film is higher than the original Curie temperature of the dielectric material,
Along with this, a thin film capacitor having a large remanent polarization and a small temperature dependence of the remanent polarization has been realized.

Next, in the present embodiment, the thin film capacitor as described above and the MOS transistor as the switching transistor were connected to form a ferroelectric memory which is a nonvolatile semiconductor memory device. Here, FIG.
(B) shows a plan view and a cross-sectional view of a MOS transistor,
6A and 6B are a plan view and a sectional view of the thin film capacitor. The configuration of the semiconductor memory device of the present invention will be specifically described below with reference to these drawings.

In the present embodiment, as shown in FIG. 5, a plurality of MOS transistors separated from each other by the element isolation region 2 made of a thermal oxide film of Si are formed on the Si substrate 11 in a matrix form. At this time, the MOS transistor is formed from the gate oxide film 13-1 and the gate electrode 13-2 on the element isolation region 2, the source and drain regions 14-1 and 14-12 in the Si substrate 11. Here, the gate electrode 13-2 forms a part of the word line of the semiconductor memory device. Further, the bit line 15 is formed on one of the source and drain regions 14-1 and 14-2, and the source and drain regions 14-1 and 14-2 are formed.
The other is connected to the extraction electrode 16 for connection with the thin film capacitor via the contact portion 10. In the figure,
Reference numerals 17, 18 and 19 are interlayer insulating films, and 20 is a planarizing insulating film.

As for the thin film capacitor, as shown in FIG. 6, a lower electrode 2 is formed by forming a (100) -oriented Pt thin film forming a drive line on a MgO (100) single crystal substrate 1. Then, a thin film of (Ba _0.85 Sr _0.15 ) TiO _{3 and} a thin film of Ni as the dielectric film 3 are sequentially formed on the obtained conductive substrate 5, and then formed into a shape corresponding to the extraction electrode 16 on the MOS transistor side. The Ni thin film was processed to form the upper electrode 4. However, here, the film thickness of each thin film, the film forming method, and the like were the same as in the case of the thin film capacitor shown in FIG.

Next, the take-out electrode 16 and the upper electrode 4
After forming the insulating films 21-1 and 21-2 on the entire surface including, respectively, polishing processing was performed to expose the extraction electrode 16 and the upper electrode 4 and flatten the surface. Subsequently, heat treatment is performed in a state where the extraction electrode 16 and the upper electrode 4 face and are in contact with each other, and these are metal-bonded, and as a result, the MOS transistor and the thin film capacitor are connected,
A semiconductor memory device was obtained in which memory cells including the thin film capacitors and MOS transistors of this example were arranged in a matrix. FIG. 7 partially shows a vertical cross-sectional view of the structure of the obtained semiconductor memory device.

FIG. 8 is an equivalent circuit diagram of such a semiconductor memory device. As shown in the figure, here, a 1-bit memory cell includes one switching transistor 24 and one thin film capacitor 25, and is arranged in a matrix. The gate electrode of the switching transistor 24 is coupled to the word line 13, and the source and drain regions 14 are connected.
One of -1, 14-2 is connected to the bit line 15. Further, the pair of electrodes of the thin film capacitor 25 are connected to the source and drain regions 14 of the switching transistor 24, respectively.
It is connected to the other of -1, 14-2 and the drive line 22. At this time, the word line 13 and the drive line 22 are orthogonal to each other and coupled to the word line selection circuit 26 and the drive line drive circuit 27, respectively. Are arranged on both sides of the drive line 22 and are coupled to the sense amplifier 28.

When writing to this semiconductor memory device, for example, the word line selection circuit 26 selects the word line 13 at a predetermined row address, and the selected word line 13 is selected.
Is activated and the switching transistor 24 coupled thereto is turned on, and then the potential corresponding to the information "1" or "0" is applied to the bit line 15 for a predetermined column address, and the drive line drive circuit 27 is applied. Thus, the drive line 22 is activated and a write signal is transmitted. Next, when the activation of the word line 13 is stopped and the switching transistor 24 is returned to the OFF state, "1" is added to the thin film capacitor 25 in the memory cell selected by the product of the row address and the column address as described above.
Alternatively, the information of “0” is accumulated and held and the information is written. After that, the switching transistor 24 and the thin film capacitor 25 of the memory cell in which information is written
Even if one of the word line 13 and the drive line 22 coupled with is activated, the written information is not lost.

On the other hand, when reading from the semiconductor memory device, first, the word line selection circuit 26 selects the word line 13 at a predetermined row address, activates the selected word line 13 and connects it to the switching transistor. Two
Turn 4 on. Then, the bit line pair is precharged to a floating state for a predetermined column address, and then the drive line drive circuit 27 activates the drive line 22 to apply a predetermined potential. Here, storage in the thin film capacitor 25 of the memory cell selected by the product of the row address and the column address as described above,
The information retained is the switching transistor 24.
Through a bit line 15 of one of the precharged bit line pairs, and a minute potential difference corresponding to the extracted information is formed between the bit line pair. Therefore, by amplifying this potential difference by the sense amplifier 28, it becomes possible to read the information accumulated and held in the thin film capacitor 25 in the memory cell. Further, the thin film capacitor 25 in the memory cell from which information has been taken out as described above is rewritten by writing information before and after reading by a predetermined operation.

The above is an example in which a nonvolatile ferroelectric memory is constructed using the thin film capacitor of the present invention.
The thin film capacitor of the present invention can also be used in a volatile semiconductor memory device such as DRAM. FIG. 9 shows an equivalent circuit diagram of such another semiconductor memory device of the present invention. As shown in the figure, here, all of the pair of electrode sides of the thin film capacitor 25 may be set to a predetermined potential, and generally, for example, except that the lower electrode of the thin film capacitor 25 is formed on the entire surface, it is completely the same as in FIG. Similarly, in the semiconductor memory device, the lower electrode of the thin film capacitor 25 is shared by all the memory cells. In the thin film capacitor (Example 2 and Comparative Example 2) Example 2 and Comparative Example 2, respectively as a dielectric film _{(Ba 0.44 Sr 0.56) TiO 3} , (Ba 0.24 Sr 0.76)
The thin film capacitor of TiO ₃ is different from the thin film capacitors of Example 1 and Comparative Example 1 described above. That is, first, as in Example 1, on a MgO (100) single crystal substrate (cubic system) having a smooth surface, (100) oriented Pt (cubic system) was used as a conductive material for forming a lower electrode. Thin film
A film was formed by a rf magnetron sputtering method at a substrate temperature of 400 ° C. to obtain a conductive substrate. At this time, the Pt thin film was epitaxially grown to a film thickness of about 50 nm.

Next, on the obtained conductive substrate, a (Ba _0.44 Sr _0.56 ) Ti film having a thickness of about 230 nm was formed as a dielectric film.
O ₃ (cubic system) thin film or (Ba _0.24 Sr _0.76 ) Ti
A thin film of O ₃ (cubic system) was epitaxially grown by the rf magnetron sputtering method to obtain an example and a comparative example, respectively. Here, the original lattice constant a _{s of} Pt
Is 0.39231 nm, (Ba _0.44 Sr _0.56 ) TiO ₃
Natural lattice constant a _d approximately 0.3946nm, c _o is equally 0.3946Nm. (Ba _0.24 Sr _{0. 76)} Ti
O ₃ natural lattice constant is approximately 0.3927nm, c _o is also well 0.3927Nm. Therefore, the value of a _d / a _s is
Although the embodiments are within the scope defined in the present invention in a _d / a _s = 1.006, in the comparative example a _d / a _s = 1.
001 is out of the range defined by the present invention.

At this time, a binary target of BaTiO ₃ sintered body and SrTiO ₃ sintered body was used as the sputtering target, the substrate temperature during film formation was 600 ° C., and the sputtering atmosphere was a mixed gas of Ar and O ₂ . And Further, the composition of the formed dielectric film was analyzed by the ICP method, and it was confirmed that all of them had a stoichiometric composition.

Finally, these (Ba _0.44 Sr _0.56 ) T
thin iO ₃ or (Ba _0.24 Sr _{0. 76)} on the thin film of TiO _3, after forming a thin film of Ni by rf magnetron sputtering method, a photolithography technique 10
An upper electrode was formed by processing into a shape of 0 μm × 100 μm to prepare thin film capacitors of Example 2 and Comparative Example 2.

Here, an X-ray diffraction pattern of the thin film of (Ba _0.44 Sr _0.56 ) TiO ₃ formed as a dielectric film on the conductive substrate in Example 2 is shown in FIG. As shown in FIG. 10, in the (Ba _0.44 Sr _0.56 ) TiO ₃ thin film, the X-ray diffraction diagram shows diffraction lines from the (100), (200), and (300) planes of the perovskite type crystal structure. It was found that only the perovskite type crystal structure in which the (100) plane was oriented was obtained. Similarly, it was confirmed from the X-ray diffraction pattern of the (Ba _0.24 Sr _0.76 ) BaTiO ₃ thin film that a perovskite type crystal structure in which the (100) plane was oriented was obtained.

With respect to these dielectric films, the lattice constant in the c-axis direction of the lattice having the perovskite type crystal structure was determined from the (300) diffraction angle of the X-ray diffraction pattern, and it was formed in Example 2 (Ba _0.44 Sr. The thin film of _0.56 ) TiO ₃ has a thickness of about 0.406 nm and is formed in Comparative Example 2 (Ba _0.24 S
The thickness of the thin film of r _0.76 ) TiO ₃ was about 0.400 nm. That is, here, the original c-axis lengths of (Ba _0.44 Sr _0.56 ) TiO ₃ and (Ba _0.24 Sr _0.76 ) TiO ₃ are about 0.3946 nm and about 0.3927 nm, respectively. In each of the dielectric films, the c-axis is longer than the original lattice constant of the dielectric material, but the amount of change is small in the comparative example.
Incidentally, c _e / c _o = 1.028 in the example and c _e / c _o = 1.018 in the comparative example.

The reason why the lattice constant in the c-axis direction becomes long in this example is that the original lattice constant a _{d of} (Ba _0.44 Sr _0.56 ) TiO ₃ is reasonably larger than the original lattice constant a _s of Pt of the underlying layer. When the dielectric film is epitaxially grown on the underlying Pt thin film, (Ba _0.44 Sr _0.56 ) TiO 3
₃ grows in the in-plane direction without misfit transition so as to match the lattice constant of Pt, and as a result, the lattice having the perovskite type crystal structure is sufficiently distorted so that the lattice constant in the in-plane direction is It is considered that this is because the lattice constant expanded in the film thickness direction while contracting.

Subsequently, various characteristics of the thin film capacitors of Example 2 and Comparative Example 2 as described above were evaluated. Figure 1
FIG. 1 is a characteristic diagram showing the temperature dependence of the capacitance of the thin film capacitor of Example 2. However, here, the frequency of the AC voltage is 1
The capacitance was measured at 00 kHz and an amplitude of 0.1V. FIG.
As shown in FIG. 1, in the thin film capacitor of Example 2, the capacitance increases with increasing temperature from room temperature, and the temperature Tmax at which the maximum capacitance value is obtained is about 200 ° C.
(Ba _0.44 Sr _0.56 ) TiO ₃ Original Curie temperature-
The temperature is higher than 40 ° C.

Further, referring to FIGS. 12 (a) and 12 (b), Example 2
And polarization versus electric field (P-E) of the thin film capacitor of Comparative Example 2.
A hysteresis curve is shown. However, here, a hysteresis curve was measured at room temperature by applying an alternating voltage of 5 kHz using a Sawyer tower circuit. As is clear from FIG. 12A, in the thin film capacitor of Example 2, hysteresis clearly appears in polarization in relation to the applied electric field. That is, in the thin film capacitor of this example, the thin film of (Ba _0.44 Sr _0.56 ) TiO _{3 as} the dielectric film exhibits ferroelectricity. However, with respect to the thin film capacitor of Comparative Example 2, as shown in FIG. 12B, hysteresis does not appear in polarization and (Ba _0.24 S
The thin film of r _0.76 ) TiO ₃ does not show ferroelectricity. As described above, in the thin film capacitor of Example 2, the Curie temperature of the dielectric film was significantly higher than the original Curie temperature of the dielectric material beyond room temperature, and accordingly, the bulk material exhibited ferroelectricity. A ferroelectric material exhibiting paraelectricity is imparted with ferroelectricity by thinning it. (Example 3) In the thin film capacitor of this embodiment 3, SrTiO ₃ that the Nb as the substrate was added 0.5 mol% of a conductive (100) single crystal (hereinafter, STO-
Abbreviated as Nb substrate) was used. As the dielectric film, a dielectric film having a composition represented by the formula (Ba _0.44 Sr _0.56 ) TiO ₃ was formed as in Example 2.

The STO-Nb single crystal belongs to a cubic crystal like SrTiO _3, and its lattice constant a _s is about 0.3905.
nm. On the other hand, the (Ba _0.44 Sr _0.56 ) TiO ₃ dielectric also originally belongs to the cubic system, and its lattice constant a _d is 0.39.
It is 46 nm. Therefore, the ratio of the lattice constant between the substrate and the dielectric film is a _d / a _s = 1.010, which falls within the range defined by the present invention. Also, by adding Nb, ST
The resistivity of the O-Nb substrate is lowered to about 1 Ωcm, and the O-Nb substrate can sufficiently act as an electrode of the dielectric film.

The thin film of (Ba _0.44 Sr _0.56 ) TiO ₃ is
Substrate temperature 60 by rf magnetron sputtering
The film was formed at 0 ° C. in a mixed gas atmosphere of Ar and O ₂ . As the sputtering target, BaTiO ₃ sintered body and S
A binary target of rTiO ₃ sinter was used. The film thickness of the dielectric film was about 230 nm as in the example. The composition of the dielectric film, that is, the ratio of Ba, Sr, and Ti was analyzed by ICP emission spectroscopy, and it was confirmed that a dielectric film having a desired composition ratio was obtained.

Finally, a 100 nm-thick Ni thin film was formed as an upper electrode on the dielectric film by the rf magnetron sputtering method. The Ni film is 100 μm × 10 by using photolithography and chemical etching.
It was processed to a size of 0 μm.

FIG. 13 shows an X-ray diffraction _{pattern of} the (Ba _0.44 Sr _0.56 ) TiO ₃ dielectric film produced as Example 3 by such a method. As shown in this figure, the diffraction line from this (Ba _0.44 Sr _0.56 ) TiO ₃ is (00
1) plane, (002) plane, and (003) plane are limited to those from, Thus, Thus were created (Ba _0.44 Sr _0.56) in TiO ₃ dielectric film (001) It was confirmed to have a perovskite structure in which the planes were oriented.

Then, in this X-ray diffraction pattern, (B
From the (003) diffraction angle of a _0.44 Sr _0.56 TiO ₃
When the length of the c-axis of (Ba _0.44 Sr _0.56 ) TiO ₃ was calculated, the length of the c-axis was 0.4125 nm. The original lattice constant of a dielectric material of this composition is 0.3946.
Therefore, the epitaxial growth on the STO-Nb substrate causes the lattice constant in the film thickness direction to be
That's a 4.5% increase.

As described above, the reason why the lattice constant in the film thickness direction is extended is considered to be the same as the reason why the lattice constant in Example 2 is extended. That is, since the original lattice constant of (Ba _0.44 Sr _0.56 ) TiO ₃ used as the dielectric material is reasonably larger than the lattice constant of STO-Nb used as the substrate, this dielectric material is applied to this substrate. As a result of growing so that the lattice constants in the in-plane direction match at the interface during epitaxial growth, (Ba _0.44 S
It is considered that the lattice constant of r _0.56 TiO ₃ contracted in the in-plane direction, and in contrast to this, the lattice constant expanded in the film thickness direction.

Subsequently, the dielectric characteristics of the thin film capacitor thus produced were evaluated. FIG. 14 is a diagram showing the measurement results of the bias electric field dependence of the relative permittivity of the thin film capacitors prepared in this example, that is, Example 3. The relative permittivity is calculated by measuring the capacitance using an AC voltage of 100 kHz and an amplitude of 0.1 V, and calculating the capacitance value, the thickness of the dielectric film, and the area of the capacitor.

The relative permittivity showed hysteresis between when the bias electric field was rising and when it was falling. Such hysteresis is one index that suggests ferroelectricity. In order to confirm the ferroelectricity, the temperature dependence of capacitance was further measured.

FIG. 15 shows the measurement result of the temperature dependence of the capacitance in this thin film capacitor. The capacity increases with increasing temperature from room temperature, indicating that the Curie temperature is higher than room temperature. This result shows that this (Ba _0.44 Sr _0.56 ) TiO ₃ dielectric film has ferroelectricity.

It is known that (Ba _0.44 Sr _0.56 ) TiO ₃ originally belongs to the paraelectric phase at room temperature in the bulk. Therefore, in this example, (Ba _0.44 Sr
The thin film of _0.56 TiO ₃ showed ferroelectricity because the lattice constant was slightly larger than that of the substrate (Ba _0.44 Sr.
_It is nothing but the effect of epitaxially growing a _0.56 TiO ₃ dielectric film on a substrate. (Embodiment 4) FIG. 16 is a sectional view of a dynamic access memory (DRAM) semiconductor memory device according to a fourth embodiment of the present invention. 41 is a first conductivity type semiconductor substrate, 42 is an element isolation oxide film, 43 is a gate oxide film, 44 is a word line,
45 and 47 are interlayer insulating films, 46 is a second conductivity type impurity diffusion layer, 48 is a bit line, 49 is a planarizing insulating film, 50 is a polishing stopper layer, 51 is a single crystal silicon storage node, 5
2 is an epitaxial barrier metal, 53 is an epitaxial lower electrode, 54 is an epitaxial dielectric film, and 55 is an upper electrode.

FIG. 17 is a schematic sectional view in order of the steps of the fourth embodiment.
Shown in FIG. 17A is a cross-sectional view after the transistor portion of the memory cell and the bit line 48 are formed, and then the planarizing insulating film 49 and the polishing stopper layer 50 are formed. Here, an etch back method may be used to planarize the insulating film, or a CMP method or the like may be used. An insulating film such as aluminum oxide can be used as the polishing stopper layer 50.

Then, as shown in FIG. 17B, by known photolithography and plasma etching,
A contact hole to the second conductivity type impurity diffusion layer 46 was subsequently formed in the opening of the polishing stopper layer 50, and a storage node 51 was formed by a selective growth technique of single crystal silicon. The storage node 51 was selectively filled with single crystal silicon at a growth temperature of 820 ° C. by the LPCVD method using dichlorosilane as a source gas.

Next, as shown in FIG. 17C, CM
The single crystal silicon formed on the polishing stopper layer 50 is removed by P or mechanical polishing to remove a nickel thin film 61.
Was formed by a sputtering method. After that, as shown in FIG. 3D, the surface of the single crystal silicon layer is reacted with nickel by heat treatment at 500 ° C. in a forming gas to form a single crystal nickel silicide layer as a barrier metal,
The nickel layer formed on the polishing stopper layer 50 was removed again by the CMP method to form the epitaxial barrier metal 52.

Next, as shown in FIG. 17E, a shallow trench was formed in the nickel silicide layer 52 by photolithography and plasma etching, and then a platinum thin film to be the lower electrode 53 was formed by sputtering.
Then, the platinum thin film formed on the polishing stopper layer 50 was removed again by the CMP method, and then the SrTiO ₃ epitaxial dielectric film 54 and the nickel upper electrode 55 were sequentially formed. Note that a known magnetron sputtering method, MOCVD method, or the like can be used for forming the dielectric film.

Subsequently, the SrTiO ₃ dielectric film 54 formed here was subjected to X-ray diffraction measurement by the θ-2θ method. As a result, only peaks corresponding to (100) and its multiples were observed, and (110) , (211), (111), etc. were not observed. (Embodiment 5) FIG. 18 shows a structure similar to that of Embodiment 4, but the ferroelectricity is strained by utilizing the mismatch strain generated by epitaxial growth instead of the paraelectric dielectric film. In this example, a ferroelectric memory (FRAM) is formed by forming an induced ferroelectric film. 41 is a first conductivity type semiconductor substrate, 42 is an element isolation oxide film, 43 is a gate oxide film, 44 is a word line, 45 and 47 are interlayer insulating films, 46 is a second conductivity type impurity diffusion layer, and 48 is a bit line. , 49 is a planarization insulating film, 50 is a polishing stopper layer, 51 is a single crystal silicon storage node, 52 is an epitaxial barrier metal,
53 is an epitaxial lower electrode, 56 is an epitaxial dielectric film, and 55 is an upper electrode.

FIG. 19 is a schematic cross-sectional view in order of the steps of the fifth embodiment.
Shown in The process up to FIG. 19B is similar to that of the fourth embodiment, and the transistor portion and the bit line of the memory cell, the planarization insulating film 49 and the polishing stopper layer 50 are formed, and a single contact hole to the impurity diffusion layer is formed. The storage node 51 has just been formed by the selective growth technique of crystalline silicon.

Next, as shown in FIG. 19C, CM
The single crystal silicon formed on the polishing stopper layer was removed by P or mechanical polishing, and a shallow trench was formed by photolithography and ion etching. Then, as shown in FIG. 3D, the epitaxial barrier metal 52 is formed into TiN at 600 ° C. by the reactive sputtering method.
Was epitaxially grown, and the polishing stopper layer 50 was polished and removed.

Then, as shown in FIG. 19E, TiN is formed by photolithography and plasma etching.
After forming a shallow trench in the layer, a platinum thin film to be the lower electrode 53 was formed by sputtering. Then, as shown in FIG. 6F, the polishing stopper layer 5 is again formed by the CMP method.
0 After removing the platinum film is formed on, Ba _0.5
An Sr _0.5 TiO ₃ epitaxial dielectric film 56 was epitaxially grown, strain-induced ferroelectricity was imparted by mismatch strain with platinum, and a nickel upper electrode 55 was sequentially formed.

The epitaxial film thus laminated was subjected to X-ray diffraction measurement by the θ-2θ method. As a result, T
Only peaks corresponding to (200) and its multiples were observed for iN and platinum, and similarly, only peaks corresponding to (100) and its multiples were observed for BSTO, and (1)
No peaks corresponding to 10), (211), (111), etc. were observed. In addition, as a result of measuring the rocking curve for the (200) diffraction line of each film, TiN,
Platinum and BSTO are 0.8 °, 0.3 °,
A half-value width of 0.5 ° is obtained, which is very clean (100)
It was confirmed that the film was a plane-oriented film.

Furthermore, by the Sawyer tower circuit, PE
When the curve was measured, a hysteresis loop showing ferroelectricity was observed, and when the temperature dependence of the relative dielectric constant up to 150 ° C. was measured, the relative dielectric constant increased from room temperature to 150 ° C. and the Curie temperature was 150 ° C. It was confirmed to be above ℃. (Embodiment 6) FIG. 20 is a sectional view of a ferroelectric memory (FRAM) semiconductor memory device according to another embodiment of the present invention. Four
1 is a first conductivity type semiconductor substrate, 42 is an element isolation oxide film,
43 is a gate oxide film, 44 is a word line, 45 and 47 are interlayer insulating films, 46 is a second conductivity type impurity diffusion layer, 48 is a bit line, 49 and 59 are planarizing insulating films, 50 is a polishing stopper layer, Reference numeral 51 is a single crystal silicon storage node, 53 is an epitaxial lower electrode, 55 is an upper electrode, 56 is an epitaxial dielectric film, 57 is a single crystal silicon layer, 58 is an epitaxial barrier insulating film made of a calcium fluoride film, and 60 is an aluminum wiring. Is.

FIG. 21 shows a schematic cross sectional view in order of the steps of this example. FIG. 21A is a cross-sectional view after forming the transistor portion of the memory cell and the bit line, and then forming the planarization insulating film 49 and the polishing stopper layer 50. An etch-back method may be used to flatten the insulating film, or CM
The P method or the like may be used. Also here, an insulating film such as aluminum oxide can be used as the polishing stopper layer 50.

Then, as shown in FIG. 21B, by known photolithography and plasma etching,
A shallow trench portion for forming a capacitor cell and a contact hole to the second conductivity type impurity diffusion layer 46 were formed, and an amorphous silicon layer 62 was formed by a selective growth technique. As a film forming technique, amorphous silicon was selectively grown on a single crystal silicon substrate at a growth temperature of 450 ° C. by an LPCVD method using disilane and diborane as source gases. After that, heat treatment was performed at 600 ° C. in a forming gas to grow single crystal silicon from the interface of the silicon substrate by solid phase growth, so that all the amorphous layers were single crystallized.

Next, as shown in FIG. 21C, CM
The single crystal silicon formed on the polishing stopper layer 50 was removed by P or mechanical polishing to form the single crystal silicon storage node 51 and the single crystal silicon layer 57. Thereafter, as shown in FIG. 3D, a calcium fluoride film 58 serving as a barrier and a platinum film serving as the lower electrode 53 were epitaxially grown by a sputtering method while sequentially heating the substrate. Then, PbZrT which is a ferroelectric material
After forming an amorphous film of iO _{3 by} a sputtering method at room temperature, it is solid-phase grown by lamp heating at 700 ° C. for 1 minute to form an epitaxial dielectric film 56. After that, an upper metal 55 was formed and processed into a capacitor cell shape by known photolithography and plasma etching.

Next, as shown in FIG. 21E, a flattening insulating film 59 was formed, and the surface was flattened by the CMP method or the etch back method. Thereafter, as shown in FIG. 6F, contact holes with the single crystal silicon storage node 51 and the upper electrode 55 of the capacitor were opened by photolithography and plasma etching, and an aluminum wiring 60 was formed.

Subsequently, the epitaxial film here was subjected to X-ray diffraction measurement by the θ-2θ method.
00) and peaks corresponding to multiples thereof are observed,
No peaks corresponding to (110), (211), (111), etc. were observed. (Embodiment 7) FIG. 22 is a sectional view showing a structure of a thin film capacitor portion of a semiconductor memory device according to a seventh embodiment of the present invention. A 400 nm TiN film 72 is epitaxially grown on the Si single crystal substrate 71 by a known method using magnetron sputtering, and a 200 nm Ca _0.5 Y _0.5 TiO ₃ film is formed as a lower electrode 73 thereon by magnetron sputtering. . At this time, CaTiO ₃ and YTiO ₃ are used as targets, and the film forming atmosphere is A
The substrate temperature is 200 ° C. in a mixed gas of r and oxygen.

Further, Ba _0.5 Sr is formed on the lower electrode 73.
_{The 0.5} TiO ₃ dielectric film 74 has a thickness of 200 nm, and a Ca _0.8 Y _0.2 TiO ₃ film as an upper electrode 75 is further formed on top of it.
00 nm, deposited using a similar procedure. At this point, the lower electrode 73, the upper electrode 75, and the layers of the dielectric film 74 are amorphous. This is annealed at 700 ° C. for 1 minute using an infrared lamp annealing device, and the upper and lower electrodes 7
3, 75 and the dielectric film 74 were single-crystallized. At this time, C
The a-Y-Ti-O film was a single crystal film, and it was confirmed by X-ray diffraction that the c-axis was growing perpendicular to the substrate.

FIG. 23 shows the result of measuring the current-voltage characteristics of the capacitor thus manufactured at room temperature. As shown in the figure, the current-voltage characteristics show a large hysteresis characteristic depending on the polarization direction, and it is understood that the current flowing in the vicinity of ± 1 to 3 V has a good memory function which is 1000 times different depending on the polarization direction. Therefore, by using this capacitor, 1-bit information is written by applying a voltage above the coercive electric field to invert the polarization, and the value of the current flowing when a bias voltage below the coercive electric field is applied varies greatly depending on the polarization direction. It is possible to create a non-volatile semiconductor memory device that performs non-destructive reading by utilizing. (Embodiment 8) Using the same method as in Embodiment 7, Ca _0.8 Y _0.2 TiO ₃ 200 nm is used as the lower electrode and B is used as the dielectric film.
a _0.5 Sr _0.5 TiO ₃ 100 nm was deposited and an epitaxial film was formed by the same annealing method. FIG. 24 shows the current-voltage characteristics of the capacitor formed by depositing Pt as the upper electrode on this. Also in this capacitor, as in the case of Example 7, the current flowing depending on the polarization direction shows a large change, and by using this, a nonvolatile semiconductor memory device can be obtained. (Example 9) C was used as the lower electrode by the same method as in Example 7.
a _0.5 Y _0.5 TiO ₃ , Ba _0.45 La _0.05 S on the dielectric film
r _0.5 TiO ₃ and Ca _0.8 Y _0.2 TiO ₃ were deposited on the upper electrode to a thickness of 200 nm, respectively, and heat-treated to obtain an epitaxial laminated film. The current-voltage characteristic of this capacitor is shown in FIG. As shown in the figure, it can be seen that this capacitor also shows a current value that greatly differs depending on the polarization direction, and that the current value in the forward direction significantly increases. By adding impurities to the dielectric film to change the electric conductivity in this way, a large leak current can be obtained, and when a nonvolatile semiconductor memory device is constructed using this capacitor, a higher speed Readout can be performed and fatigue resistance is improved. (Embodiment 10) In this embodiment, in the device structure shown in FIG. 20, a non-volatile semiconductor memory device is produced by using a leak in a dielectric film as a principle of operation.

As shown in FIG. 20, if a memory cell composed of a switching transistor and a capacitor is used,
By applying a voltage higher than the coercive electric field of the ferroelectric film of the capacitor through the switching transistor selected by the word line and the bit line, it becomes possible to polarize in the positive or negative direction and write 1-bit information. . Similarly, when an appropriate voltage equal to or lower than the coercive electric field is applied to the capacitor element, a large difference occurs in the read current depending on the polarization direction, so that the written information can be read nondestructively. (Embodiment 11) In this embodiment, a circuit configuration of a dielectric memory in which the thin film capacitor according to the present invention is integrated will be described.

In this embodiment, a plurality of memory cells having the structure shown in FIG. 7 are arranged in a matrix on a semiconductor substrate. Although it is possible to configure a memory cell for storing one digital signal from one capacitor and one transistor, here, a case where two capacitors and two transistors are used is described for simplification of description. . FIG. 26 shows a circuit configuration of such a ferroelectric memory.

One terminal of one capacitor is a MOS
Bit line (B
L) and the other terminal is a drive line (DL)
Connected to. Similarly, for the other capacitor, one terminal is connected to the bit line (BL ') via the source and drain of the MOS transistor, and the other terminal is connected to the drive line (DL). BL and B
The two bit lines L'are paired and connected to the same sense amplifier 73, 74. The drive line may be a single common line and is connected to the drive circuit 71 for the drive line.

MO connected to one terminal of the capacitor
The gate of the S transistor is connected to the word line (WL). The gates of the two MOS transistors inside the same cell are connected to the same word line WL. Word line WL
Are connected to the word line drive circuit 72.

In the circuit configuration shown in FIG. 26, the bit line pairs and the drive lines are arranged in parallel and shared by a plurality of memory cells in the same row among a plurality of memory cells arranged in a matrix. ing. On the other hand, the word line is arranged so as to be orthogonal to the bit line and the drive line, and is shared by a plurality of memory cells in the same column among a plurality of memory cells arranged in a matrix.

Sense amplifiers 73 and 74 are connected to each bit line pair, and the sense amplifiers 73 and 74 are activated by the signal φact.

Input / output (I / O) is further applied to the bit line pair.
BL and I / O, and BL ′ and I / O ′ are connected via connection circuits 75 and 76, respectively. The connection between BL and the I / O line is controlled by the I / O connection signal φI / O.

Next, a writing method for storing a digital signal in one memory cell in the ferroelectric memory having such a structure will be described with reference to the timing chart of FIG.

It is assumed that the input / output lines I / O and I / O 'are previously supplied with a complementary potential corresponding to a signal to be written from the outside. For example, here, it is assumed that the potential of 5 V on the I / O line and the potential of 0 V on the I / O line are set as the potential corresponding to the information to be written.

The bit line pair is kept at the same potential in advance by a precharge circuit (not shown in FIG. 27). Before starting the write operation, the precharge signal φpre is released in a specific row corresponding to the address information indicating the position of the memory cell to be written, and BL and BL 'are separated from all voltage sources (floating state). )
To At this time, for bit line pairs in other rows,
Do not cancel the precharge state.

Then, BL and I / O and BL 'and I
In order to connect / O ', the φI / O signal is activated in a specific row based on the address to be written. As a result, BL in this row has the same potential as I / O and BL 'has the same potential as I / O'. That is, the potential corresponding to the information to be written is supplied to the bit line pair.

In order to stabilize the potential of the bit line pair introduced at this stage, the sense amplifier connected to this bit line pair is activated. At this time, the potential of BL is fixed to a voltage Vwrite that is high enough to invert the polarization of the capacitor by the activated sense amplifier.

Next, in a specific column corresponding to the address information indicating the writing position, the potential required to turn on the transistor is applied to the word line. As a result,
The MOS transistor connected to the word line in this column is o
The n state is set, and the capacitor and the bit line pair are connected. Naturally, in the other columns that do not correspond at this time, no signal is sent to the word line, so that the capacitor and the bit line remain electrically disconnected.

The potential of the drive line (DL) is first fixed at 0 V, and after a certain time elapses, a voltage Vwrite high enough to invert the polarization of the capacitor is applied to the drive line.
While being fixed at 0 V, the potential difference Vwrite generated between BL (potential: Vwrite) causes writing in the capacitor connected between BL and DL. At this time, B
Since L '(potential: 0) and DL (potential: 0) are the same potential,
No change occurs in the capacitor connected between BL 'and DL. Next, while giving Vwrite to DL, B
The potential difference −Vwrite generated between L ′ (potential: 0) causes writing in the capacitor connected between BL ′ and DL. At this time, BL (potential: Vwrite) and DL are equal potential, so BL No change occurs in the capacitor connected between DL and DL. As a result, the residual polarization due to the potential difference Vwrite is stored in the capacitor connected to the BL line, and the residual polarization due to the potential difference -Vwrite is stored in the capacitor connected to the BL 'line.

Thereafter, the word line signal is returned to the non-selected state, the sense amplifier is deactivated, and the bit line precharge is started to complete the write operation.

In the holding state after completion of the write operation,
BL and BL 'are held at the same potential by the precharge circuit. At this time, it is desirable to keep the potential of the bit line pair and the DL potential at the same potential. Further, since all the word lines are kept in the non-selected state, the capacitors are held in a state of being electrically separated from the bit line pair. The MOS transistor connected to the capacitor is OFF when power is not supplied, so that the information written in the capacitor in the form of remanent polarization can retain digital information even when power is not supplied to the memory circuit. it can.

Next, a method of reading the digital information stored in one memory cell in the memory circuit by such a method will be described with reference to the read timing chart of FIG.

First, the potential of the bit line pair is charged to a constant potential by using the precharge circuit. Next, the precharge is released and the bit line is set to the floating state. Next, one word line (WL) corresponding to the address
Is selected to turn on the MOS transistor connected to the word line. As a result, the capacitor of the memory cell and the bit line pair are electrically connected. At this time, the other transistors connected to the non-selected WLs are kept off.

Then, the drive line of the row corresponding to the address is selected, and the low potential Vread for reading is applied to the drive line. This adds Vread to the two capacitors in the memory cell. Remnant polarizations in different directions are accumulated in the two capacitors, but the remnant polarizations are not inverted by the low Vread voltage. Therefore, this read can be performed nondestructively without changing the polarization direction of the capacitor.

As described in the other embodiments, the capacitor according to the present invention has a leakage current value of 100 to 1000 times different depending on the direction of remanent polarization. Therefore, the value of the current flowing into the bit lines BL and BL 'differs depending on the polarization direction written in the capacitor. As a result, a slightly different potential is applied to the bit line pair.

When a sufficient potential difference occurs between the bit line pair, the potential of WL is returned to electrically disconnect the capacitor from the bit line pair. After this, the potential of the DL line is also restored. The capacitor and the bit line may be separated before activating the sense amplifier because the capacitor of the present invention can read information nondestructively. Such timing is not possible in the ferroelectric memory of the type that reads out the amount of charge stored in the capacitor.

Here, the sense amplifier is activated by selecting φact. As a result, the potential difference between the bit line pair is amplified and further fixed. At this time, since the transistor of the memory cell is already off, the amplified potential does not affect the polarization of the capacitor.

The potential read to the bit line can be transferred to I / O and I / O 'by sending a signal to φI / O. After the information is transferred to I / O and I / O ', the bit line pair and the input / output line pair are disconnected. After that, the bit line pair is returned to the precharged state again to the information holding state.

[0154]

As described in detail above, the present invention (claims 1 to 3)
According to the first aspect of 11), it is possible to improve the remanent polarization and the temperature dependence of the remanent polarization in a thin film capacitor used for a ferroelectric memory or the like without changing the composition of the dielectric film. For a dielectric material that does not exhibit ferroelectricity as a bulk material, depending on the composition of the dielectric material, it is possible to form a ferroelectric thin film with ferroelectricity and to have a large capacitance and good temperature dependence of the capacitance. And, for example, D
It is possible to realize a thin film capacitor that can be suitably used for RAM, and its industrial value is great.

According to the second aspect of the present invention (claim 12), the use of the epitaxial dielectric film causes an increase in the accumulated charge amount, induction of ferroelectricity, and variation in the capacitance of the capacitor between memory cells. It is possible to realize the reduction and the mutual diffusion between the dielectric film and the base film, and it is possible to realize a highly integrated semiconductor memory device, and the industrial value of the present invention is extremely large.

According to the third aspect of the present invention (claim 13), non-destructive reading can be performed by applying an electric field equal to or lower than the coercive electric field of the thin film capacitor, and the dielectric film / electrode junction having better matching. As a result, the writing of information according to the polarization direction of the dielectric film exhibiting ferroelectricity is performed.
In a so-called ferroelectric memory, it is possible to realize a semiconductor device with less fatigue such as a decrease in remanent polarization of a thin film capacitor and a decrease in coercive electric field due to writing and reading of information.

[Brief description of drawings]

FIG. 1 is a plan view and a vertical sectional view showing the structure of a thin film capacitor of the present invention.

2 is a characteristic diagram showing temperature dependence of capacitance of the thin film capacitors of Example 1 and Comparative Example 1. FIG.

FIG. 3 is a characteristic diagram showing polarization vs. electric field (PE) hysteresis curves of the thin film capacitors of Example 1 and Comparative Example 1.

FIG. 4 is a characteristic diagram showing temperature dependence of remanent polarization of the thin film capacitors of Example 1 and Comparative Example 1.

5A and 5B are a plan view and a vertical sectional view showing the structure of a MOS transistor in the semiconductor memory device of the present invention.

6A and 6B are a plan view and a vertical sectional view showing a structure of a thin film capacitor in a semiconductor memory device of the present invention.

FIG. 7 is a vertical cross-sectional view partially showing the structure of the semiconductor memory device of the present invention.

8 is an equivalent circuit diagram of the semiconductor memory device shown in FIG.

FIG. 9 is an equivalent circuit diagram of another semiconductor memory device of the present invention.

FIG. 10 is an X-ray diffraction pattern of a thin film of (Ba _0.44 Sr _0.56 ) TiO ₃ .

11 is a characteristic diagram showing the temperature dependence of the capacitance of the thin film capacitor of Example 2. FIG.

12 is a characteristic diagram showing polarization vs. electric field (PE) hysteresis curves of the thin film capacitors of Example 2 and Comparative Example 2. FIG.

FIG. 13 (Ba _0.44 Sr _0.56 ) Ti in Example 3
Shows the X-ray diffraction of the O ₃ thin film.

FIG. 14 is a diagram showing the bias electric field dependence of the relative permittivity of the thin film capacitor prepared in Example 3;

FIG. 15 is a graph of Example 3 (Ba _0.44 Sr.
_0.56) shows the temperature dependence of the measurement result of capacitance in TiO ₃ thin-film capacitor.

FIG. 16 is a sectional view of a dynamic access memory (DRAM) semiconductor memory device according to a fourth embodiment.

FIG. 17 is a step sectional view showing the method of manufacturing the DRAM of the fourth embodiment.

FIG. 18 is a sectional view showing a ferroelectric memory according to the fifth embodiment.

FIG. 19 is a step sectional view showing the method of manufacturing the ferroelectric memory according to the fifth embodiment.

FIG. 20 is a sectional view showing a ferroelectric memory according to the sixth embodiment.

FIG. 21 is a process sectional view showing the method of manufacturing the ferroelectric memory according to the sixth embodiment.

FIG. 22 is a sectional view showing the configuration of a thin film capacitor portion of a semiconductor memory device according to a seventh embodiment.

FIG. 23 is a diagram showing current-voltage characteristics of a capacitor in the seventh embodiment.

FIG. 24 is a diagram showing current-voltage characteristics of a capacitor in the eighth embodiment.

FIG. 25 is a diagram showing current-voltage characteristics of a capacitor in the ninth embodiment.

FIG. 26 is a diagram showing a circuit configuration of a ferroelectric memory according to the eleventh embodiment.

FIG. 27 is a timing chart for explaining a writing method in the eleventh embodiment.

FIG. 28 is a timing chart for explaining a reading method according to the eleventh embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Single crystal substrate 2 ... Lower electrode 3 ... Dielectric film 4 ... Upper electrode 5 ... Conductive substrate 10 ... Contact part 11 ... Si substrate 13 ... Word line 15 ... Bit line 16 ... Extraction electrode 22 ... Drive line 24 ... Switching Transistor 25 ... Thin film capacitor 26 ... Word line drive circuit 27 ... Drive line drive circuit 28 ... Sense amplifier 41 ... First conductivity type semiconductor substrate 44 ... Word line 46 ... Second conductivity type impurity diffusion layer 48 ... Bit line 50 ... Polishing stop Layer 51 ... Single crystal silicon storage node 52 ... Epitaxial barrier metal 53 ... Epitaxial lower electrode 54 ... Epitaxial dielectric film 55 ... Upper electrode 56 ... Epitaxial dielectric film 57 ... Single crystal silicon layer 58 ... Calcium fluoride film 60 ... Aluminum wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/822 7735-4M H01L 27/10 621 Z (72) Inventor Takashi Kawakubo Kawasaki City, Kanagawa Prefecture Komukai-shi Toshiba-cho 1-share company in Toshiba Research and Development Center (72) Inventor Shin Fukushima Komukai-shi, Kawasaki-shi Kanagawa-shi 1-house in Toshiba Research and Development Center (72) Inventor Kenya Sano Kanagawa 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, Japan Stock company Toshiba Research and Development Center

Claims (13)

[Claims] 1. A conductive substrate made of a conductive material having at least a surface having a crystal structure belonging to either a tetragonal (001) plane or a cubic system, and a tetragonal crystal epitaxially grown on the conductive substrate. A thin film capacitor comprising a dielectric film made of a dielectric material having a perovskite type crystal structure belonging to one of a cubic system and a cubic system, and an upper electrode formed on the dielectric film. When the original Curie temperature is below 150 ℃,
Original lattice constant a _d of dielectric material expressed by a-axis length of perovskite type crystal structure and original lattice constant of conductive material expressed by a-axis length of either tetragonal or cubic crystal structure A thin film capacitor, wherein a _s and the following relational expression are satisfied. 1.002 ≤ a _d / a _s ≤ 1.015 2. A conductive substrate made of a conductive material having at least a surface having a crystal structure belonging to either a tetragonal (001) plane or a cubic system, and a tetragonal crystal epitaxially grown on the conductive substrate. A thin film capacitor comprising a dielectric film made of a dielectric material having a perovskite type crystal structure belonging to one of a cubic system and a cubic system, and an upper electrode formed on the dielectric film. Is a general formula ABO ₃ (where A is B
at least 1 selected from the group consisting of a, Sr, and Ca
Seed, B is Ti, Zr, Hf, Sn, (Mg _1/3 N
b _2/3 ), (Mg _1/3 Ta _2/3 ), (Zn _1/3 N
b _2/3 ), (Zn _1/3 Ta _2/3 ), (Mg _1/2 T
e _1/2 ), (Co _1/2 W _1/2 ), (Mg _1/2 W _1/2 ),
(Mn _1/2 W _1/2 ), (Sc _1/2 Nb _1/2 ), (Mn
_1/2 Nb _1/2 ), (Sc _1/2 Ta _1/2 ), (Fe _1/2 N
b _1/2 ), (In _1/2 Nb _1/2 ), (Fe _1/2 T
a _1/2 ), (Cd _1/3 Nb _2/3 ), (Co _1/3 N
b _2/3 ), (Ni _1/3 Nb _2/3 ), (Co _1/3 T
a _2/3 ), (at least one selected from the group consisting of Ni _1/3 Ta _2/3 )), and a dielectric represented by the a-axis length of a perovskite-type crystal structure. The intrinsic lattice constant a _{d of the} conductive material and the intrinsic lattice constant a _s of the conductive material represented by the a-axis length of either a tetragonal or cubic crystal structure satisfy the following relational expression: And thin film capacitors. 1.002 ≤ a _d / a _s ≤ 1.015 3. The original Curie temperature of the dielectric material is 150 ° C.
The thin film capacitor according to claim 2, wherein: 4. The thin film capacitor according to claim 1, wherein the conductive substrate comprises a base material and a thin film of a conductive material formed on the base material. 5. A (00) tetragonal system at least on the surface of the substrate.
1) The thin film capacitor according to claim 4, which has a crystal structure belonging to one of a plane and a cubic system. 6. The thin film capacitor according to claim 4, wherein the thin film of the conductive material has a thickness of 80 nm or less. 7. A first electrode, a dielectric film made of a dielectric material having a perovskite type crystal structure belonging to either a tetragonal system or a hexagonal system epitaxially grown on the first electrode, and the dielectric film. A thin film capacitor comprising a second electrode formed on a body film, wherein the dielectric film has a film thickness of 15 nm or more, and the C-axis length Ce of the dielectric material after epitaxial growth and the C-axis length Ce
And a corresponding tetragonal C-axis length or hexagonal a-axis length Co of the dielectric material before the epitaxial growth satisfying the following relational expression. Ce / Co ≧ 1.02 8. The dielectric material has the general formula (Ba _x Sr _1-x ) T.
The thin film capacitor according to claim 1, wherein the thin film capacitor has a perovskite composition represented by iO ₃ (0.30 ≦ x ≦ 0.90). 9. The thin film capacitor according to claim 1, wherein the film thickness of the dielectric film is 70 nm or more. 10. The thin film according to claim 1, wherein the Curie temperature inherent to the dielectric material is room temperature or lower, and the dielectric film made of this dielectric material exhibits ferroelectricity at room temperature. Capacitors. 11. A memory cell comprising the thin film capacitor according to claim 1, and a switching transistor connected to the thin film capacitor, the memory cells being arranged in a matrix. Semiconductor memory device. 12. A thin film comprising a first electrode, a dielectric film made of a crystal positive dielectric material epitaxially grown on the first electrode, and a second electrode formed on the dielectric film. In a semiconductor memory device in which memory cells each including a capacitor and a switching transistor connected to the thin film capacitor are arranged in a matrix on a silicon substrate, an insulating film having a partial opening on the silicon substrate is provided. A (100) oriented silicon layer is grown and
A semiconductor memory device comprising a dielectric film of the thin film capacitor formed on an oriented silicon layer. 13. The semiconductor memory device according to claim 11, wherein the dielectric film of the thin film capacitor exhibits ferroelectricity at room temperature, and an electric field higher than a coercive electric field is applied to the dielectric film to form a dielectric film.・ Information is written by utilizing the fact that the interface resistance of the electrode changes depending on the polarization direction of the dielectric film,
A semiconductor memory device, wherein nondestructive reading of information is performed by utilizing a change in leak current value when an electric field equal to or less than a coercive electric field is applied.