JPH08139201A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: To reduce a contact resistance for wiring to drop an operating voltage by constituting a contact region for electrically connecting a gate electrode of a MOS transistor and a source/drain region of another MOS transistor with partially overlapped shallow diffused region and deep diffused region. CONSTITUTION: A contact region C for electrically connecting a gate electrode 20 of a MOS transistor A and a source/drain region 44 of a MOS transistor B is constituted by a shallow first contact diffused region 41 and a second contact diffused region 40 which is deeper than and is partially overlapping with the first contact diffused region 41. Therefore, the first contact diffused region 41 limits the depth and expansion of the second contact diffused region 40. Thereby, a contact resistance between a wiring 60 formed of a second polycrystalline silicon film and a semiconductor substrate 31 can be lowered and an operating voltage can also be dropped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode of one MOS transistor and an MO transistor of the other formed on a semiconductor substrate.
The present invention relates to a structure of a contact region of a semiconductor substrate formed to connect with a source / drain region of an S transistor and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A semiconductor device has a plurality of semiconductor elements formed on a semiconductor substrate. The semiconductor elements are usually electrically connected in some form to form a semiconductor integrated circuit. For example, when the gate of the first MOS transistor and one of the source / drain regions of the second MOS transistor are electrically connected to each other so as to increase the degree of integration, the polycrystalline silicon film forming the gate is used as the wiring. It is performed by connecting the gate of one transistor to a contact region (hereinafter referred to as a DC (direct contact) region) electrically connecting to one of the other source / drain regions. First, a semiconductor device having a conventional DC portion (contact region) will be described with reference to FIG. The figure is a cross-sectional view of the semiconductor device. As the semiconductor substrate of this semiconductor device, for example, an n-type silicon semiconductor substrate 1 is used, and a p well 2 is formed in the surface region thereof. A field oxide film 3 is formed in the element isolation region on the main surface of the semiconductor substrate 1 by the LOCOS method or the like, and first and second NMOS transistors A and B are formed in the element region.

Source / drain regions 14 of MOS transistors A and B are formed in the surface region of the semiconductor substrate 1. The source / drain regions of the MOS transistor A are formed on the front surface and the back surface of the drawing sheet, and are not shown. A silicon oxide film 4 to be a gate oxide film having a film thickness of about 10 nm is formed on the source / drain regions 14 and the semiconductor substrate between them. A gate electrode 7 is formed on the source / drain region 14 via the gate oxide film 4.
1, 72 are formed. The gate electrode 71 of the MOS transistor A is connected to the polycrystalline silicon wiring 73, and this wiring 73 is formed on the surface region of the semiconductor substrate 1 by D.
It is in contact with the C region 9. A metal wiring 18 such as aluminum is formed on the semiconductor substrate 1 with an interlayer insulating film 17 interposed therebetween. The metal wiring 18 is covered with an insulating protective film 19 such as Si ₃ N ₄ . Next, referring to FIGS. 12 to 16, used in a memory cell of SRAM,
A method of forming a semiconductor device having a conventional structure in which elements are connected to each other through a diffusion region of a silicon substrate will be described. A p well 2 is formed on an n-type silicon semiconductor substrate 1, and a field oxide film 3 for element isolation is formed in a semiconductor element isolation region. Then, a gate oxide film 4 such as SiO ₂ is formed in the element region of the semiconductor substrate 1.

Subsequently, a photoresist pattern 5 having a contact opening 51 for opening the silicon semiconductor substrate 1 and a gate of a MOS transistor to be formed later is formed (FIG. 12). After that, the gate oxide film 4 is etched by wet etching using the photoresist pattern 5 as a mask to form a contact opening 6. Next, the photoresist pattern 5 is removed (FIG. 13). Then, a polycrystalline silicon film 7 having a film thickness of about 400 nm is formed on the semiconductor substrate 1, and phosphorus diffusion 8 is further performed by gas diffusion or the like to pass through the contact opening 6 to form an N ⁺ region in the p well 2. A DC region (phosphorus diffusion region) 9 is formed (FIG. 14). Then, a photoresist pattern 10 is formed for forming the gate of the MOS transistor, and the polycrystalline silicon film 7 is etched by the reactive ion etching (RIE) method to contact the gates 71 and 72 of the MOS transistor and the DC region 9. Wiring 7
3 is formed. At this time, since the polycrystalline silicon film 7 and the silicon substrate 1 are made of the same material, the silicon semiconductor substrate 1 is also etched at the contact opening portion 6 due to the over-etching of the polycrystalline silicon film 7.
1 is generated and a part of the DC region 9 is etched (FIG. 15).

Subsequently, the photoresist pattern 10 is removed, and then arsenic ions 12 are accelerated with an acceleration voltage of 50 ke to form the source / drain regions of the MOS transistor.
Arsenic 13 is implanted into the source / drain formation region under the conditions of V and a dose amount of 5 × 10 ¹⁵ cm ⁻² (FIG. 16). The arsenic 13 injected into the semiconductor substrate 1 is thermally diffused and the source /
The drain region 14 is formed. Subsequently, an interlayer insulating film 17 such as SiO ₂ is formed so as to cover the gate electrodes 71 and 72 and the wiring 73, and a metal wiring 18 such as aluminum having a predetermined pattern is formed on the interlayer insulating film 17. An insulating protective film 19 such as Si ₃ N ₄ is formed on the semiconductor substrate 1 so as to cover the metal wiring 18 to obtain a semiconductor device (see FIG. 11).

[0006]

As described above, according to the prior art, the polycrystalline silicon film 7 formed on the semiconductor substrate 1 is used.
When this is etched, this semiconductor substrate 1 is also etched together, and a part of the DC region 9 which is a phosphorus diffusion region is also etched. Therefore, the resistance 15 of the DC region 9
Is increased, which is a serious problem in circuit operation. Further, when the polycrystalline silicon film 7 has a thickness of 400 nm and 100% over-etching is performed, the depth of the substrate hole 11 becomes 40.
It may reach 0 nm, and the resistance 15 of the phosphorus diffusion layer 9 may increase from several tens of ohms to several thousand ohms. Especially S
An increase in resistance in the memory cell of RAM loses stability of the cell and leads to a defect. Further, the substrate hole 11 part is subjected to ion bombardment by the reactive ion etching, so that the crystal defect 16 is induced. In a SRAM memory cell, this crystal defect 16
Is a leak path to the p-well 2 region, which leads to loss of cell stability, which is a serious problem not only in initial failure but also in reliability. The present invention has been made under such circumstances, and a contact region formed on a semiconductor substrate for electrically connecting the gate electrode of one MOS transistor and the source / drain region of the other MOS transistor. (EN) Provided is a semiconductor device having a stable resistance in the (DC region), eliminating a substrate hole at the time of forming a gate electrode, reducing a diffusion layer resistance, and eliminating generation of a crystal defect due to ion bombardment of RIE etching. It is an object of the present invention to provide a method for manufacturing a semiconductor device having high yield and high reliability, which is formed in the above.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate, first and second MOS transistors formed on the main surface of the semiconductor substrate, and a first formed on the semiconductor substrate and in contact with one of source / drain regions of the second MOS transistor Contact area of
A second contact region that partially overlaps with the first contact region and has a depth from the semiconductor substrate main surface that is deeper than a depth of the first contact region from the semiconductor substrate main surface; The first feature is that the gate electrode of the MOS transistor is integrally formed with a wiring that is in contact with the first and second contact regions.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate oxide film on a main surface of a semiconductor substrate and a first step of covering the entire main surface of the semiconductor substrate with the gate oxide film.
Forming a polycrystalline silicon film, forming a first resist pattern having an opening on the first polycrystalline silicon film, and using the first resist pattern as a mask. Etching the crystalline silicon film to form an opening having a diameter larger than that of the opening of the first resist pattern; etching the gate oxide film using the first resist pattern as a mask; Forming an opening having a diameter smaller than that of the opening of the first polycrystalline silicon film; removing the first resist pattern; and using the etched first polycrystalline silicon film as a mask, A first polycrystalline silicon film is formed on the semiconductor substrate below the opening;
Forming a first contact region by ion-implanting a conductive type first impurity; and a second polycrystalline silicon film so as to cover the entire main surface of the semiconductor substrate with the first polycrystalline silicon film. And a gate oxide film having the opening formed therein as a mask, the first conductivity type is formed on the semiconductor substrate below the opening of the gate oxide film via the second polycrystalline silicon film. The second impurity of
And a second resist pattern is formed on the second polycrystalline silicon film, and the second polycrystalline silicon film is used as a mask to form the gate oxide film. By patterning the first and second polycrystalline silicon films so as to cover the opening of the first and second MOS transistors, the first and second MOS transistors are connected to the gate electrodes of the first and second MOS transistors and are connected to the first and second MOS transistors. Forming a wiring connected to the first and second contact regions, removing the second resist pattern, and using the patterned first and second polycrystalline silicon films as a mask Ion-implanting a third conductivity type impurity,
And the step of forming the source / drain regions of the MOS transistor. The diffusion rate of the first impurity of the first conductivity type may be lower than the diffusion rate of the second impurity of the first conductivity type. Arsenic may be used as the first impurity of the first conductivity type and phosphorus may be used as the second impurity of the first conductivity type.

The semiconductor device manufacturing method of the present invention is
Forming a gate oxide film on the main surface of the semiconductor substrate; forming a first polycrystalline silicon film on the entire main surface of the semiconductor substrate so as to cover the gate oxide film;
Forming a first resist pattern having an opening on the polycrystalline silicon film, and etching the first polycrystalline silicon film by using the first resist pattern as a mask to form the first resist pattern. Forming an opening having a diameter larger than the diameter of the opening; etching the gate oxide film using the first resist pattern as a mask to make the diameter smaller than the diameter of the opening of the first polycrystalline silicon film; Forming an opening, a step of removing the first resist pattern, and a step of removing the first resist pattern under the opening of the first polycrystalline silicon film using the etched first polycrystalline silicon film as a mask. Forming a contact region by ion-implanting a first impurity of a first conductivity type into the semiconductor substrate; and forming the first polycrystalline silicon on the entire main surface of the semiconductor substrate. A step of forming a second polycrystalline silicon film so as to cover the silicon film, and forming a second resist pattern on the second polycrystalline silicon film, and using the second resist pattern as a mask, By patterning the first and second polycrystalline silicon films such that the second polycrystalline silicon film covers the opening of the gate oxide film, the gate electrodes of the first and second MOS transistors and the first and second MOS transistors are patterned. A step of forming a wiring connected to the gate electrode of the first MOS transistor and connected to the contact region; a step of removing the second resist pattern; and a step of removing the patterned first and second polycrystalline silicon films. As a mask, second impurities of the first conductivity type are ion-implanted to form the source / drain regions of the first and second MOS transistors. That and a degree and second features. The first polycrystalline silicon film may be etched by isotropic etching, and the gate oxide film may be etched by anisotropic etching.

[0010]

Since the DC region is composed of a shallow diffusion region and a deep diffusion region which are partially overlapped with each other, the contact resistance of this region is reduced, and when it is applied to a memory, for example,
Decrease the minimum value of power supply voltage. Further, according to the present invention, the size of the contact opening of the first polycrystalline silicon film is larger than the size of the contact opening of the gate silicon oxide film, and the gate of the contact opening is formed by the subsequent first arsenic ion implantation. Arsenic is also implanted just below the oxide film,
Since the arsenic diffusion region is formed, the second polycrystalline silicon film can be patterned so as to cover the contact opening, and when the second polycrystalline silicon film is etched, there is no occurrence of substrate holes, and the second polycrystalline silicon film can be formed. There is also no ion damage during etching of the polycrystalline silicon film. Further, when the stacked gate oxide film and the polycrystalline silicon film are etched to form the contact openings, the polycrystalline silicon film is opened by isotropic etching and the gate oxide film is opened by anisotropic etching. By doing so, contact openings having different opening diameters are easily formed.

[0011]

Embodiments of the present invention will be described below with reference to the drawings (FIGS. 1 to 10). First, referring to FIG. 1, DC
A semiconductor device having a portion (contact region) will be described.
The figure is a cross-sectional view of a semiconductor device. For example, an n-type silicon semiconductor substrate 31 is used as a semiconductor substrate of this semiconductor device, and a p well 32 is formed in the surface region thereof.
The LOCO is formed in the element isolation region on the main surface of the semiconductor substrate 31.
A field oxide film 33 is formed by the S method or the like, and first and second NMOS transistors A and B are formed in the element region. Source / drain regions 44 of the MOS transistors A and B are formed in the surface region of the semiconductor substrate 31, respectively. The source / drain regions of the MOS transistor A are formed on the front surface and the back surface of the drawing sheet, and are not shown. A silicon oxide film serving as a gate oxide film 34 having a film thickness of about 10 nm is formed on the source / drain regions 44 and the semiconductor substrate 31 between them. Gate electrodes 20 and 30 are formed between the source / drain regions 44 with a gate oxide film 34 interposed therebetween.

The gate electrode 20 of the MOS transistor A is connected to the polycrystalline silicon wiring 60, and this wiring 60 is in contact with the DC region formed in the surface region of the semiconductor substrate 1. In the semiconductor device of this embodiment, the DC region is shallow and the first contact diffusion region 41 is deeper than the first contact diffusion region 41, and the second contact region 41 partially overlaps the first contact diffusion region 41.
Of the contact diffusion region 40. A metal wiring 18 made of aluminum or the like is formed on the semiconductor substrate 31 via an interlayer insulating film 45 made of SiO ₂ . The metal wiring 18 is Si ₃ N ₄ insulating protection film 4 such as
7 is covered. It is also possible to further form a second metal wiring on the metal wiring 18. In that case, the metal wiring 18 is used as the first metal wiring, and the second metal wiring is formed thereon via the interlayer insulating film. Then, the protective insulating film is formed thereon. The first contact diffusion region 41 in the DC region limits the depth and spread of the second contact diffusion region 40 more than the conventional contact diffusion region 9 (see FIG. 11). Then, the first contact diffusion region 41 has the wiring 6 made of the second polycrystalline silicon film.
The contact resistance between 0 and the semiconductor substrate 31 is reduced.

This contact resistance, which has been conventionally 500 Ω, is reduced to about 300 Ω, and as a result, the stability of the SRAM cell is improved and the SRAM cell can be operated at a low power supply voltage. That is, conventionally, the minimum value of the power supply voltage is 3.5.
Although it was about V, it became possible to operate at 3V,
The operating margin expands. In addition, since the impurity arsenic forming the first contact diffusion region 41 suppresses the phosphorus diffusion performed when forming the second contact diffusion region 40, the second contact diffusion region 40 becomes shallower than the conventional one. In addition, since the lateral spread becomes small, the SRAM cell can be miniaturized. 1st and 2nd MO of FIG.
The S transistors A and B and the contact region C are applied to, for example, an SRAM memory having an NMOS structure using a high resistance polycrystalline silicon load resistor shown in FIG. This memory is composed of four NMOS transistors A, B, D and E and two polycrystalline silicon resistors R1 and R2.
The gate electrode of the MOS transistor A is connected to one of the source / drain regions of the MOS transistor B via the DC region C, and the other of the source / drain regions is connected to the bit line.

The gate electrode of the MOS transistor B is connected to the word line. This SRAM is for performing data transfer of reading and writing with a bit line through a pair of access transistors B and E having a word line as a gate input. The word line is an output of the row decoder circuit, is wired by a low resistance polycrystalline silicon film, becomes 1 level only when a memory cell is selected, and turns on the access transistors B and E. The present invention can be applied not only to this type of SRAM, but also to the SRAM having the complete CMOS structure shown in FIG. 9, for example.

Next, a method of manufacturing a semiconductor device will be described with reference to FIGS. The figure shows the gate electrode of one MOS transistor and the source / source of the other MOS transistor.
FIG. 7 is a cross-sectional view showing a manufacturing process in the case where one of the drain regions is connected via a diffusion region (DC region) in the p well. A p well 32 is formed on the n-type silicon semiconductor substrate 31. Then, a field oxide film 33 is formed in the element isolation region of the semiconductor substrate 31, and, for example, a film thickness of 1 is formed in the element region.
A gate oxide film 34 of SiO ₂ or the like having a thickness of about 0 nm is formed. Then, the first polycrystalline silicon film 35 is LPCVD-processed.
(Low Pressure Chemical Vapor Deposition) method 100
Then, a photoresist pattern 36 having a contact opening 48 for forming a contact opening is formed by photolithography (FIG. 3).

Subsequently, the first polycrystalline silicon film 35 is isotropically etched by isotropic etching such as CDE (Chemical Dry Etching) method or wet etching method to form the first polycrystalline silicon film 35. The opening is made larger than the opening of the photoresist pattern 36, for example, about 40 nm. Further, the gate oxide film 34 is etched by an anisotropic etching method such as RIE (Reactive Ion Etching) using the photoresist pattern 36 as a mask to open a contact opening 49 of the first polycrystalline silicon film 35, and further this contact opening. A contact opening 50 of the gate oxide film 34 is opened in the portion 49 (FIG. 4). As shown in FIG. 4, the first photoresist film 36 is isotropically etched with the same photoresist pattern 36, and the gate oxide film 34 is anisotropically etched.
The size of each contact opening 49 is larger than the size of the opening 50 of the gate oxide film, and the position of each contact opening is determined by self-alignment.

Then, the photoresist pattern 36 is removed, and arsenic ions (As ⁺ ) 37 are accelerated with an acceleration voltage of 30 ke.
Implantation is performed under the conditions of V and a dose amount of 1 × 10 ¹⁵ cm ⁻² . By this ion implantation, arsenic 371 is implanted into the p well 32 from the contact opening 49 of the first polycrystalline silicon film 35. At this time, the ion implantation ranges (Projected Range) of arsenic ions (As ⁺ ) to the polycrystalline silicon film and the silicon oxide film of the gate oxide film under the above conditions are 21.5 nm and 17.3 nm, respectively. The ions do not penetrate the first polycrystalline silicon film 35 but penetrate the exposed portion of the gate oxide film 34 and are implanted into the p well 32 in the size of the opening of the first polycrystalline silicon film 35. When the gate oxide film thickness and the first polycrystalline silicon film thickness are changed, the accelerating voltage for ion implantation is adjusted to implant arsenic into the p-well 32 at the size of the opening of the first polycrystalline silicon film 35. (Fig. 5).

Subsequently, the second polycrystalline silicon film 38 is formed,
For example, by the LPCVD method at a deposition temperature of about 650 ° C.
Deposited to a thickness of about 00 nm, and further phosphorus 39 by gas diffusion.
Is diffused from the surface of the p well 32 under the condition of 850 ° C. for 30 minutes to form a phosphorus diffusion region which is the second contact region 40. At this time, the p-well 32 is formed by the first arsenic ion implantation.
The arsenic 371 implanted into the substrate is thermally diffused at about 650 ° C. to form a first arsenic diffusion region which is the first contact region 41. Since the impurity is phosphorus, the second contact region 40 is deeper than the first contact region 41 containing arsenic, which has a smaller diffusion rate than phosphorus, as an impurity (FIG. 6).

Then, a photoresist pattern 42 is formed on the second polycrystalline silicon film 38, and then the first and second polycrystalline silicon films 35 and 38 are formed by RIE using the photoresist pattern 42 as a mask. Is etched to form a wiring 60 that contacts the gate electrodes 20 and 30 of the MOS transistor and the first and second contact regions 40 and 41. At this time, the first and second polycrystalline silicon films 35 and 38, which are gate electrodes and wirings, cover the entire contact openings 50 of the gate oxide film 34, and their edges are gate oxide on the first arsenic diffusion layer 41. The first and second polycrystalline silicon films 35, 3 so that they are on the film 34.
8 is patterned (FIG. 7). Then, using the patterned first and second polycrystalline silicon films 35 and 38 as a mask, arsenic ions (As ⁺ ) 43 are accelerated at a voltage of 50 k.
Second arsenic ion implantation is performed under the conditions of eV and a dose amount of 5 × 10 ¹⁵ cm ⁻² , and arsenic 431 is implanted into the p well 32 (FIG. 8). Then, arsenic 431 implanted in the p-well
Are thermally diffused to form a second arsenic diffusion region. This region is the source / drain region 44 of the MOS transistor.
Used as. Gate electrode 2 on semiconductor substrate 31
The layers 0 and 30 and the wiring 60 are covered with the interlayer insulating film 45. A metal wiring 46 of aluminum or the like is formed in a predetermined pattern on the interlayer insulating film 45. Semiconductor substrate 31
An insulating protective film 47 is formed on the uppermost layer (see FIG. 1).

Next, the structure of the contact region and its effect will be described with reference to the sectional view of the semiconductor device shown in FIG. 10A is a partial sectional view of FIG. 5, and FIGS. 10B and 10C are partial sectional views of FIG. In FIG. 10A, arsenic ions 37 are implanted into the p-well 32 of the semiconductor substrate from the contact opening 49 of the first polycrystalline silicon film 35 under the conditions described above, and arsenic 371 is introduced into the surface region of the semiconductor substrate. To do. In this state, the second
Is deposited by LPCVD so as to cover the contact openings 49. Since the deposition temperature during this deposition is about 650 ° C., the arsenic 371 in the p-well 32 is activated to form the n-type arsenic diffusion region 41 which is the first contact region. Next, FIG.
As shown in (c), the phosphorus 39 is thermally diffused to form the second contact region 40. This phosphorus diffusion is
When the POCl ₃ gas is heat-treated at 850 ° C. for 30 minutes, phosphorus 39 is generated in the contact opening 5 of the gate oxide film 34.
A phosphorus diffusion region 40, which is a first contact region, is formed by diffusing from 0 to the p well of the semiconductor substrate.

Since the first contact region is not formed in the conventional method, the phosphorus diffusion region 9 is deeper than the phosphorus diffusion region 40 of the present invention. The depth D1 of the first contact region (arsenic diffusion region) 41 of the present invention from the surface of the semiconductor substrate is
0.2 μm, second contact region (phosphorus diffusion region) 4
The depth D2 of 0 from the surface of the semiconductor substrate is 0.4 μm. On the other hand, the depth D3 from the semiconductor substrate surface of the contact region (phosphorus diffusion region) 9 without the shallow first contact region according to the conventional method is as deep as 0.6 μm. This is because the arsenic atoms forming the first contact region can sufficiently suppress the diffusion of phosphorus into the semiconductor substrate during phosphorus diffusion. In the above embodiment, the phosphorus 3 is deposited after the second polycrystalline silicon film 38 is deposited.
9 is thermally diffused to form a phosphorus diffusion region (second contact region)
Although 40 is formed, the present invention is not limited to this, and phosphorus may be implanted by an ion implantation method to form a phosphorus diffusion region. Further, the phosphorus diffusion and the ion implantation of phosphorus may be omitted, and the formation of the phosphorus diffusion region 40 may be omitted. Further, in the above-described embodiment, the second polycrystalline silicon film covers the entire contact opening 50 of the gate oxide film 34, but the present invention is not limited to this, and it may be covered only in the direction of current flow in circuit operation. .

In the above embodiment, the method of forming the n-type connection on the p-well has been described, but the p-type connection may be formed on the n-well. At this time, the impurities introduced into the n-well become p-type impurities such as boron. Further, in the above-mentioned embodiment, the connection of the gate of one MOS transistor and the source or drain of the other MOS transistor has been described. However, without being particular about this, the elements or the wirings or the elements via the diffusion region in the well May be connected between the wiring and the wiring.

[0023]

As described above, the semiconductor device of the present invention is
Since the shallow contact region that partially overlaps the second contact region is provided in the C region (contact region), the contact resistance with the wiring in this region is reduced, and the operating voltage can be reduced. According to the method of manufacturing a semiconductor device of the present invention, the size of the contact opening of the first polycrystalline silicon film is larger than the size of the contact opening of the gate oxide film, and the contact opening is formed by the first arsenic ion implantation. Since arsenic is also implanted under the gate oxide film to form the first arsenic diffusion region, the second polycrystalline silicon film can be patterned so as to cover the contact opening, and the substrate hole during etching of the polycrystalline silicon film can be formed. Does not occur, there is no increase in resistance in the phosphorus diffusion region, which is a problem of the prior art, and there is no ion damage during etching of the second polycrystalline silicon film, and no crystal defects occur, resulting in high yield. A highly reliable semiconductor device can be provided. Further, when the stacked gate oxide film and the polycrystalline silicon film are etched to form the contact openings, the polycrystalline silicon film is opened by isotropic etching and the gate oxide film is opened by anisotropic etching. By doing so, contact openings having different opening diameters are easily formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a circuit diagram of an SRAM according to the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a sectional view of a manufacturing process of a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device of the present invention.

FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a cross-sectional view of the manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a circuit diagram of an SRAM according to the present invention.

FIG. 10 is a partial cross-sectional view of a semiconductor device of the present invention.

FIG. 11 is a cross-sectional view of a conventional semiconductor device.

FIG. 12 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 13 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 14 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 15 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 16 is a sectional view of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

1, 31 Semiconductor substrate 2, 32 p well 3, 33 Field oxide film 4, 34 Gate oxide film 5, 10, 36, 42 Photoresist pattern 6, 50 Gate oxide contact opening 7 Polycrystalline silicon film 8, 39 Phosphorus 9 DC region (contact region) 11 Substrate hole 12, 37, 43 Arsenic ion 13, 371, 431 Arsenic 14 Source / drain region (arsenic diffusion region) 15 Diffusion layer resistance 16 Crystal defect 17, 45 Interlayer insulating film 18, 46 Metal wiring 19, 47 Insulation protective film 20, 30, 71, 72 Gate electrode of MOS transistor 35 First polycrystalline silicon film 38 Second polycrystalline silicon film 40 Second contact region (phosphorus diffusion region) 41 First Contact region (first arsenic diffusion region) 44 source / drain region (second arsenic diffusion region) 8,51 contact openings 60,73 interconnect photoresist pattern contact opening 49 first polycrystalline silicon film

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/768 21/8244 27/11 H01L 27/10 381

Claims (6)

[Claims] 1. A semiconductor substrate, and first and second MOSs formed on the main surface of the semiconductor substrate.
A first transistor formed on the semiconductor substrate and in contact with one of source / drain regions of the second MOS transistor;
A second contact region partially overlapping the first contact region and having a depth from the semiconductor substrate main surface that is deeper than a depth of the first contact region from the semiconductor substrate main surface. A semiconductor device comprising: a wiring formed integrally with a gate electrode of the first MOS transistor and in contact with the first and second contact regions. 2. A step of forming a gate oxide film on a main surface of a semiconductor substrate; a step of forming a first polycrystalline silicon film on the entire main surface of the semiconductor substrate so as to cover the gate oxide film; Forming a first resist pattern having an opening on the first polycrystalline silicon film, etching the first polycrystalline silicon film using the first resist pattern as a mask, and forming the first resist pattern Forming an opening having a diameter larger than the diameter of the opening of the first polycrystalline silicon film, and etching the gate oxide film using the first resist pattern as a mask to make the opening smaller than the diameter of the opening of the first polycrystalline silicon film. A step of forming an opening having a diameter, a step of removing the first resist pattern, and a step of using the etched first polycrystalline silicon film as a mask. Forming a first contact region by ion-implanting a first impurity of a first conductivity type into the semiconductor substrate below the opening of the polycrystalline silicon film; and forming a first contact region on the entire main surface of the semiconductor substrate. Forming a second polycrystalline silicon film so as to cover the polycrystalline silicon film, and using the gate oxide film in which the opening is formed as a mask, the semiconductor under the opening in the gate oxide film. A step of forming a second contact region by introducing a second impurity of the first conductivity type into the substrate through the second polycrystalline silicon film, and forming a second contact region on the second polycrystalline silicon film. A resist pattern is formed, and using the second resist pattern as a mask, the first and second polycrystalline silicon films are patterned so that the second polycrystalline silicon film covers the opening of the gate oxide film. To do The gate electrodes of the first and second MOS transistors and said first MOS
Forming a wiring connected to a gate electrode of a transistor and connected to the first and second contact regions; removing the second resist pattern; the patterned first and second polycrystalline And a step of implanting a third impurity of the first conductivity type with the silicon film as a mask to form the source / drain regions of the first and second MOS transistors. Manufacturing method. 3. The semiconductor device according to claim 2, wherein the diffusion rate of the first impurity of the first conductivity type is lower than the diffusion rate of the second impurity of the first conductivity type. Production method. 4. The semiconductor device according to claim 3, wherein the first impurity of the first conductivity type is arsenic, and the second impurity of the first conductivity type is phosphorus. Production method. 5. A step of forming a gate oxide film on a main surface of a semiconductor substrate; a step of forming a first polycrystalline silicon film on the entire main surface of the semiconductor substrate so as to cover the gate oxide film; Forming a first resist pattern having an opening on the first polycrystalline silicon film, etching the first polycrystalline silicon film using the first resist pattern as a mask, and forming the first resist pattern Forming an opening having a diameter larger than the diameter of the opening of the first polycrystalline silicon film, and etching the gate oxide film using the first resist pattern as a mask to make the opening smaller than the diameter of the opening of the first polycrystalline silicon film. A step of forming an opening having a diameter, a step of removing the first resist pattern, and a step of using the etched first polycrystalline silicon film as a mask. Forming a contact region by ion-implanting a first impurity of a first conductivity type into the semiconductor substrate below the opening of the polycrystalline silicon film; and forming the first polycrystal on the entire main surface of the semiconductor substrate. Forming a second polycrystalline silicon film so as to cover the silicon film; forming a second resist pattern on the second polycrystalline silicon film; and using the second resist pattern as a mask, By patterning the first and second polycrystalline silicon films so that the second polycrystalline silicon film covers the opening of the gate oxide film, the gate electrodes of the first and second MOS transistors and the First MOS
Forming a wiring connected to the gate electrode of the transistor and connected to the contact region; removing the second resist pattern; and using the patterned first and second polycrystalline silicon films as a mask, And a step of implanting second impurities of the first conductivity type to form the source / drain regions of the first and second MOS transistors. 6. The method according to claim 2, wherein the first polycrystalline silicon film is etched by isotropic etching, and the gate oxide film is etched by anisotropic etching. A method for manufacturing a semiconductor device according to any one of the above.