JPH08139149A - Evaluation method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To obtain an evaluation technology for semiconductor integrated circuit device having an upper layer wiring formed on an lower layer wiring connecting semiconductor elements through an interlayer insulation film in which the cause of defect arising from the semiconductor element can be investigated (analyzed). CONSTITUTION: The method for evaluating a semiconductor integrated circuit device comprises a step for removing an upper layer wiring Ist, a step for making an opening 4A through an interlayer insulation film 4 to partially expose the surface of a lower layer wiring 3, and a step for forming a conductor connected with the part of the surface of the lower layer wiring 3 and an evaluation electrode pad 8B connected with a conductor 8A on the interlayer insulation film 4. The method further comprises a step for evaluating the electric characteristics of a semiconductor element by touching the surface of the evaluation electrode pad 8B with a probe needle or irradiating the surface of the evaluation electrode pad 8B with an electron beam.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for evaluating a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which an upper layer wiring is formed with an interlayer insulating film interposed on a lower layer wiring for connecting semiconductor elements. It relates to evaluation technology.

[0002]

2. Description of the Related Art In order to improve the reliability of a semiconductor integrated circuit device, the cause of a defect (or failure) occurring at each stage of its development, design, trial manufacture, production, use, etc. is investigated and countermeasures are taken. This is very important. In order to investigate the cause of such a defect, it is necessary to evaluate the electrical characteristics of the semiconductor elements constituting the circuit system mounted on the semiconductor integrated circuit device. This electrical characteristic evaluation is generally performed by the following method.

First, an opening is formed in the interlayer insulating film to expose a part of the surface of the wiring connecting the semiconductor elements. This opening may, for example focused ion beam (FIB: F ocused I on
B eam) method.

Next, a conductor connected to the surface of a part of the wiring is formed in the opening, and an inspection electrode pad connected to the conductor is formed on the interlayer insulating film. The conductor and the inspection electrode pad are, for example, laser C.
It is selectively formed in VD (C hemical V apor D eposition ) process.

Next, the surface of the inspection electrode pad is contacted with a probe needle or irradiated with an electron beam to evaluate the electrical characteristics of the semiconductor element. This makes it possible to investigate the cause of the defect caused by the semiconductor element (defect analysis).

[0006]

In recent years, semiconductor integrated circuits
The device wiring structure tends to be multi-layered as the integration becomes higher.
It For example, a bipolar flip-flop circuit
SRAM having a memory cellStaticRandom
AccessMemory) has a four-layer wiring structure
It Between the semiconductor elements in the memory cell is the first wiring layer.
An in-cell wiring and a word line for connecting to each other are formed. Second
In the wiring layer of the first layer, the first backing wiring (shunt
Wiring) and potential supply for supplying intermediate potential to memory cells
Wiring is formed. Complementary data is provided on the third wiring layer.
A line (complementary digit line) is formed.

On the fourth wiring layer, a second backing wiring for word lines and a backing wiring for potential supply wiring are formed. That is, on the intra-cell wiring that connects the semiconductor elements of the memory cell, each wiring formed in the upper wiring layer is dense.

Therefore, in the semiconductor integrated circuit device having the multilayer wiring structure, the evaluation electrode pad cannot be electrically connected to the wiring connecting the semiconductor elements, and the electrical characteristics of the semiconductor element must be evaluated. Therefore, it is impossible to investigate the cause of the defect due to the semiconductor element (defect analysis).

An object of the present invention is to provide a technique for evaluating a semiconductor integrated circuit device in which an upper layer wiring is formed on a lower layer wiring for connecting semiconductor elements with an interlayer insulating film interposed therebetween. It is to provide a technology capable of conducting investigation (defect analysis).

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In a method of evaluating a semiconductor integrated circuit device in which an upper layer wiring is formed with an interlayer insulating film interposed on a lower layer wiring connecting between semiconductor elements, a step of removing the upper layer wiring and an opening in the interlayer insulating film. And exposing a part of the surface of the lower layer wiring, and forming a conductor electrically connected to a part of the surface of the lower layer wiring in the opening, and on the interlayer insulating film. Forming an evaluation electrode pad electrically connected to the conductor, and abutting a probe needle or irradiating an electron beam on the surface of the evaluation electrode pad to evaluate the electrical characteristics of the semiconductor element And stages.

[0013]

According to the above-mentioned means, since the evaluation electrode pad can be electrically connected to the lower layer wiring, the electrical characteristics of the semiconductor element can be evaluated. As a result, it is possible to investigate the cause of the defect caused by the semiconductor element (defect analysis).

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment in which the present invention is applied to an SRAM (semiconductor integrated circuit device) evaluation technique. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 (equivalent circuit diagram) shows the configuration of the memory cell of the SRAM which is an embodiment of the present invention.

As shown in FIG. 1, the memory cell M of the SRAM has a word line WL, a potential supply wiring Ist, and a data line D.
It is arranged at the intersection of L1 and the data line DL2. A plurality of the memory cells M are arranged in a matrix along the extending direction of each of the word line WL and the data line DL1.
Of the memory cell array.

The memory cell M is composed of, for example, a bipolar flip-flop circuit.

This bipolar flip-flop circuit has four bipolar transistors (semiconductor elements) T.
r, four resistance elements (semiconductor elements) R, two Zener diode elements (semiconductor elements) D, and two capacitance elements (semiconductor elements) C.

The SRAM has a four-layer wiring structure, for example. In the first wiring layer on the memory cell M, as shown in FIG.
As shown in (plan view), the in-cell wiring 3 and the word line WL that connect the semiconductor elements in the memory cell M are formed. As shown in FIG. 3 (plan view), an intermediate potential is supplied to the second back wiring layer (shunt wiring) 5 of the word line WL and the memory cell M to the second wiring layer on the memory cell M. The potential supply wiring Ist is formed. In the third wiring layer on the memory cell M, as shown in FIG. 4 (plan view),
The data line DL1 and the data line DL2 are formed. In the fourth wiring layer on the memory cell M, the second word line WL
The lining wiring 6 and the lining wiring 7 of the potential supply wiring Ist are formed. That is, on the intra-cell wiring 3 that connects the semiconductor elements of the memory cell M, each wiring formed in the upper wiring layer is dense.

Each of the in-cell wiring 3 and the word line WL is shown in FIG. 6 (a sectional view taken along the line AA shown in FIG. 3).
As shown in FIG. 3, the interlayer insulating film 2 insulates and separates from the semiconductor substrate 1. The first backing wiring 5 and the potential supply wiring Ist are insulated and separated from the in-cell wiring 3 and the word line WL by the interlayer insulating film 4. The data line D
Each of the L1 and the data line DL2 is an interlayer insulating film (not shown)
Thus, the first backing wiring 5 and the potential supply wiring Ist are insulated and separated from each other. Each of the second backing wiring 6 and the backing wiring 7 is formed of an inter-layer insulating film (not shown) to form a data line D.
It is electrically isolated from each of the L1 and the data line DL2.

Next, a method for evaluating the electrical characteristics of the semiconductor element that constitutes the memory cell M of the SRAM will be described with reference to FIGS. 7 to 9 (cross-sectional views for explaining the method for evaluating the electrical characteristics).

First, as shown in FIG. 7, an upper layer first backing wiring 5 and a potential supply wiring Ist formed with an interlayer insulating film 4 interposed on a lower layer in-cell wiring 3 connecting between semiconductor elements. For example, it is removed by a polishing method or a wet etching method. In removing the wiring, the wiring formed in the fourth wiring layer and the wiring formed in the third wiring layer are also removed.

Next, an opening 4A is formed in the interlayer insulating film 4 to expose a part of the surface of the in-cell wiring 3. This opening 4
A is selectively formed by the focused ion beam method, for example.

Next, the in-cell wiring 3 is placed in the opening 2A.
A conductor 8A electrically connected to a part of the surface is formed, and an evaluation electrode pad 8B electrically connected to the conductor 8A is formed on the interlayer insulating film 4. Each of the conductor 8A and the evaluation electrode pad 8B is selectively formed by, for example, a laser CVD method.

Then, the surface of the evaluation electrode pad 8B is irradiated with a probe needle or an electron beam, and the memory cell M is exposed.
The electrical characteristics of the semiconductor element are evaluated.

In this way, the backing wiring (upper layer wiring) 5 and the potential supply wiring (upper layer wiring) with the interlayer insulating film 4 interposed on the in-cell wiring (lower layer wiring) 3 connecting the semiconductor elements of the memory cell M. In a method for evaluating an SRAM (semiconductor integrated circuit device) having Ist formed therein, the step of removing the backing wiring 5 and the potential supply wiring Ist, the opening 4A is formed in the interlayer insulating film 4, and the cell wiring 3 is formed. Exposing a part of the surface and forming a conductor 8A electrically connected to a part of the surface of the in-cell wiring 3 in the opening 4A, and forming the conductor on the interlayer insulating film 4. 8A for forming the evaluation electrode pad 8B electrically connected to the memory cell M, and the surface of the evaluation electrode pad 8B is contacted with a probe needle or irradiated with an electron beam to electrically connect the semiconductor element of the memory cell M. The stage of characterization Since the evaluation electrode pad 8B can be electrically connected to the in-cell wiring 3 by including, the electrical characteristics of the semiconductor element of the memory cell M can be evaluated. As a result, the cause of the defect due to the semiconductor element of the memory cell M can be investigated (defect analysis).

The opening 4A may have a structure inclined with respect to the surface of the in-cell wiring 3, as shown in FIG. 10 (cross-sectional view).

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device having a multilayer wiring structure having a logic circuit.

[0030]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In the evaluation technique of a semiconductor integrated circuit device in which an upper layer wiring is formed with an interlayer insulating film interposed on a lower layer wiring connecting between semiconductor elements, the cause of the defect caused by the semiconductor element is investigated (defect analysis). It can be carried out.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a SRAM memory cell according to an embodiment of the present invention.

FIG. 2 is a plan view of a first wiring layer on the memory cell.

FIG. 3 is a plan view of a second wiring layer on the memory cell.

FIG. 4 is a plan view of a third wiring layer on the memory cell.

FIG. 5 is a plan view of a fourth wiring layer on the memory cell.

6 is a cross-sectional view taken along the line AA shown in FIG.

FIG. 7 is a sectional view for explaining a method of evaluating the SRAM.

FIG. 8 is a sectional view for explaining a method of evaluating the SRAM.

FIG. 9 is a sectional view for explaining a method for evaluating the SRAM.

FIG. 10 is a sectional view showing a modified example of the present invention.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Interlayer insulating film, 3 ... In-cell wiring, W
L ... Word line, 4 ... Interlayer insulating film, 5 ... First lining wiring of word line, Ist ... Potential supply wiring, DL1 ... Data line, D
L2 ... Data line, 6 ... Second backing wiring of word wiring, 7
... Backing wiring for potential supply wiring, 8A ... Conductor, 8B ... Electrode pad for evaluation.

Claims (3)

[Claims] 1. A method for evaluating a semiconductor integrated circuit device in which an upper layer wiring is formed with an interlayer insulating film interposed on a lower layer wiring connecting between semiconductor elements, the step of removing the upper layer wiring, and the interlayer insulating film. Forming an opening in the opening to expose a part of the surface of the lower layer wiring, and forming a conductor electrically connected to a part of the surface of the lower layer wiring in the opening, and the interlayer insulating film. Forming an evaluation electrode pad electrically connected to the conductor, and contacting a probe needle on the surface of the evaluation electrode pad or irradiating with an electron beam to evaluate the electrical characteristics of the semiconductor element. A method of evaluating a semiconductor integrated circuit device, the method comprising: 2. The method for evaluating a semiconductor integrated circuit device according to claim 1, wherein the opening is selectively formed by a focused ion beam method. 3. The method for evaluating a semiconductor integrated circuit device according to claim 1, wherein the conductor and the evaluation electrode pad are selectively formed by a laser CVD method.